WO2009046300A2 - Appareil de bus de données mésosynchrone et procédé de transmission de données - Google Patents

Appareil de bus de données mésosynchrone et procédé de transmission de données Download PDF

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Publication number
WO2009046300A2
WO2009046300A2 PCT/US2008/078752 US2008078752W WO2009046300A2 WO 2009046300 A2 WO2009046300 A2 WO 2009046300A2 US 2008078752 W US2008078752 W US 2008078752W WO 2009046300 A2 WO2009046300 A2 WO 2009046300A2
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WIPO (PCT)
Prior art keywords
data
node
clock
character
memory
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PCT/US2008/078752
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English (en)
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WO2009046300A3 (fr
Inventor
James H. Jones
Kevin D. Drucker
Jon C.R. Bennett
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Violin Memory, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Violin Memory, Inc. filed Critical Violin Memory, Inc.
Priority to CN2008801113298A priority Critical patent/CN101836193B/zh
Priority to JP2010528163A priority patent/JP2011502293A/ja
Priority to KR1020107009902A priority patent/KR101132321B1/ko
Priority to EP08836238A priority patent/EP2201463A4/fr
Publication of WO2009046300A2 publication Critical patent/WO2009046300A2/fr
Publication of WO2009046300A3 publication Critical patent/WO2009046300A3/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This application relates to the management of a distributed clock in a memory system.
  • the central processor accesses program information and data that is stored in a memory system.
  • a memory system There is a hierarchy of memory systems, in size, in speed and capacity that a computer systems architect selects during the design phase, which may comprise, for example, cache memory, main memory and secondary memory.
  • Cache memory is typified by low latency, high bandwidth and high cost per bit, and may be integral to the CPU.
  • Cache memory may be a semiconductor device and which may be, for example, SRAM (static random access memory).
  • Main memory which is also a semiconductor technology, and which is typically a form of DRAM (dynamic random access memory), is used for less frequently accessed data and program data.
  • personal computers may have up to about 4GB of DRAM, while high end servers may have about 16GB or more of DRAM.
  • Strategies such as using a plurality of memory controllers and computer cores may provide access to larger amounts of such memory; however, many of the computer bus systems have practical upper limits due to propagation time, bus loading, power consumption and the like.
  • Larger amounts of data may be stored on mass storage; for example, magnetic disks, where a single disk may contain a terabyte (TB) of memory, FLASH memory disks (sometimes called solid state drives - SSD), and clusters of disks may be used.
  • the access time for data stored on magnetic disks is significantly longer than that for data stored in main memory.
  • DRAM or other memory such as FLASH may be provided in memory appliances such as that described in US patent application Serial No.: 11/405,083, filed on April 17, 2006.
  • memory arrays may be considered as similar to main memory and provide rapid access to large amounts of data that would have otherwise been stored in mass storage, such as rotating disk media.
  • a data bus may be operated in a synchronous manner if the clock frequency for the transmission and reception of data is the same at all points in the system, and a known phase relationship exists between the data bits at each point where the data is to be sensed (e.g., received). However, considering the transmission of data in a parallel bus between two adjacent nodes, the phase relationship of the data bits in different lines changes, depending on the time-delay skew.
  • the data bits may be received in varying phase relationships to the system clock, and may be delayed by more than one clock interval, resulting in errors, or requiring de-skewing and phase alignment, typically at each memory node.
  • This problem may be mitigated by transmitting the clock and data on each of the lines, and recovering the clock for each channel at a node.
  • This clock differs in time delay with respect to the system clock from line-to-line.
  • transmission of data, or at least an idle data pattern may be required so as to maintain the synchronization of the clock for each line.
  • the data may be recovered at each node by accumulating the data for each line in a buffer, determining the time delay adjustment needed to compensate for the data skew, and reconstructing the data received at each node prior to acting on the data (where the word data is understood to include in-band commands such as read, write, and the like as well as information, which may include instructions, that is to be written to, or read from memory.)
  • the word data is understood to include in-band commands such as read, write, and the like as well as information, which may include instructions, that is to be written to, or read from memory.
  • the amount of data that must be buffered may be up to the number of clock cycles of skew that may accumulate along the bus.
  • a bus may also be operated as a multi-drop bus where the data is transmitted from a sending end (such as a memory controller) and received at a target memory module: for example the 3rd memory module along a linear bus.
  • the module may be a dual-in-line memory module (DIMM), as is known in the art, and the maximum total skew may be equal to that of the specific bus line having the longest transmission delay.
  • the transmission delays result from differences in trace lengths for the individual data lines, and the differences in trace lengths may include the traces on a mother board as well as the traces on the circuit card containing the memory module.
  • the total skew may limit the length of the bus or the signaling speed.
  • An interconnection system including a first node and a second node in communication with the first node.
  • a first clock is provided to the first node and the second node; and, a second clock is generated with reference to the first clock, having an first integral relationship to the first clock, and having a time delay offset with respect to the first clock adjusted such that the transmission time of bits between an output the first node and an output of the second node is maintained substantially constant.
  • a data transmission system including at least two modules connectable by a data bus.
  • a module has a transmitter for transmitting serial data, and a receiver for receiving serial data.
  • the module is supplied with a signal from a common clock, and has a clock generator producing an internal clock on the each module that is derived from the common clock.
  • a clock data recovery circuit produces a received data clock that maintains synchronism with the bits of the serial data signal, and an alignment buffer is operable to establish and maintain synchronism between the bits of the serial data and the internal clock.
  • a switch is operable to route the received serial data to one of an external port or an internal port.
  • the module may have a plurality of external and internal ports.
  • a memory system in another aspect, includes a plurality of modules, connected by links, and at least one module has a data memory.
  • a system clock is distributed to at least two modules, and a data clock rate of data being transmitted between modules is integrally related to the system clock.
  • a buffer on a module is operable to maintain synchronism between a bit position of a received data character and a previously established bit position.
  • a data interface includes a clock data recovery circuit; a clock phase alignment buffer, and a data transmission circuit.
  • the clock data recovery circuit recovers a clock having a same frequency as the clock used in the data transmission circuit, and the phase alignment circuit compensates for a change in a time-of-arrival of the data.
  • a memory module has a data receiver; a clock data recovery circuit, a routing switch, a memory interface, and a data transmitter.
  • the clock data recovery circuit recovers a clock having the same frequency as a clock used in the data transmission circuit, and the phase alignment buffer circuit compensates for a time-of-arrival of the data.
  • a node of an interconnection system includes a data receiving circuit; a data transmitting circuit; a switch connecting the data receiving and the data transmitting circuits.
  • a circuit is operable to maintain a sampling time in a fixed relationship to a first bit of a character of a received character having a plurality of bits; and an input data buffer is configured to resample the first bit so that an overall time delay measured between the resampled bit and a corresponding bit transmitted by another module is maintained substantially constant.
  • a method of transmitting data between modules comprising providing at least two modules, the modules including a receiver, a transmitter, a clock data recovery circuit, a phase alignment buffer, and a routing switch.
  • the modules are connectable by lines.
  • a character of a frame of data is assigned to a first line.
  • the first line at the receiving end thereof is initialized so that a first bit of a character is sampled so as to maintain the alignment of alignment of the sampling of the first bit of the character when a time delay between the transmitted character and the receipt of the character changes.
  • a method of managing an interconnection system is described, where the system includes a plurality of nodes in communication with each other.
  • the method includes transmitting a character of data comprising a plurality of bits from a first node to a second node; receiving the character at a second node; recovering a clock from the received data and aligning a sampling time to a first bit of the character; and, re-sampling the sampled data at a submultiple of the clock frequency and adjusting the phase or time delay of the resampling clock so that the overall time delay between the transmitted data and the resampled data is substantially constant.
  • FIG. 1. is a block diagram of a computer system having memory modules
  • FIGs. 2 (a) and (b) illustrate naming conventions for logical and physical aspects of the examples
  • FIG. 3 is a simplified block diagram of a memory module
  • FIG. 4 is a more detailed block diagram of the memory module of FIG.
  • FIG. 5 shows an example of the logical arrangement of data bits at the input and the output of a deserializer circuit
  • FIG. 6 illustrates an arrangement of functional elements in a switch of a memory module
  • FIGs. 7 (a) and (b) show the timing regimes associated with mesosynchronous operation.
  • the instructions can be used to cause a digital processor, or the like, that is programmed with the instructions to perform the operations described.
  • the operations might be performed by specific hardware components that contain hardwired logic or firmware instructions for performing the operations described, or by any combination of programmed computer components and custom hardware components, which may include analog circuits.
  • a microprocessor, a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) may be used.
  • Such circuits may have integral or associated memory to store any necessary instructions or data.
  • the methods may be provided, at least in part, as a computer program product that may include a machine-readable medium having stored thereon instructions which may be used to program a computer (or other electronic devices) to perform the methods.
  • machine-readable medium shall be taken to include any medium that is capable of storing or encoding a sequence of instructions or data for execution by a computing machine or special-purpose hardware and that cause the machine or special purpose hardware to perform any one of the methodologies or functions of the present invention.
  • the term “machine-readable medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical and magnetic disks, magnetic memories, optical memories, and carrier wave signals.
  • carrier wave signals is understood to encompass the electronics and instructions needed to generate or receive electrical signals having instructions or data imposed thereon, whether such signals are conducted or radiated.
  • a machine readable medium may include read-only memory (ROM); random access memory (RAM) of all types (e.g., SRAM, DRAM); programmable read only memory (PROM); electronically alterable read only memory (EPROM); magnetic random access memory; magnetic disk storage media; flash memory; and, transmission using electrical, optical, acoustical or other forms of signals.
  • ROM read-only memory
  • RAM random access memory
  • PROM programmable read only memory
  • EPROM electronically alterable read only memory
  • magnetic random access memory magnetic disk storage media
  • flash memory flash memory
  • the example may include a particular feature, structure, or characteristic, but every example may not necessarily include the particular feature, structure or characteristic. This should not be taken as a suggestion or implication that portions of the features, structure, or characteristics of two or more examples should not or could not be combined, except when such a combination is explicitly excluded.
  • a particular feature, structure, or characteristic is described in connection with an example, a person skilled in the art may give effect to such feature, structure or characteristic in connection with other examples, whether or not explicitly described.
  • a connector or connector interface as described herein is not limited to physically separable interfaces where a male connector or interface engages a female connector or interface.
  • a connector interface also includes any type of physical interface or connection, such as an interface where leads, solder balls or connections from a memory circuit are electrically connected to another memory circuit or a circuit board.
  • a number of integrated circuit die e.g., memory devices, buffer devices, or the like
  • the memory devices and buffer device may be interconnected via a flexible tape interconnect and interface to a memory controller through one of a ball grid array type connector interface or a physically separable socket type connector interface.
  • Connection types may include the interface between integrated circuit chips, interconnection conductors on a substrate, between substrates, or on printed circuit boards, or the like.
  • the apparatus and techniques described herein may be used for a data communication system where the modules are physically separated, and where data transmission techniques using wireless technologies, or the like, may be used in whole or in part.
  • a plurality of memory modules may be fabricated or assembled on a common substrate, including the interconnections therebetween. The choice of physical embodiment depends on engineering and economic consideration at the time a product is designed.
  • FIG. 1 shows an example of a system including a central processing unit (CPU), a memory controller (MC), and memory module (MM) and a system clock (SYSC).
  • CPU central processing unit
  • MC memory controller
  • MM memory module
  • system clock system clock
  • the system may have volatile and non- volatile memory such as RAM and FLASH attached for rapid access to program instructions and data to be used or manipulated by the programs.
  • This memory may be connected to the CPU by a memory controller MC and include a plurality of memory modules MM.
  • the memory modules may be connected to each other and the memory controller by a plurality of electrical connections, printed wiring connections, or lines, which are often collectively called a bus, line, or channel.
  • some memory modules MM are shown as being serially connected, such as MMl to MM2 and some MM being connected in a branching arrangement, such as MM2 to MM3 and MM4.
  • a system clock In a mesosynchronous system, a system clock (SYSC) is distributed to modules (for example, MM) in a domain so that a plurality of modules of a group of modules may have access to a clock source of a common frequency.
  • Various clock frequencies may be derived from SYSC which may be multiples or submultiples of the SYSC clock frequency.
  • the clocks throughout the system of a particular multiple or submultiple of the SYSC clock frequency have the same frequency, but may differ in time or phase offset from each other.
  • This offset may be described in fractions of the clock period, or as a phase offset, where 0, 90, 180, 270 degrees of phase correspond to 0.0, 0.25, 0.5, and 0.75 of the clock period.
  • the offset may vary slowly with time due to temperature or circuit aging. Slowly will be understood to mean that a multiplicity of characters may be transmitted before a sufficient change in offset occurs that may need a change in a compensation or alignment.
  • FIG. 2 serves to define the conventions used in the description of the connections, or bus, between two devices, which may be, for example, two memory modules MM. Data may be said to flow in an upstream or downstream direction, where upstream is conventionally defined as being towards the end of a channel having a management interface, such as a memory controller MC or a CPU, and downstream is the opposite direction.
  • a bus may be reconfigurable so that an upstream direction becomes a downstream direction. Other terms such as northbound and southbound may be used.
  • a bus, link, or channel connects the two devices for the purposes of high speed data, address and command transmission. While there are many configurations of channels, typically the channel may have a group of lines, which may use unipolar, bipolar, or differential signaling technology. The lines may be unidirectional or bi-directional.
  • a differential line is used, which may include a pair of traces on a motherboard, terminated at a memory module in a differential signaling electronic circuit, as is known in the art. (The electrically differential line is shown as a single line in the drawings.) At present, this type of connection is being used for high-speed interfaces in contemporary product design, but any type of connection may be used, including optical or wireless techniques, and the like.
  • the channel may have a unidirectional group of lines.
  • ten unidirectional lines are provided of which nine may be in use at any time, and the tenth line may be a spare. Other numbers of lines and spares may be used.
  • a spare line is not required.
  • Data may be transmitted over the channel in the form of characters which may be of a fixed length in clock cycles, and a data bit of the character may be associated with a clock cycle. In this example, a 20 bit character length is used, associated with 20 clock cycles.
  • the characters on a plurality of lines may be grouped into logical clusters and called frames. That is, as shown in FIG.
  • a character on each of the active lines may be associated with a character on another line that is being transmitted contemporaneously with the other character(s).
  • the characters on individual lines need not be bit- synchronized with each other in time, and may be offset from each other in time by one or more bit periods, and the clock offset may include fractional bit periods.
  • the transmission of data between a first module and a second module may be controlled at the transmitting module and the receiving module can accept the data at the mesosynchronous clock data rate.
  • a similar channel may exist in the reverse direction.
  • the direction of signal propagation will be described as in the downstream direction; however, it will be appreciated that signal propagation in the upstream direction will have similar characteristics.
  • a character from an upstream device, such as a MC or MM to a downstream device, such as a MM may be termed a hop.
  • a hop In this discussion, for clarity, the transmission of data is between two memory modules MM, without loss of generality.
  • line or lines is usually used when describing the physical nature of the connection between two modules in a hop, and these lines may be associated with, for example, traces on a printed circuit board, ancillary components such as connectors, and the sending and receiving end interface electronics.
  • the term lane is usually used to represent the logical assignment of data of a character in a frame.
  • Each of the lanes may be assigned (or "bound") to a line by operation of the MC, MM or the like, and this binding may change from hop-to-hop, and may change with time.
  • the binding is considered to be static once the system is configured, but may be different at each module. That is, the association of a lane with a line in each hop is established at a prior time of system configuration, and remains in the assigned state for the duration of operation, or until a reconfiguration is performed. Lanes may be bound to different lines in different hops so as to manage, and perhaps to reduce or minimize, the skew between the arrival time of characters in a frame at a destination module.
  • a channel or link between two modules may be considered to exist when the modules have been initialized, and been trained, and where lanes have been bound to lines and a process of frame alignment has been completed. This process may be called configuration.
  • a group of lines exiting from a module in the downstream direction connecting with another module by a hop is called an output sub-port and the entry of such lines into the another module is through an input sub-port.
  • Another similar group of lines, configured as sub-ports, may exist in the upstream direction, and the combination of the output and input sub-ports associated with the hop between two modules may be termed a port.
  • a character in a data frame may include steering data, and this generally means the addressing information needed to route the data in a frame, which may be the present frame or another frame on another line or a subsequent frame on the present line, to a destination module. This may be steering data such as is described in US Serial 11/405,083. Other means of providing addressing or routing of the data are known by persons of skill in the art and may be used.
  • the same lane or a plurality of lanes, which may not include the steering lane, may contain characters for commands, addresses, or data.
  • FIG. 2b is an example of the physical interface between two modules, which may be memory modules MM. Pairs of traces on a motherboard may connect between connectors on the mother board. Single or multiple connectors may be used so that the MM may plug into a motherboard and connect to printed circuit wiring. Other connections such as, for example, power, power management, clock and test may also be present, but are not shown.
  • FIG. 3 shows a simplified block diagram of a memory module, showing only the downstream path.
  • An input port P 0 has n data lines, in this example 10.
  • the input data at port P 0 is routed to one of the memory in the MM or to port P 1 or port P 2 , depending on the information provided in the steering data, or by other routing methods.
  • a memory which may be integral to the MM or in communication with the MM, and which may be any of the types of data memory that have been previously mentioned.
  • the memory may be replaced or supplemented by an interface to other computer or communications equipment, or other external device, so that a memory address may, for example, result in the input or output of data from the MM to a display, network interface, or the like.
  • the device performing the routing and other related functions may be called a configurable switching element (CSE).
  • FIG. 4 shows portions of the CSE.
  • the MM circuits may operate at several different clock rates. Multiple clock rates may facilitate the electronic implementation of the system; however, providing that sufficiently fast electronic components can be obtained, all of the operations of the CSE may be performed at a common clock speed, and that clock speed my be that of the bus data rate.
  • the system clock SYSC may be distributed from a common clock (SYSC) to each of the modules for which the system clock SYSC is used.
  • the system clock (SYSC) rate may be other than the bit clock rate of the serial bit data on the lines of a hop, and clock-rate multipliers or dividers, as are known in the art, may be used at the modules, or elsewhere, so as to derive local clocks.
  • the serial bit rate clock may be a multiple, m, or a submultiple of the system clock SYSC, and portions of the MM may operate at another clock rate: for example; a switch clock rate (SWC).
  • SWC switch clock rate
  • the data rate clock rate DC is 16 times the SYSC
  • SWC switch clock rate
  • Other clock frequencies may also be used in the module.
  • Some of the clocks used may not be integrally related to the SYSC.
  • One of the lines connecting modules MM is discussed as being representative of the process used on the other lines.
  • the input line at port P 0 may be received by, or interfaced to, an analog circuit that may provide impedance matching, which may include explicit or intrinsic bandwidth filtering, and which may convert the differential signal on the line into an electrical signal suitable for further data processing or manipulation.
  • impedance matching which may include explicit or intrinsic bandwidth filtering, and which may convert the differential signal on the line into an electrical signal suitable for further data processing or manipulation.
  • an output signal from the receiver circuit (RX) is processed by a clock data recovery (CDR) circuit.
  • a deserializer (DES) may be used to convert the data from a serial format to a plurality of data streams so that the data may be processed in parallel at a lower clock rate SWC, such as may be used in the switch circuitry (SW).
  • the CDR circuit may be one of a number of circuit types known in the art as a DLL (delay locked loop), or a PLL (phase locked loop), or the like, so as to establish a recovered data clock (RDC) having a fixed relationship with respect to a bit position in the data being received.
  • DLL delay locked loop
  • PLL phase locked loop
  • the recovered data clock RDC may be used to sample the signal on the line at a point in time of the received bit where the data signal is valid. That is, the time of sampling of the received data signal is aligned so that the data sample is not taken on the boundary between bits, and where the effects of distortions that may have occurred in transmission on the hop are a minimum.
  • the RDC may also be aligned with a character boundary at the time of initialization.
  • the recovered data-rate-clock may be offset from a locally generated data clock (DC) by a phase offset (or at least a fractional bit time) that is due to the different propagation paths taken by the clock signal SYSC from the common system clock to different modules, differential time delays in the modules, and by the differing signal propagation delays for different lines between adjacent modules.
  • the difference in propagation delay time between modules may be termed a skew, and the skew may have both fixed and variable components.
  • the additional propagation time differential delays experienced by each path on the module is also relevant and, when skew is described, the total differential time delay is meant, unless specifically otherwise characterized.
  • the propagation time between modules may include the propagation time of the signals along the traces on the mother board, which may at a speed greater than about half the velocity of light, and the propagation delays in the filters of the transmitter TX of the previous module and the receiver RX of the present module and in digital buffers, or the like.
  • Practical analog electronic circuits have finite bandwidths, and such circuits operating near a bandwidth limit may result in additional propagation delay in processing signals.
  • the propagation delay may be thought of as either a phase delay or a time delay.
  • Analog circuits may have time delays of the order of a clock period, and the delay may be a function of the component values, which may be temperature dependent. Some ageing may occur, but this is generally on a long time scale. So, therefore, the phase or time relationship between the incoming first bit of a character and a corresponding module clock edge may not be known a priori.
  • a time scale for the variation of skew or propagation in a fixed circuit configuration is described, a long time is understood to mean that the time scale of the variation is greater than a small multiple of the character duration at the clock rate.
  • An alignment of the clocks and the data may be made during a configuration process, and may use training characters to establish a relationship between a character or frame boundary, the signal valid window, and the RDC, for each line. Once established, the relationship is maintained by the DLL or the PLL, and the RDC may also used to clock a deserializer (DES).
  • the DLL or PLL may be updated by the CDR circuit so that the sampling point is maintained with a valid data window, even if the propagation time delay of the hop changes, for example, due to environmental factors (usually temperature). That is, the association between the specific clock bit in the recovered data clock (RDC) at a module for a line and the Oth bit of the character remains unchanged even when the time delay on the hop varies.
  • the DDL or PLL may not be continuously updated.
  • a periodic synchronization transmission may be initiated to adjust the RDC to maintain the association.
  • FIG. 5 An example of the conversion of a serial data stream, which may represent the bits of character on a line to a plurality of parallel data streams which may be processed locally at a lower data rate, is shown in FIG. 5.
  • the character (20 bits in this example) is processed by the deserializer (DES) at the recovered data clock rate (RDC) and routed within the module at clock rates of one half and one quarter of the line data rate.
  • RRC recovered data clock rate
  • SWC switch clock rate
  • Other logical assignments of the data to the lower- clock-rate portions of the processing are equally possible.
  • the data of a character is not completely deserialized.
  • a phase alignment buffer is used to align the output of the deserializer (DES) with the internal switch clock (SWC).
  • the switch rate clock is shown as being distributed from the switch SW as SWC 1 and SWC 11 to connote that the SWC used for the PABs at the input and the output of the switch have clock rates that are both the same frequency as that of the SWC, but may each have a different but substantially fixed phase or time offset from the SWC used in the switch (SW) itself.
  • the bit length of the PAB may be less than a character, and when a routing scheme described in US 11/405,083 is used, the routing information may be obtained before a complete character is received by the receiving module.
  • the PAB length may be less than 18 bits and may be 5 bits in length.
  • the character is deserialized into four packets of five data bits, and the clock rate SWC is one fourth of the DC.
  • the PAB may act so that the 0 th bit of the input character is aligned with a leading edge of the SWC.
  • Subsequent bits of the deserialized data of the character (the 1st, 2nd and 3rd) may be aligned with relative phases of the SWC (90, 180 and 270°), respectively.
  • Subsequent bits of the character, which follow in time may be processed similarly.
  • the packet may be processed by the switch (SW) so as to route the packet to a memory, or to one of the output ports P 1 , P 2 .
  • This routing may be dynamic, based on a received steering data character.
  • the switch may perform a lane exchange by, for example, transferring an input character on line 1 of P 0 , to an output line 3 on P 1 .
  • the logical lane to physical line association may be static in nature, and the process may be called "binding".
  • binding an input character may be routed along a path to a memory location, or to another module, and the assignment of lanes to lines may be used, for example, to manage the differential skew between characters of a frame at the destination module.
  • the term spare line is used to designate any line connecting two ports that is not presently bound to a lane.
  • An interface between the switch (SW) and an on-module memory may be similar to a module-to-module interface, and provide for the reception of characters in a packet that are intended to be to or from the local memory. This reception may include deskewing the characters within a frame and transferring the frame to the memory. Such local data recovery is described in patent application US Serial No.: 11/405,083.
  • the packets of the character are output as the input to an output phase alignment buffer PAB.
  • the output PAB serves to maintain the alignment of the 0 th bit of a character with the clock edge of the data clock DC at the output serializer SER that was established during the configuration process. Since the processing in the switch (SW) is a generally synchronous process, the skew between the switch clock (SWC) and the data clock (DC) tends to remain relatively static, once established. That is, the propagation delay time of a bit through the switch is substantially constant.
  • phase or relative time of the data input to the switch (SW) may differ for each line, with respect to the data clock (DC).
  • Output PABs may be used to align the bits of the character on a line with the appropriate clock cycle of the data clock (DC) for the line. This alignment is performed on a line-by-line basis, and the characters of a frame need not be resynchronized at each hop as they are processed separately.
  • the serializer then merges the bits of the packets of the character into a character having the same timing as a previously transmitted character on the line. That is, the association of bit 0 of the n th following character with a clock edge of the data clock DC delayed by 2On clock cycles from the 0 th bit of the previous character is maintained, where n is a positive integer. Thus, the timing of the characters is maintained even when there is no actual character being transmitted.
  • the output of the serializer (SER) may be converted to a differential analog data signal in the TX circuit for transmission on the next hop.
  • the other characters on the other lines in the frame are treated similarly.
  • each of the lines has a separate CDR circuit, and the RDC for each line may have different phases with respect to each other and with respect to the SWC.
  • the variation of the phase on each line may also have a different dependence on time or temperature, corresponding to the circuit details, such as line length, amplifier or filter characteristics, or the like.
  • FIG. 6 shows a simplified functional block diagram of the switch (SW).
  • the switch may be formed of two switches, a lane-exchange grid (LEG) and a port-exchange grid (PEG).
  • LEG lane-exchange grid
  • PEG port-exchange grid
  • the input lines (0-9) are associated with lanes (for example, A-J) where, such that, for example, lane A is associated with line 0 at the input.
  • the routing may be to output port Pi, for example, where lane A may be associated with, for example, line 3 at the output.
  • the binding, switching, or routing a character from an input line to an output line and port may be performed by the LEG and the PEG, respectively.
  • the binding of remaining lines B-J to output lines 1-9 may be determined when the system is configured, so that each lane in the input frame is routed to a particular physical line at the output.
  • Lane A may be bound to another line as well. Binding may differ from port-to-port on a module, and may differ as between one module and another.
  • the result of this process may be to maintain the association of a bit (for example the 0 th bit) of a character transmitted by a memory controller MC to a same clock edge of the data clock DC, where the data clock is the data clock DC at any of the modules, even when the time delay of the transmission of data over the hops changes with time.
  • a bit for example the 0 th bit
  • the propagation delay time D 1 represents the propagation delay time between the output of module MM 1 and the output of module MM 2 . Maintaining this time a constant for each lane of data results in the established correspondence between a first bit of a character transmitted on a line and the clock edge of the DC being maintained the same as existed at the completion of the configuration process.
  • the delay D] may be considered to be a sum of the delays D 2 and D 3 , where D 2 may be the delay not associated with the switch (SW) and D 3 is the delay associated with the switch (SW).
  • Each of the delays D 2 and D 3 may vary with environment factors over time, however the effect of the changes in delay are compensated by the phase alignment buffer (PAB) so that the overall transmission time delay is substantially constant. This is shown in more detail in FIG. 7B.
  • PAM phase alignment buffer
  • Substantially constant is understood to mean that the circuits are adjusted so that, after synchronization, the overall transmission time of the first bit of a character does not change by more than a bit duration, without resynchronization.
  • the result of the arrangement described is that a full character or more may not need to be buffered at the input PAB of the MM in order to adjust for the change in delay of a hop.
  • the depth of the PAB may be approximately the variation of the skew over the operating temperature range for the line in the hop, rather than, for example, the total variation of skew over all of the lines of the hop.
  • the data may be positioned at a suitable point in the buffer for transfer between clock speed domains so that the data bit position is maintained in the buffer during the transfer period.
  • a result of the phase alignment buffer is that the overall time delay through the memory module may be optimized, taking account of the changes in the skew due to environmental factors.
  • the overall time delay between the MC and the destination module may be reduced, when compared with an approach which recovers the data of a frame at an intermediate module and performs deskewing by adding delays along the data path.
  • a delay may be added to one or more of the lines at a source or destination module in order to deal with the remaining skew, or may be added during configuration so as to optimize the overall skew.
  • the association which may be termed synchronization, of the data clock DC with the data of any line is maintained after the association has been established, and is maintained locally at a module pair, the data transmission on each line does not have to be continuous except when required for system bandwidth or latency performance reasons.
  • the lines are not needed, power can be removed from the transmitter and receiver components, as well as perhaps from portions of the CDR and other circuitry.
  • data is typically routed from an input port to either the local memory or one of the two output ports, at least one of the output ports may be shut down when not needed.
  • One of the lines in a group of lines of the sub-port may be maintained in an active state for purposes of signaling, such as alerting the remaining lines to a data frame in a previously inactive link, or to data being sent for refresh purposes.
  • a signal presence indicator may also be used, so that the presence on data on a line will activate the receiver and associated circuitry.
  • a line in steady- state operation, a line may be either active or inactive, and when the data line is active, data, where data may be steering data, a command (including addressing), data being stored or read, or a clock maintenance transmission, is being transmitted.

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)

Abstract

L'invention concerne un système de mémoire dans lequel la durée de transmission de données entre des modules de mémoire est gérée de sorte que le retard temporel global entre des points spécifiés dans le système de mémoire est maintenu constant. Chaque voie d'un bus multivoie peut être gérée séparément et une trame de données évaluée au niveau du module destinataire, sans nécessiter de correction de désalignement au niveau des modules intermédiaires. Le retard temporel de propagation de données à travers un module, qui peut comporter un commutateur pour dérouter les données, est réduit par l'actionnement du trajet des données à travers le module au niveau d'un ou plusieurs sous-multiples du débit de données sériel de bus et la sélection du point d'échantillonnage des données reçues de sorte que des variations de retard dues à des modifications de température ou au vieillissement sont absorbées.
PCT/US2008/078752 2007-10-05 2008-10-03 Appareil de bus de données mésosynchrone et procédé de transmission de données WO2009046300A2 (fr)

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CN2008801113298A CN101836193B (zh) 2007-10-05 2008-10-03 一种同步数据总线装置及数据传输方法
JP2010528163A JP2011502293A (ja) 2007-10-05 2008-10-03 メソシンクロナス・データ・バス装置及びデータ伝送方法
KR1020107009902A KR101132321B1 (ko) 2007-10-05 2008-10-03 중간동기식 데이터 버스 장치 및 데이터 전송 방법
EP08836238A EP2201463A4 (fr) 2007-10-05 2008-10-03 Appareil de bus de données mésosynchrone et procédé de transmission de données

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US60/997,899 2007-10-05

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CN108259134A (zh) * 2018-01-10 2018-07-06 上海灵动微电子股份有限公司 一种基于afp协议的数据传输方法
EP4016428A4 (fr) * 2019-08-21 2022-09-14 Huawei Technologies Co., Ltd. Dispositif et système de traitement de données

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CN108259134A (zh) * 2018-01-10 2018-07-06 上海灵动微电子股份有限公司 一种基于afp协议的数据传输方法
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CN101836193A (zh) 2010-09-15
JP2011502293A (ja) 2011-01-20
KR101132321B1 (ko) 2012-04-05
CN101836193B (zh) 2012-10-03
KR20100098596A (ko) 2010-09-08
EP2201463A2 (fr) 2010-06-30
WO2009046300A3 (fr) 2009-05-22
EP2201463A4 (fr) 2010-10-13

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