WO2009027488A1 - Structure de connexion à répartiteur de signalisation entrelacé pour composant haute fréquence, et composant haute fréquence comprenant cette structure - Google Patents

Structure de connexion à répartiteur de signalisation entrelacé pour composant haute fréquence, et composant haute fréquence comprenant cette structure Download PDF

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Publication number
WO2009027488A1
WO2009027488A1 PCT/EP2008/061345 EP2008061345W WO2009027488A1 WO 2009027488 A1 WO2009027488 A1 WO 2009027488A1 EP 2008061345 W EP2008061345 W EP 2008061345W WO 2009027488 A1 WO2009027488 A1 WO 2009027488A1
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Prior art keywords
signal
ground
conductors
connection conductors
terminal structure
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PCT/EP2008/061345
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German (de)
English (en)
Inventor
Harald Klockenhoff
Franz-Josef Schmueckle
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Forschungsverbund Berlin E. V.
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Publication of WO2009027488A1 publication Critical patent/WO2009027488A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1903—Structure including wave guides
    • H01L2924/19032—Structure including wave guides being a microstrip line type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1903—Structure including wave guides
    • H01L2924/19033—Structure including wave guides being a coplanar line type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the present invention relates to a connection structure for a high-frequency component such.
  • B a transistor or a diode and such a high-frequency component.
  • High frequency devices often can provide only a limited output power, which may be too low for certain applications such as radar or mobile base stations. Therefore, a plurality of high-frequency components are often connected in parallel to obtain an output of the entire arrangement which is higher than the output of each one of the high-frequency components. So z.
  • multiple field effect transistors such as high electron mobility transistors (HEMTs) or bipolar transistors such as heterojunction bipolar transistors (HBTs) are commonly connected to an input signal to allow greater output power.
  • HEMTs high electron mobility transistors
  • bipolar transistors such as heterojunction bipolar transistors (HBTs)
  • HBTs heterojunction bipolar transistors
  • a source circuit is used for this purpose. The sources of the transistors are grounded and the gates are connected to the input signal. The drains of the transistors then form the output of the overall arrangement (the same applies to bipolar transistors).
  • the overall arrangement is called a "multi-cell transistor.”
  • the feed structure distributes the signal to the individual cells at the input or
  • a feed line is used as the input conductor for the input signal between two groundplanes or ground planes.
  • the input conductor and the two ground planes lie in a wiring plane and are laterally spaced from each other such that the input conductor is electrically isolated from the two ground surfaces surrounding it on both sides.
  • the distances between the ground planes and the input conductor are kept as constant as possible to ensure uniform signal line properties along the propagation direction of the input signal.
  • This arrangement is generally referred to as "coplanar line” or English “coplanar waveguide” (CPW).
  • the two ground planes are omitted and functionally replaced by a ground plane or ground plane on the underside of the substrate.
  • a ground plane or ground plane on the underside of the substrate.
  • the entire underside of the substrate is metallized.
  • This arrangement is referred to as “microstrip line” or “microstrip”.
  • the ground plane is passed through metallized holes through the substrate, so-called “vias”, to the top of the substrate.
  • the individual transistors of the multi-cell transistor are arranged side by side transversely to the direction of the signal flow such that a respective source and drain region alternate. Between the source and drain regions, a gate electrode extending along the direction of propagation of the input signal is then arranged in each case, which is connected to the feed line. This gate electrode together with the underlying Semiconductor material and the adjacent drain and source surfaces of a transistor cell. Each source and each drain region thereby acts as the source and drain of two single transistors of the multi-cell transistor. Accordingly, a transistor cell with a signal and a ground terminal can be constructed internally as a double transistor, wherein then the gate electrode is divided into two within the transistor cell.
  • the active regions of the single transistors are formed in the semiconductor layer under the source / drain regions.
  • the current flow direction in the active regions is transverse to the propagation direction of the input signal.
  • materials for the active region in addition to silicon, in particular for high-frequency applications, preferably III-V matehals, such as, for example, are used.
  • the manifold transistor Since the manifold transistor is wider than the input conductor, the problem now is that the outer gates of the manifold transistor must be connected to the input conductor.
  • the T-structure in which the individual gates are connected to each other via a straight, lying transversely to the direction of propagation of the input signal conductors, or the tapered-manifold structure is used, wherein the connection structure has a tapered delta-shaped form ,
  • a corresponding connection structure is usually provided on the output side to connect the drains of the individual transistors to an output signal conductor.
  • the sources of the manifold transistor are in the source circuit
  • Multicell transistor uses a so-called source bridge that transversely extends to the propagation direction of the input signal from the first ground plane to the second across the individual transistors of the manifold and is on a higher wiring level or is realized as an air bridge.
  • the source bridge is arranged on both sides of the multi-cell transistor metallized holes with the ground plane contacted on the substrate bottom.
  • the actual power available at the output of a multi-cell transistor does not increase linearly with the number of individual transistors of the manifold transistor. Instead, the increase in output power for each additional single transistor becomes smaller and smaller. Likewise, the gain and the cut-off frequency of the multi-cell transistor decrease as the number of cells increases. As a result, the achievable maximum output power can not be increased beyond a certain extent by using a plurality of parallel-connected transistor cells. Likewise, other high frequency components can not be connected in parallel to any degree to increase the output power of the overall arrangement.
  • a first aspect of the invention accordingly provides a connection structure for a high-frequency component equipped with a plurality of signal terminals and a plurality of ground terminals.
  • the connection structure comprises at least one contact region, a connection region, a supply line, a first ground plane and a plurality of strip-shaped signal connection conductors which are electrically connected to the supply line.
  • a plurality of contacts in a first direction next to each other and spaced from each other.
  • the connection region adjoins the contact region in a second direction perpendicular to the first direction.
  • the feed line has a directional component along the second direction.
  • the longitudinal extension direction of each signal connection conductor in the connection region has a directional component along the second direction.
  • connection structure has a plurality of strip-shaped ground connection conductors which are electrically connected to the first ground plane.
  • the longitudinal extension direction of each ground connection conductor in the connection region has a directional component along the second direction.
  • the plurality of grounding conductors and the plurality of signal connection conductors are arranged side by side in the connection region in a projection in a plane spanned by the first and the second direction (projection plane).
  • no two of the plurality of signal connection conductors are arranged directly next to each other, meaning that at least one of the plurality of ground connection conductors is arranged between each directly adjacent pair of the plurality of signal connection conductors It has been found that such a connection structure is the one at the signal inputs of the
  • High frequency individual elements available input power particularly evenly distributed to the high-frequency single elements.
  • the signal flow direction is in the second direction when the terminal structure is connected on the output side, and opposite to the second direction when the terminal structure is connected on the input side.
  • the contact region has a plurality of contacts, which are preferably arranged on a straight line extending in the first direction. Accordingly, the contact area is defined by the contacts provided for connection of ground and signal as the area in which these contacts are located.
  • connection region In addition to the contact region in a second direction perpendicular to the first direction, the connection region is arranged in which the signal and ground connection conductors extend.
  • the ground connection conductors run in the connection region in such a way that they do not intersect any signal connection or distribution conductor.
  • the signal conductors run in the Connection area so that they do not cross a ground connection or distribution conductor.
  • the subject invention differs from the prior art, where the ground line is usually made only on a first-direction extending source bridge, which contacts the provided for ground terminal contacts in the vertical. According to the invention, however, the supply line of the mass as well as the supply of the signal from the adjoining the contact area terminal area and thus with a
  • Direction component made in or against the second direction.
  • the signal connection conductors are electrically connected to the supply line via a plurality of signal distribution conductors.
  • the electrical connection of the ground connection conductors to the first and possibly the second ground plane takes place via a plurality of ground distribution conductors.
  • These signal or ground distribution conductors may include branches and underpasses.
  • An underpass means the following: in the projection of the signal and ground distribution conductors onto the projection plane, the signal and ground distribution conductors running at different distances (heights) to the projection plane and not contacting each other intersect in the area of the underpass. It is irrelevant whether the respective signal distribution conductor or the respective ground distribution conductor in the region of the underpass has a greater or lesser distance from the projection plane.
  • the connection structure may be implemented in a coplanar waveguide variant, in which the supply line has a second ground area electrically connected to the plurality of ground connection conductors, and the first and second ground areas are arranged on respectively opposite sides next to the supply line and spaced therefrom.
  • connection structure may be embodied as a microstrip variant, in which the supply line is arranged on an upper side of a substrate and the first ground surface is arranged on an underside of a substrate.
  • connection structure may additionally be configured such that the plurality of ground connection conductors and the plurality of signal connection conductors between the first ground plane and the second ground plane are also arranged next to one another so that no two of the plurality of ground connection conductors are arranged directly next to one another.
  • the plurality of signal connection conductors comprise a total number n1 of signal connection conductors and the
  • Grounding conductors wherein the total number n1 of signal conductors is one greater than the total number m1 of grounding conductors.
  • this connection structure is combined with the aforementioned embodiments so that signal connection conductors and
  • Signal conductor is arranged directly between two ground connection conductors. Exceptions to this rule are only the two extremely arranged signal connection conductors, which are directly on their inner side next to a ground connection conductor and on its outer side are arranged next to one of the two ground planes.
  • the plurality of signal connection conductors preferably comprise a total number n2 of signal connection conductors and the plurality of ground connection conductors have a total number m2 of ground connection conductors, wherein the total number n2 of signal connection conductors is one less than the total number m2 of ground connection conductors.
  • signal connection conductors and ground connection conductors can alternate with one another such that each ground connection conductor is arranged directly between two signal connection conductors and each signal connection conductor directly between two ground connection conductors. Since no ground planes lying in the same plane as the feed line are provided in the microstrip variant, then the signal feed conductors arranged too highly are each arranged on both sides directly next to one of the ground connection conductors.
  • connection structure is formed symmetrically along an axis of symmetry extending in the second direction.
  • a high-frequency unit component receives the same proportion of the total available input power as another high-frequency unit element arranged symmetrically with respect to the symmetry axis, which results in an overall more uniform distribution of the input power.
  • the signal connection conductors preferably have no direction component in the first direction, so that the signal connection conductors run perpendicular to the first direction in which the contacts are arranged next to one another.
  • the signal connection conductors are then designed as metal strips running in the second direction.
  • the ground connection conductors preferably also have no direction component in the first direction.
  • the signal connection conductors and the ground connection conductors can be arranged in one plane. It is possible, but not required, for both signal connection conductors and ground connection conductors to lie in the same plane. It is much more conceivable that the signal connection conductors are arranged in a first plane and the ground connection conductors are arranged in a second plane lying above or below the first plane. The first and second planes are then preferably parallel to each other.
  • each radio frequency single element converts power dissipation into heat which must be dissipated across the substrate or via the source or emitter bridge (eg, in flip-chip mounting). Since the superposition of the power loss of the cells, the thermal load of the substrate in the environment of an internal high-frequency single element is greater than that of the environment of an external high-frequency single element, the resulting maximum temperature can be reduced by the area-related Power loss density is reduced to the center of the high-frequency device. This is done in this embodiment, by increasing the distances between adjacent high-frequency individual components to the center of the high-frequency component out.
  • a first distance of a second of the plurality of signal connection conductors to a third of the plurality of signal connection conductors immediately adjacent to the second of the plurality of signal connection conductors may be greater than a second distance of the third of the plurality of signal connection conductors to one of the third of the plurality of signal terminals Signal conductors directly adjacent fourth of the plurality of signal conductors.
  • a third distance of the fourth of the plurality of signal connection conductors to an axis of symmetry extending in the second direction is then greater than a fourth distance of the third of the plurality of signal connection conductors to the axis of symmetry.
  • the invention includes the realization that the distribution of the available input power to the individual high-frequency individual components connected in parallel can be influenced by the widths of the individual signal connection conductors and / or the widths of the ground connection conductors lying between the individual signal connection conductors and the distances between the directly adjacent ones Signal and ground connection conductors are varied.
  • reducing the width of a signal conductor relative to the width of the other signal conductors results in a reduced portion of the high frequency component connected to the signal conductor of reduced width is supplied to the stationary input power.
  • the same effect can be achieved for a high frequency single element device connected to a ground lead when the width of a ground lead is reduced or the distance between a signal lead and a ground lead disposed directly adjacent thereto is increased.
  • a fifth of the plurality of signal conductors to a directly adjacent second of the plurality of grounding conductors has a fifth spacing and a sixth of the plurality of signal conductors to a directly adjacent third of the plurality of grounding conductors has a sixth spacing different from the fifth spacing ,
  • a first width of a seventh of the plurality of signal connection conductors may differ from a second width of an eighth of the plurality of signal connection conductors.
  • a third width of a fourth of the plurality of ground connection conductors may differ from a fourth width of a fifth of the plurality of ground connection conductors.
  • connection structure In order to connect the ground connection conductors to the first and / or the second ground plane, it may be necessary to provide underpasses in which a ground connection conductor is carried out above or below a signal connection conductor.
  • a particularly preferred embodiment of the connection structure according to the invention provides a plurality of signal undercuts, wherein in one each supply path from the supply line to each of the plurality of signal conductors is arranged the same number of signal sub-paths of the plurality of signal sub-conductors.
  • a first length of a first of the plurality of signal conductors differs by less than 20 percent from a second length of a first one of the plurality of signal conductors directly adjacent to the first of the plurality of signal conductors grounding conductors.
  • the first of the plurality of signal connection conductors and the first of the plurality of ground connection conductors form a connection pair.
  • a further improvement may be achieved if the deviation is less than 10 percent, or even equal to the first length of the first of the plurality of signal leads of the second length of the first one of the plurality of ground lead conductors.
  • the first length of each one of the plurality of signal connection conductors differs in an advantageous embodiment of the connection structure by less than 20 percent of the second length of one immediately adjacent to the respective one of the plurality grounding conductor of signal conductors arranged in the plurality of grounding conductors.
  • a further improvement may be achieved if the deviation is less than 10 percent, or the first length of each of the plurality of signal leads of the second length of the ground lead disposed adjacent to each one of the plurality of signal leads is equal to the plurality of ground lead conductors.
  • the first length of each of the plurality of signal conductors may differ by less than 20 percent or less than 10 percent from the second length of each of the plurality of ground conductors. Also, an embodiment is provided in which the first length of each of the plurality of signal leads equals the second length of each of the plurality of ground lead conductors.
  • a second aspect of the present invention introduces a high frequency device having a plurality of signal inputs and a plurality of input side ground terminals, wherein the plurality of signal inputs and the plurality of input side ground terminals are juxtaposed so that no two of the plurality of signal inputs are directly juxtaposed ,
  • the high-frequency component comprises an input-side connection structure electrically connected to the plurality of signal inputs and the plurality of input-side ground connections via the contacts lying in the contact region according to the first aspect of the invention.
  • the high-frequency device may have a plurality of signal outputs and a plurality of output-side ground terminals, wherein the plurality of signal outputs and the plurality of output-side ground terminals are juxtaposed so that no two of the plurality of signal outputs are directly juxtaposed.
  • the high-frequency component has an output-side connection structure which is electrically connected to the plurality of signal outputs and the plurality of output-side ground connections via the contacts lying in the contact region according to the first aspect of the invention.
  • the first ground plane of the second connection structure can be electrically connected be connected to the first ground plane of the first connection structure or be identical to this.
  • the second ground plane of the second connection structure can then be electrically connected to or identical to the second ground plane of the first connection structure.
  • the high-frequency component particularly preferably comprises a plurality of transistors connected in parallel, in particular of field effect transistors (FETs) such as high electron mobility transistors (HEMTs) or of bipolar transistors such as heterojunction bipolar transistors (HBTs).
  • FETs field effect transistors
  • HEMTs high electron mobility transistors
  • HBTs heterojunction bipolar transistors
  • This high frequency device is referred to as a Plaited Signal Ground Manifold Transistor (PSG Manifold Transistor).
  • the plurality of signal inputs having a plurality of gate terminals of the plurality of parallel-connected transistors, the plurality of input-side ground terminals, and the plurality of output-side ground terminals having a plurality of sources (FIG. Emitter terminals) of the plurality of parallel-connected transistors and the plurality of signal outputs with a plurality of drain terminals (or collector terminals) of the plurality of parallel-connected transistors to be electrically connected.
  • FIG. 2 shows a multi-cell transistor with a tapered manifold structure
  • FIG. 6 shows a representation of the input power and output power (in dBm) of a PSG manifold transistor according to the invention
  • Fig. 7 shows a variant of the PSG Manifold transistor with shortened connection structure
  • FIG 8 shows a further embodiment variant of the PSG manifold transistor and a PSG manifold transistor optimized by adjusting the conductor widths of this variant embodiment.
  • Fig. 1 shows a multi-cell transistor of known design with source or ground bridge 3. The propagation direction of the input signal is in all
  • Partial image a) shows an isometric view of the complete multicell transistor.
  • a source bridge 3 extends over a plurality of juxtaposed parallel-connected individual transistors and connects a first ground plane 4a, the source terminals 5 of the individual transistors and a second ground plane 4b.
  • the first ground plane 4 a extends along the signal input 1 and the signal output 2 on the side shown in the sub-illustration on the top left, the second ground surface 4 b on the side shown in the bottom right part of the signal input and output.
  • the second partial image b) shows the ground surfaces 4a, 4b and the entire metallization, which is connected to the ground surfaces 4a, 4b. These are on the one hand the underpasses 6, 7 at the signal input 1 and signal output 2, which serve to suppress unwanted waves.
  • the source connections can be seen under the source bridge 3, which connect the source regions to the source bridge 3 and at the same time serve as pillars for the source bridge 3.
  • Part of Figure c) shows the signal input 1 and all metalizations associated with it, ie the T-shaped distribution structure and the individual gate fingers. 8
  • Part of Figure e) shows a section of the region of the source bridge 3 with the input and output side terminals.
  • subfigure f) is the Source bridge 3 not shown for better illustration. It can clearly be seen that the source regions and the drain regions of the individual transistors of the multi-cell transistor are alternately adjacent to one another, wherein a gate finger 8 lies between each sequence of drain-source and source-drain.
  • the investigations leading to the invention have shown that a significant disadvantage of the T-shaped distribution structure is due to the different distances that must cover the input signals of the respective individual transistors in order to achieve the respective individual transistor.
  • the path from the signal input to the gate of a single transistor becomes longer and longer the farther it is from the center of the multi-cell transistor.
  • the distance over which source terminal 3 supplies a single transistor to the bulk terminal for the source region becomes shorter, the farther the single transistor is removed from the center of the manifold transistor, which improves the uniformity of the distribution of the available input power over the single cells of the multi-cell transistor further deteriorated.
  • the various lengths can be represented as inductances of different sizes, via which the individual cells are connected to the signal input 1 or the ground surfaces 4a, 4b.
  • FIG. 3 shows a plot of the input and output power of a tapered manifold transistor versus the available source power (P SOURCE ) of a radio frequency source.
  • P SOURCE available source power
  • the figure illustrates the lack of uniformity of the distribution of the input power to the three individual transistors of the transistor on the basis of the three divergent input powers P
  • Single low power transistors at the source of the tapered manifold transistor are equal and approximately 10.3 dB.
  • the transistor cell starts with the largest input and saturate output power while the other transistor cells sequentially saturate at higher overall power. This leads firstly to the fact that the total power at about 17 dBm P SOURCE begins to go into saturation. Second, when the total saturation power is reached at about 28 dBm P SOURCE, the transistor cell that first saturates is so far in compression that significant harmonics arise, here on the order of 15 dBm.
  • FIG. 4 shows in four partial illustrations an embodiment of a plaited signal ground (PSG) manifold transistor according to the invention with a signal input 11 and a signal output 12.
  • the PSG manifold transistor has six signal connection conductors 15 and five ground connection conductors 16 on the input side are connected via gate fingers 18 as in the classical multi-cell transistor with the gates of two individual transistors, which are designed as a double transistor with a common drain region.
  • the signal connection conductors 15 are connected to the signal input 11 via signal distribution conductors 17.
  • the two source regions of a dual transistor are each connected to one of the ground connection conductors 16, which are also connected via ground distribution conductor 20 to the ground planes 14a, 14b. Passing across the PSG manifold transistor is a bridge 13 which conductively connects the ground planes 14a, 14b disposed on either side of the PSG manifold transistor.
  • the braided connection structure can clearly be seen in FIG The name "plaited signal ground” is derived and signal and ground leads alternate, and each ground lead 16 is connected to one or both of the ground planes 14a, 14b to provide underpasses at a plurality of locations where a signal conductor The vertical distance between the wiring planes is small, which is why a signal underpass is a capacitive load on the respective supply path, Therefore, the PSG connection structure shown in Fig.
  • Fig. 5 shows a comparison of the current density distribution between the individual transistors of the classical tapered-manifold transistor and the PSG manifold transistor.
  • the magnetic field strength which is directly dependent on the respective current flowing, applied over a cross-sectional line through the manifold transistor.
  • the classical tapered-manifold transistor dashed line
  • the two most isolated single transistors receive a significantly larger proportion of the input power than the individual transistors located further inside.
  • the proportion of the total input power decreases the further inside a single transistor lies.
  • Electromagnetic simulations have shown in the investigations that led to the present invention, that the magnetic Field strength on the outer sides of the signal lead and the Tapered- connection structure due to the proximity to the two ground planes is strongest, so there also flows the main part of the signal current, which is why the outer individual transistors receive a correspondingly a larger proportion of the input power.
  • the maximum for the outer transistors and the minimum for the inner transistors differ by about a factor of 2.5.
  • the solid line shows a much more uniform magnetic field strength distribution compared to the first for the PSG manifold transistor.
  • the maximum for and the minimum differ only by about a factor of 1, 3. In the variant shown here, the maximum is now even in the inner transistor cells.
  • the PSG Manifold can be set so that all cells with virtually identical power components are controlled. As a result, all individual transistors saturate at approximately the same input power, so that distortions can only be expected at higher powers of the PSG manifold transistor. In addition, due to the matched impedances of the individual supply paths and the thus adapted phase shifts, the output signals are superimposed in a better constructive manner, so that a higher total gain is to be expected. Another positive effect has the effect that due to the better current distribution, a relatively larger cross-sectional area of the electrical conductor is utilized for the signal line and therefore the resistance lining of the connection structure is smaller.
  • FIG. 6 is a plot of the input and output power of a PSG manifold transistor versus available source power (P SOURCE ).
  • P SOURCE available source power
  • the resulting harmonics are about 1 O dB lower than the comparison transistor in Fig. 3. It is also to be noted as a particular advantage that the gain of the overall arrangement at about 11, 5 dB by 1, 2 dB higher than the tapered manifold Transistor.
  • the PSG manifold transistor therefore offers higher gain, lower distortion, and higher summed linear output power over prior art multi-cell transistors, making it particularly interesting in radar signal power amplification.
  • the PSG manifold transistor's output power scales better with the number of single transistors than the traditional tapered manifold transistor due to the more uniform distribution of input power to the single transistors. In order to achieve greater output powers, therefore, a large number of individual transistors can be connected in parallel.
  • the two outermost transistors make the largest contribution to the output power and saturate early, while additional, internal transistors only make a small contribution to the output power total output power is low for each further single transistor.
  • the advantages of the PSG manifold transistor over the conventional manifold transistor for a larger number of single transistors connected in parallel in Manifold transistor always larger.
  • FIG. 7 shows in four sub-illustrations a variant embodiment of the PSG manifold transistor with a shortened connection structure. Corresponding elements are indicated in FIG. 7 by the same reference numerals as in FIG. 4, a repetition of a description takes place only where necessary.
  • a manifold transistor a large number of individual transistors can be interconnected.
  • the connection structure becomes deeper, the wider the manifold transistor to be contacted.
  • the individual supply paths have angles of less than ⁇ 135 degrees with respect to the axis of symmetry. The angles can be from ⁇ 135 degrees to ⁇ 90 degrees with respect to the axis of symmetry, which allows for different degrees of shortening of the connection structure.
  • Fig. 8 shows half of a symmetrical multi-cell transistor according to the invention with source bridge 13.
  • Main supply line are electrically connected. Accordingly, it is also possible to couple a larger number of Manifold transistors with terminal structures according to the invention by the
  • Supply lines of the individual Manifold transistors in turn via a Connection structure according to the invention are coupled to the main supply line. This results in a recursive self-similar structure.
  • the input signal is fed to the CPW terminal of the signal input 11.
  • the output is taken via a CPW (not shown) immediately following the drain 19 in its left corner.
  • the picture shows the basic circuit without observing the real dimensions.
  • the circuit is divided into four vertically successive levels.
  • the first level is the lower level, the vertical levels following are counted naturally.
  • the level 3 contains only feedthroughs (vias) 22, which are listed in part c).
  • the lower level 1 is shown in part c). It contains all ground connections, vias 21 to level 2 (signal conductor level) and vias 22 to level 4 (source bridge).
  • the level 2 (signal conductor level) is shown in part b). It contains the ground environment of the coplanar line 14a, the CPW signal conductor terminal 11 with the connected, triangular taper which feeds the gate fingers 18.
  • the ground fingers 23 each contact the top right of the
  • the drain terminal and its fingers 19 are in the same plane.
  • the level 4 contains the source bridge 13.
  • All ground lines and ground feedthroughs are isolated from the gate and drain lines.
  • the PSG connection structure can also be used on any other components transmit, process the signals of high frequencies and seek to achieve an increase in the output power or the maximum allowable current or other parameters by connecting a plurality of similar individual components in parallel.
  • An example of such other components are diodes.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Amplifiers (AREA)

Abstract

L'invention concerne une structure de connexion pour un composant haute fréquence doté d'une pluralité de bornes de signalisation et d'une pluralité de bornes de mise à la masse, ainsi qu'un tel composant haute fréquence. La structure de connexion comporte une pluralité de conducteurs de connexion de signalisation connectés électriquement à une ligne d'amenée et une pluralité de conducteurs de mise à la masse connectés électriquement à un premier et/ou à un second plan de masse. La pluralité de conducteurs de mise à la masse et la pluralité de conducteurs de connexion de signalisation sont disposés côte à côte de telle façon qu'aucun des conducteurs de connexion de signalisation ne soit placé directement à côté d'un autre conducteur de signalisation.
PCT/EP2008/061345 2007-08-31 2008-08-28 Structure de connexion à répartiteur de signalisation entrelacé pour composant haute fréquence, et composant haute fréquence comprenant cette structure WO2009027488A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE102007041974 2007-08-31
DE102007041974.2 2007-08-31
DE102008045240.8 2008-08-28
DE102008045240A DE102008045240A1 (de) 2007-08-31 2008-08-28 Plaited-Signal-Manifold-Anschlussstruktur für ein Hochfrequenzbauelement und ein solches Hochfrequenzbauelement

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WO2009027488A1 true WO2009027488A1 (fr) 2009-03-05

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110943281A (zh) * 2018-09-24 2020-03-31 恩智浦美国有限公司 馈送结构、包括馈送结构的电气部件以及模块

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19522364C1 (de) * 1995-06-20 1996-07-04 Siemens Ag Halbleiter-Bauelement
EP0725445A1 (fr) * 1995-02-06 1996-08-07 Nec Corporation Transistor à effet de champ en forme de peigne
DE19823069A1 (de) * 1997-09-29 1999-04-08 Mitsubishi Electric Corp Halbleiterbauelement
US20020180005A1 (en) * 2001-05-31 2002-12-05 Fujitsu Quantum Devices Limited Semiconductor device and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0725445A1 (fr) * 1995-02-06 1996-08-07 Nec Corporation Transistor à effet de champ en forme de peigne
DE19522364C1 (de) * 1995-06-20 1996-07-04 Siemens Ag Halbleiter-Bauelement
DE19823069A1 (de) * 1997-09-29 1999-04-08 Mitsubishi Electric Corp Halbleiterbauelement
US20020180005A1 (en) * 2001-05-31 2002-12-05 Fujitsu Quantum Devices Limited Semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110943281A (zh) * 2018-09-24 2020-03-31 恩智浦美国有限公司 馈送结构、包括馈送结构的电气部件以及模块
CN110943281B (zh) * 2018-09-24 2024-03-12 恩智浦美国有限公司 馈送结构、包括馈送结构的电气部件以及模块

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