WO2009010265A3 - Semiconductor substrate and method for producing a semiconductor component - Google Patents

Semiconductor substrate and method for producing a semiconductor component Download PDF

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Publication number
WO2009010265A3
WO2009010265A3 PCT/EP2008/005752 EP2008005752W WO2009010265A3 WO 2009010265 A3 WO2009010265 A3 WO 2009010265A3 EP 2008005752 W EP2008005752 W EP 2008005752W WO 2009010265 A3 WO2009010265 A3 WO 2009010265A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor
producing
base
membrane
semiconductor substrate
Prior art date
Application number
PCT/EP2008/005752
Other languages
German (de)
French (fr)
Other versions
WO2009010265A2 (en
Inventor
Joachim Burghartz
Original Assignee
Stuttgart Mikroelektronik
Joachim Burghartz
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stuttgart Mikroelektronik, Joachim Burghartz filed Critical Stuttgart Mikroelektronik
Publication of WO2009010265A2 publication Critical patent/WO2009010265A2/en
Publication of WO2009010265A3 publication Critical patent/WO2009010265A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments

Abstract

A semiconductor substrate for producing a semiconductor component comprises a base (31), produced of a first semiconductor material and having a first lattice characteristic, and a membrane (32) that is integral with the base and that is movably received relative to the base (31). The membrane (32) forms a surface on which a layer (38), produced of a second semiconductor material and having a second lattice characteristic, is arranged. The second lattice characteristic is different from the first lattice characteristic. In an embodiment of the invention, the membrane (32) has a central membrane zone (34) which is supported by the base (10) from below. The invention further relates to a method for producing a semiconductor component using a semiconductor of this type.
PCT/EP2008/005752 2007-07-16 2008-07-15 Semiconductor substrate and method for producing a semiconductor component WO2009010265A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102007034701.6 2007-07-16
DE102007034701.6A DE102007034701B4 (en) 2007-07-16 2007-07-16 Semiconductor substrate and method of manufacturing a semiconductor device

Publications (2)

Publication Number Publication Date
WO2009010265A2 WO2009010265A2 (en) 2009-01-22
WO2009010265A3 true WO2009010265A3 (en) 2009-04-09

Family

ID=39967203

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2008/005752 WO2009010265A2 (en) 2007-07-16 2008-07-15 Semiconductor substrate and method for producing a semiconductor component

Country Status (2)

Country Link
DE (1) DE102007034701B4 (en)
WO (1) WO2009010265A2 (en)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2650704B1 (en) 1989-08-01 1994-05-06 Thomson Csf PROCESS FOR THE MANUFACTURE BY EPITAXY OF MONOCRYSTALLINE LAYERS OF MATERIALS WITH DIFFERENT MESH PARAMETERS
US5294808A (en) * 1992-10-23 1994-03-15 Cornell Research Foundation, Inc. Pseudomorphic and dislocation free heteroepitaxial structures
US5461243A (en) 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
FR2774511B1 (en) 1998-01-30 2002-10-11 Commissariat Energie Atomique SUBSTRATE COMPLIANT IN PARTICULAR FOR A DEPOSIT BY HETERO-EPITAXY
US6498086B1 (en) * 2001-07-26 2002-12-24 Intel Corporation Use of membrane properties to reduce residual stress in an interlayer region
US20030122130A1 (en) 2001-12-27 2003-07-03 Motorola, Inc. Structure and method for fabricating semiconductor structures and devices utilizing the formation of a compliant substrate having a mechanical decoupling layer
DE102006013419B4 (en) 2006-03-14 2008-05-29 Institut Für Mikroelektronik Stuttgart Method for producing an integrated circuit

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
JONES A M ET AL: "Long-wavelength InGaAs quantum wells grown without strain-induced warping on InGaAs compliant membranes above a GaAs substrate", APPLIED PHYSICS LETTERS, AIP, AMERICAN INSTITUTE OF PHYSICS, MELVILLE, NY, vol. 74, no. 7, 15 February 1999 (1999-02-15), pages 1000 - 1002, XP012023230, ISSN: 0003-6951 *
ROMANOV S I ET AL: "GeSi films with reduced dislocation density grown by molecular-beam epitaxy on compliant substrates based on porous silicon", APPLIED PHYSICS LETTERS, AIP, AMERICAN INSTITUTE OF PHYSICS, MELVILLE, NY, vol. 75, no. 26, 27 December 1999 (1999-12-27), pages 4118 - 4120, XP012024346, ISSN: 0003-6951 *
SATO T ET AL: "FABRICATION OF SILICON-ON-NOTHING STRUCTURE BY SUBSTRATE ENGINEERING USING THE EMPTY-SPACE-IN-SILICON FORMATION TECHNIQUE", JAPANESE JOURNAL OF APPLIED PHYSICS, JAPAN SOCIETY OF APPLIED PHYSICS, TOKYO,JP, vol. 43, no. 1, 1 January 2004 (2004-01-01), pages 12 - 18, XP001191452, ISSN: 0021-4922 *
TOMMI SUNI ET AL: "Bonded thick film SOI with pre-etched cavities", MICROSYSTEM TECHNOLOGIES ; MICRO AND NANOSYSTEMS INFORMATION STORAGE AND PROCESSING SYSTEMS, SPRINGER, BERLIN, DE, vol. 12, no. 5, 1 April 2006 (2006-04-01), pages 406 - 412, XP019349563, ISSN: 1432-1858 *

Also Published As

Publication number Publication date
WO2009010265A2 (en) 2009-01-22
DE102007034701B4 (en) 2017-09-14
DE102007034701A1 (en) 2009-01-22

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