WO2009005477A1 - Séparation de dispositifs semi-conducteurs - Google Patents

Séparation de dispositifs semi-conducteurs Download PDF

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Publication number
WO2009005477A1
WO2009005477A1 PCT/SG2008/000238 SG2008000238W WO2009005477A1 WO 2009005477 A1 WO2009005477 A1 WO 2009005477A1 SG 2008000238 W SG2008000238 W SG 2008000238W WO 2009005477 A1 WO2009005477 A1 WO 2009005477A1
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WO
WIPO (PCT)
Prior art keywords
layer
epitaxial layers
substrate
etching
patterns
Prior art date
Application number
PCT/SG2008/000238
Other languages
English (en)
Inventor
Xuejun Kang
Shu Yuan
Jenny Lam
Shiming Lin
Original Assignee
Tinggi Technologies Private Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from SG200704890-3A external-priority patent/SG148895A1/en
Application filed by Tinggi Technologies Private Limited filed Critical Tinggi Technologies Private Limited
Priority to JP2010514706A priority Critical patent/JP2010532563A/ja
Priority to US12/667,418 priority patent/US8507367B2/en
Priority to CN200880023028XA priority patent/CN101743619B/zh
Publication of WO2009005477A1 publication Critical patent/WO2009005477A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1892—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof methods involving the use of temporary, removable substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate

Definitions

  • This invention relates to the separation of semiconductor devices and refers particularly, though not exclusively, to the separation of such semiconductor devices after removal of a sapphire substrate.
  • GaN semiconductor devices such as, for example, light emitting diodes (“LEDs”), laser diodes, photo detectors, transistors, switches, and so forth, are widely used in many applications.
  • Well known applications include, but are not limited to, traffic signals, mobile telephone display backlighting, liquid crystal display (“LCD”) back lighting, flash lights for cameras, and so forth.
  • the fabrication of gallium nitride semiconductors for use as LEDs, laser diodes or lighting gives relatively low productivity.
  • known techniques result in semiconductor devices with a light output that is not optimized.
  • those that form a second substrate have great difficulty managing the second substrate due to warping, and dicing through the second substrate, particularly after removal of the first substrate.
  • a method of fabricating semiconductor devices comprises providing a substrate with a plurality of epitaxial layers mounted on the substrate and separating the substrate from the plurality of epitaxial layers while the plurality of epitaxial layers is intact. This preserves the electrical, optical, and mechanical properties of the plurality of epitaxial layers.
  • a first stage of device isolation may be performed by trench etching.
  • Mesas may be formed sequent to separation of the substrate, the trench etching being along edges of each mesa.
  • the mesas may be formed in an area defined by the trench.
  • the trench etching may be through the epitaxial layer.
  • the method may further comprise pad etching. After pad etching a final stage of die isolation may be performed.
  • a photoresist layer may be applied to protect regions of an n-type layer of the plurality of epitaxial layers during the etching process.
  • a first insulating layer may be exposed around the mesa, and the photoresist layer may be removed.
  • a second insulating layer may be applied over the exposed surfaces of the first insulating layer, the sides of the epitaxial layers, and a center of the epitaxial layers. Pad etching may take place to remove at least a part of the second insulating layer to expose part of the surface of the epitaxial layers.
  • a further photoresist layer may be applied over exposed surfaces of the second insulating layer and the center of the exposed surface of the epitaxial layers leaving a gap for etching of the exposed surface of the epitaxial layers. Etching may take place through the gap to surface texture the exposed surface of the epitaxial layers.
  • the further photoresist layer may be removed.
  • a new photoresist layer may be applied. Etching may take place to expose ends of thick patterns.
  • an array of n-type ohmic contacts may be formed on the n-type layer.
  • the method may further comprise die separation as a final step in the process.
  • the method may further comprise: prior to separation of the substrate from the plurality of epitaxial layers, forming at least one seed layer on the plurality of epitaxial layers, and forming an outer layer on the at least one seed layer, the outer layer being relatively thick and being for at least one of: a structural support, a heat sink, a heat dissipater, a current dissipater, and as a terminal, for the semiconductor devices.
  • a p-type metal ohmic contact layer may be applied to a p-type layer of a plurality of epitaxial layers;
  • a layer of a dielectric may be applied over the p-type metal ohmic contact layer and the p-type layer;
  • the dielectric layer may be removed from above the metal ohmic contact layer
  • the at least one seed layer may be deposited on the dielectric layer and the metal ohmic contact layer.
  • the thick patterns may be applied to the at least one seed layer, the outer layer being formed between the thick patterns.
  • the dielectric may be an oxide or a nitride. Die separation may be a final step in the process.
  • a method of fabricating semiconductor devices comprises providing a substrate with a plurality of epitaxial layers mounted on the substrate and applying patterns. An outer layer is formed between the patterns.
  • the outer layer is at least 0.3 mm thick and is for at least one of: a new substrate, a structural support, a heat sink, a heat dissipater, a current dissipater, and as a terminal, for the semiconductor devices; and separating the substrate from the plurality of epitaxial layers.
  • the outer layer may be at least 1 mm thick or at least 2 mm thick.
  • the patterns may be of a material that does not adhere to the outer layer such that the outer layer does not require dicing for die separation.
  • the separating the substrate from the plurality of epitaxial layers may be while the plurality of epitaxial layers are intact and preserves electrical, mechanical and optical properties of the plurality of epitaxial layers.
  • the patterns may define individual devices of the semiconductor devices.
  • a p-type metal ohmic contact layer may be applied to a p-type layer of the plurality of epitaxial layers and a layer of a dielectric may be applied over the p-type metal ohmic contact layer and the p-type layer.
  • the dielectric layer may be removed from above the metal ohmic contact layer.
  • the at least one seed layer may be deposited on the dielectric layer and the metal ohmic contact layer.
  • Figure 1 is a non-scale schematic, cross-sectional view of a semiconductor at a first stage in the fabrication process
  • Figure 2 is a non-scale schematic, cross-sectional view of a semiconductor at a second stage in the fabrication process
  • Figure 3 is a non-scale schematic, cross-sectional view of a semiconductor at a third stage in the fabrication process
  • Figure 4 is a non-scale schematic, cross-sectional view of a semiconductor at a fourth stage in the fabrication process
  • Figure 5 is a non-scale schematic, cross-sectional view of a semiconductor at a fifth stage in the fabrication process
  • Figure 6 is a non-scale schematic, cross-sectional view of a semiconductor at a sixth stage in the fabrication process
  • Figure 7 is a non-scale schematic, cross-sectional view of a semiconductor at a seventh stage in the fabrication process
  • Figure 8 is a non-scale schematic, cross-sectional view of a semiconductor at an eighth stage in the fabrication process
  • Figure 9 is a non-scale schematic, cross-sectional view of a semiconductor at a ninth stage in the fabrication process
  • Figure 10 is a non-scale schematic, cross-sectional view of a semiconductor at a tenth stage in the fabrication process
  • Figure 11 is a non-scale schematic, cross-sectional view of a semiconductor at an eleven stage in the fabrication process
  • Figure 12 is a non-scale schematic, cross-sectional view of a semiconductor at a twelfth stage in the fabrication process
  • Figure 13 is a non-scale schematic, cross-sectional view of a semiconductor at a thirteenth stage in the fabrication process
  • Figure 14 is a non-scale schematic, cross-sectional view of a semiconductor at a fourteenth stage in the fabrication process
  • Figure 15 is a non-scale schematic, cross-sectional view of a semiconductor at a fifteenth stage in the fabrication process.
  • Figure 16 is a non-scale schematic, cross-sectional view of a semiconductor at a sixteenth stage in the fabrication process.
  • the GaN devices described below are fabricated from epitaxial wafers that consist of a stack of thin semiconductor layers (called epitaxial layers) on a sapphire substrate.
  • the composition and thickness of the epitaxial layers depends on the wafer design, and determine the light colour (wavelength) of light that will be emitted by the devices that are fabricated from the wafer.
  • a thin buffer layer is first deposited on the sapphire substrate with a thickness often in the range 10 to 30 nm, and can be either AlN or GaN. In this specification this layer is not described or illustrated.
  • On top of the thin buffer layer may be another buffer layer that may be a relatively thick buffer layer. It may be in the range 1 to 7 micrometers.
  • the relatively thick buffer layer is followed by other layers of, for example, GaN, AIGaN, InN, InGaN, AIGaInN, and so forth.
  • n-type layers are often deposited on the buffer layers, followed by an active region.
  • p-type doped layers are deposited.
  • the active region is usually a double heterostructure made of a single quantum well, or multiple quantum wells and is for light generation. But it may be in other forms such as, for example, quantum dots.
  • the deposition of epitaxial layers is usually by metal organic chemical vapor deposition ("MOCVD") or molecular bean epitaxy (“MBE").
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular bean epitaxy
  • the thickness of the epitaxial layers is in the range from a few nanometers to a few microns.
  • the process starts after the sapphire substrate 4 has applied to it the n-type layer 3 of gallium nitride (GaN), the quantum well or active layer 2, and the p-type layer 1 of GaN.
  • GaN gallium nitride
  • the n-type layer 3 includes all layers below the active layer 2, including the two buffer layers, and the other layers referred to above.
  • the p-type layer 1 is relatively thin - normally no more, but preferably less, than 1 micron.
  • a p-metal layer 5 is then applied over the p-type layer 1.
  • the p-type metal layer 5 may be of nickel-gold (NiAu) or other suitable metal and is preferably relatively thin so that it is transparent. Alternatively, it may be reflective. More preferably it acts as a diffusion barrier to prevent or minimize diffusion into the epitaxial layers 1 , 2 and 3.
  • Standard photolithography and etching are then used to pattern layer 5. This is done by applying a thin layer of photoresist (layer 6(a) in Figure 2) on to metal layer 5, followed by resist exposure and development.
  • the resist pattern 6(a) serves as an etching mask for etching the metal layer 5.
  • the etching may be by wet chemical etching or plasma dry etching (see Figure 2).
  • the photoresist 6(a) is then removed.
  • the patterned layer 5 that remains on the surface of p-type GaN layer 1 will serve as an Ohmic contact layer to the p-type GaN layer 1. Annealing may take place either before or after layer 5 is patterned.
  • a layer 7 of silicon dioxide (SiO 2 ) is deposited over the remaining p-metal layer portions 5 and the p-type GaN layer 1 ( Figure 3) by a standard thin film deposition method. This may be by plasma enhanced chemical vapor deposition ("PECVD"), sputtering, evaporation, or other suitable techniques.
  • PECVD plasma enhanced chemical vapor deposition
  • a second photoresist layer 6(b) is applied over the oxide layer 7.
  • the resist is then patterned and serves as mask for patterning the oxide layer 7.
  • Wet etching or dry etching (plasma etching) of the oxide layer 7 is carried out.
  • the oxide 7 in the areas 7(a) where there is no photoresist 6(b) is removed, while oxide 7 protected by the resist 6(b) remains after etching.
  • the patterned second resist layer 6(b) is larger in area than the NiAu layer 5 so that the SiO 2 layer 7 remaining extends across the NiAu layer 5 and down the sides of NiAu layer 5 to the p-type GaN layer 1 , as shown in Figure 4.
  • the second resist layer 6(b) is removed.
  • Seed layer deposition follows, as is shown in Figure 5.
  • the seed layer 8 is of different metal layers, preferably three different metal layers, as shown.
  • the first seed layer 11 contacts with and adheres well to the NiAu layer 5 and the SiO 2 layer 7. It may be of chromium or titanium. It is followed by second layer 10 and third layer 9 of tantalum and copper respectively. Other materials may be used.
  • the first seed layer 11 preferably has good reflectivity for the reflection of light generated in the light emitting device.
  • the second seed layer 10 acts as a diffusion barrier, preventing copper or other materials placed on top of it (such as, for example, the third seed layer 9) from diffusing into the Ohmic contact layer 5 and the semiconductor epitaxial layers 1 , 2, 3.
  • the third seed layer 9 acts as a seeding layer for subsequent layer formation.
  • the coefficients of thermal expansion of the seed layers 9, 10, 11 may be different from that of GaN which is 3.17. While the thermal expansion coefficients of the Ohmic contact layers (Ni and Au) are also different from that of GaN (they are 14.2 and 13.4 respectively), they are relatively thin (a few nanometers) and do not pose serious stress problems to the underlining GaN epitaxial layers. However, a copper layer to be added later may be as thick as hundreds of microns and thus may cause severe stress problems. Thus, the seed layers 9, 10, 11 can be used to buffer the stress. This may be by one or more of: (a) by having sufficient flexibility to absorb the stress,
  • the first layer 11 is preferably less than that of the second layer 10, and that of the second layer 10 is preferably less than that of the third layer 9.
  • the first layer 11 may be chromium with a coefficient of thermal expansion of 4.9
  • the second layer 10 may be tantalum with a coefficient of thermal expansion of 6.3
  • the third layer 9 may be copper with a coefficient of thermal expansion of 16.5. In this way the coefficients of thermal expansion are graded from the
  • the thicknesses of the seed layers 9, 10, 11 are chosen in such a way that the stress on the epitaxial layers 1, 2, 3 is minimized.
  • the outer, copper layer 9 was applied directly to the SiO 2 layer 7 and Ohmic contact 7, the differences in their thermal expansion rates may cause cracking, separation, and/or failure.
  • the first seed layer 11 should be of a material with a relatively low coefficient of thermal expansion, whereas the final layer 9 may have a higher coefficient of thermal expansion. If there are intermediate layer(s) 10, the intermediate layer(s) should have coefficients) of expansion between those of layers
  • intermediate layer 10 There may be no intermediate layer 10, or there may be any required or desired number of intermediate layers 10 (one, two, three and so forth).
  • the seed layers 9, 10 and 11 may be replaced by a single layer of dielectric such as, for example, AIN with vias or holes therethrough to enable the copper layer 9 to connect to the p-type metal layer 5.
  • a pattern of thick resists 12 is applied to or in the outer third seed layer 9 by standard photolithography (Figure 6).
  • the thick metal layer 29 is formed in the regions 30 between and as defined by the thick resists 12 ( Figure 7).
  • the thick layer 29 may be formed by electroplating, and may be formed over the thick resists 12 to form a single metal support layer 29.
  • the thick layer 29 may be of any suitable thickness such as, for example, 0.3 mm, 1 mm, 2 mm, or more than 2 mm.
  • the third seed layer 9 may be partially etched in the center of the street 31 between the mesas 32 for the formation of the thick photoresists 12 (Figure 6) and plating of the main copper layer 29 ( Figure 7). This has the advantage of improved adhesion.
  • the resists 12 may be of a material such as, for example, SU-8 or any other material able to form high aspect ratio patterns.
  • the pattern of the resists 12 defines the ultimate shape and size of the devices.
  • a soft buffer material 33 is provided that encapsulates the entire wafer, or part of the material of the wafer, and the exposed lower surface 35 of the sapphire substrate 4.
  • the buffer material 33 may be, for example, a rubber emulsion, a silicone, an epoxy, an emulsion, a glue, a thermal glue, Crystal BondTM, wax, or the like.
  • a laser 37 is used to apply a beam 36 through the sapphire substrate 4 to the interface between the sapphire substrate 4 and n-type GaN layer 3 to separate the sapphire substrate 4 from the n-type GaN layer 3.
  • the beam 36 may be diverging (as shown) or collimated.
  • the sapphire substrate 4 is removed from the plurality of epitaxial layers while the plurality of epitaxial layers is intact. This preserves the electrical, mechanical and optical properties of the plurality of epitaxial layers 1 , 2, 3.
  • the soft buffer layer 33 may then be removed.
  • the individual devices are then isolated from each other by trench etching from the newly exposed surface along the edges 40 of the mesa 39, as shown in Figures 12 to 14, with a photoresist layer 41 protecting the regions of the n-type GaN- layer 3 during the etching process. This leaves the SiO 2 layer 7 exposed around the mesa 39. The resist 41 is then removed.
  • the lowermost surface 13 of the n-type layer 3 may be cleaved at locations in alignment with the photoresists 12 and the dies separated. This is of advantage for laser diodes as the exposed side surfaces of the n-type layer 3 are substantially parallel, thereby forming mirrors, and thus causing a large amount of total internal reflection. This acts as a light amplification system for improved, and directed, light output.
  • a layer 42 of SiO 2 is applied over the exposed surfaces of the SiO 2 layer 7, the sides of the n-type GaN layer 3, and the center of the n-type GaN layer 3 ( Figure 11). Pad etching then takes place to remove the SiO 2 layer to expose the surface 13 of the n-type layer 3.
  • a further resist layer 43 is applied over the exposed surfaces of the SiO 2 layer 42 and the center of the exposed surface 13 leaving a gap 16 for etching of the exposed surface 13. Etching takes place through the gap 16 to surface texture the exposed surface 13.
  • the resist 43 is removed and a new resist layer 44 is applied over all exposed lower- surfaces except those aligned with thick patterns 12. Etching then takes place ( Figure 14) through the SiO 2 layers 42 and 7, and seed layers 8, until the ends of the thick patterns 12 are exposed.
  • a layer or layers 18 of metals are then applied over the resist 44 with the layer 18 having a gap 17 at the center of the n-type GaN layer 3 so that the layers 18 are applied directly to the GaN layer 3 ( Figure 15).
  • the resist layer 44, with the layer 18 attached, is removed leaving the layer 18 attached to the center 17 of the n-type GaN layer 3 where gap 17 was previously located.
  • the layers 18 may be one or more layers. All layers 18 may be the same or different. They may be, for example, 18(a) titanium, 18(b) aluminum, 18(c) titanium and 18(d) gold, respectively.
  • the thick copper layer 29 is then polished flat ( Figure 16).
  • the dies are then each separated by physical separation as the patterns 12 do not adhere to the copper of the thick layer 29. This means that dicing, or another method of cutting, of the thick layer 29 into individual devices is not required.
  • the seed layers 11 , 10, 9 and the copper layer 29 act as reflectors to increase light output, with copper layer 29 being one terminal, thus not interfering with light output.
  • the second terminal is layer 18 on the n-type layer 3 of GaN.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Led Devices (AREA)

Abstract

L'invention porte sur un procédé de fabrication de dispositifs semi-conducteurs. Le procédé consiste à fournir un substrat sur lequel est montée une pluralité de couches épitaxiales ; et à séparer le substrat de la pluralité de couches épitaxiales tout en maintenant la pluralité de couches épitaxiales intacte. Ce procédé permet de préserver les propriétés électriques, optiques et mécaniques de la pluralité de couches épitaxiales.
PCT/SG2008/000238 2007-07-04 2008-07-03 Séparation de dispositifs semi-conducteurs WO2009005477A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2010514706A JP2010532563A (ja) 2007-07-04 2008-07-03 半導体デバイスの分離
US12/667,418 US8507367B2 (en) 2007-07-04 2008-07-03 Separation of semiconductor devices
CN200880023028XA CN101743619B (zh) 2007-07-04 2008-07-03 半导体器件的分离

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
SG200704890-3 2007-07-04
SG200704890-3A SG148895A1 (en) 2007-07-04 2007-07-04 Separation of semiconductor devices for light emission
SG200718567-1A SG153672A1 (en) 2007-07-04 2007-12-10 Separation of semiconductor devices
SG200718567-1 2007-12-10

Publications (1)

Publication Number Publication Date
WO2009005477A1 true WO2009005477A1 (fr) 2009-01-08

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WO (1) WO2009005477A1 (fr)

Cited By (5)

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Publication number Priority date Publication date Assignee Title
CN101807655A (zh) * 2009-02-17 2010-08-18 Lg伊诺特有限公司 制造半导体发光器件的方法
EP2372791A3 (fr) * 2010-03-10 2012-07-18 LG Innotek Co., Ltd. Diode électroluminescente
EP2221892B1 (fr) * 2009-02-18 2013-01-16 LG Innotek Co., Ltd. Dispositif électroluminescent à semi-conducteur et emballage de dispositif électroluminescent comprenant ce dispositif
CN103219451A (zh) * 2008-06-13 2013-07-24 三星电子株式会社 发光元件
JP2017079335A (ja) * 2009-10-15 2017-04-27 エルジー イノテック カンパニー リミテッド 発光素子

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US5972781A (en) * 1997-09-30 1999-10-26 Siemens Aktiengesellschaft Method for producing semiconductor chips
WO2005008740A2 (fr) * 2003-07-14 2005-01-27 Allegis Technologies, Inc. Procedes de traitement du nitrure de gallium
WO2005029572A1 (fr) * 2003-09-19 2005-03-31 Tinggi Technologies Private Limited Fabrication d'une couche metallique conductrice sur des dispositifs semiconducteurs
US20050247950A1 (en) * 2004-05-06 2005-11-10 Cree, Inc. Lift-off process for GaN films formed on SiC substrates and devices fabricated using the method
CN1779996A (zh) * 2004-11-23 2006-05-31 北京大学 在金属热沉上的激光剥离功率型led芯片及其制备方法
WO2007037762A1 (fr) * 2005-09-29 2007-04-05 Tinggi Technologies Private Limited Fabrication de dispositifs semi-conducteurs pour l’émission de lumière

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WO2005008740A2 (fr) * 2003-07-14 2005-01-27 Allegis Technologies, Inc. Procedes de traitement du nitrure de gallium
WO2005029572A1 (fr) * 2003-09-19 2005-03-31 Tinggi Technologies Private Limited Fabrication d'une couche metallique conductrice sur des dispositifs semiconducteurs
US20050247950A1 (en) * 2004-05-06 2005-11-10 Cree, Inc. Lift-off process for GaN films formed on SiC substrates and devices fabricated using the method
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103219451A (zh) * 2008-06-13 2013-07-24 三星电子株式会社 发光元件
CN101807655A (zh) * 2009-02-17 2010-08-18 Lg伊诺特有限公司 制造半导体发光器件的方法
EP2219234A3 (fr) * 2009-02-17 2010-11-24 LG Innotek Co., Ltd. Procédé de fabrication de dispositif électroluminescent à semi-conducteur
US8236581B2 (en) 2009-02-17 2012-08-07 Lg Innotek Co., Ltd. Method of manufacturing semiconductor light emitting device
US8785963B2 (en) 2009-02-17 2014-07-22 Lg Innotek Co., Ltd. Method of manufacturing semiconductor light emitting device
EP2221892B1 (fr) * 2009-02-18 2013-01-16 LG Innotek Co., Ltd. Dispositif électroluminescent à semi-conducteur et emballage de dispositif électroluminescent comprenant ce dispositif
JP2017079335A (ja) * 2009-10-15 2017-04-27 エルジー イノテック カンパニー リミテッド 発光素子
EP2372791A3 (fr) * 2010-03-10 2012-07-18 LG Innotek Co., Ltd. Diode électroluminescente
US8653547B2 (en) 2010-03-10 2014-02-18 Lg Innotek Co., Ltd Light emitting device and light emitting device package
US9455377B2 (en) 2010-03-10 2016-09-27 Lg Innotek Co., Ltd. Light emitting device
US9899567B2 (en) 2010-03-10 2018-02-20 Lg Innotek Co., Ltd. Light emitting device

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