WO2009002477A1 - Diodes à courant direct élevé pour une cellule 3d à écriture inverse et procédé de fabrication de ces diodes - Google Patents

Diodes à courant direct élevé pour une cellule 3d à écriture inverse et procédé de fabrication de ces diodes Download PDF

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Publication number
WO2009002477A1
WO2009002477A1 PCT/US2008/007802 US2008007802W WO2009002477A1 WO 2009002477 A1 WO2009002477 A1 WO 2009002477A1 US 2008007802 W US2008007802 W US 2008007802W WO 2009002477 A1 WO2009002477 A1 WO 2009002477A1
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Prior art keywords
diode
oxide
state
dielectric layer
resistivity
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PCT/US2008/007802
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English (en)
Inventor
S. Brad Herner
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Sandisk 3D Llc
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Publication date
Priority claimed from US11/819,078 external-priority patent/US7830697B2/en
Priority claimed from US11/819,079 external-priority patent/US7684226B2/en
Application filed by Sandisk 3D Llc filed Critical Sandisk 3D Llc
Priority to JP2010513272A priority Critical patent/JP2010531543A/ja
Priority to CN200880021393A priority patent/CN101720485A/zh
Priority to EP08768726A priority patent/EP2165336A1/fr
Publication of WO2009002477A1 publication Critical patent/WO2009002477A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5685—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using storage elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/32—Material having simple binary metal oxide structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/33—Material including silicon
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/34—Material includes an oxide or a nitride
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Definitions

  • the invention relates to a nonvolatile memory array.
  • Nonvolatile memory arrays maintain their data even when power to the device is turned off.
  • each memory cell is formed in an initial unprogrammed state, and can be converted to a programmed state. This change is permanent, and such cells are not erasable. In other types of memories, the memory cells are erasable, and can be rewritten many times.
  • Cells may also vary in the number of data states each cell can achieve.
  • a data state may be stored by altering some characteristic of the cell which can be detected, such as current flowing through the cell under a given applied voltage or the threshold voltage of a transistor within the cell.
  • a data state is a distinct value of the cell, such as a data '0' or a data T.
  • Floating gate and SONOS memory cells operate by storing charge, where the presence, absence or amount of stored charge changes a transistor threshold voltage.
  • These memory cells are three-terminal devices which are relatively difficult to fabricate and operate at the very small dimensions required for competitiveness in modern integrated circuits.
  • One embodiment provides a nonvolatile memory device, comprising at least one memory cell which comprises a diode and a metal oxide antifuse dielectric layer, and a first electrode and a second electrode electrically contacting the at least one memory cell.
  • the diode acts as a read / write element of the memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.
  • a nonvolatile memory device comprising a plurality of memory cells, and a first electrode and a second electrode electrically contacting the plurality of memory cells.
  • Each memory cell of the plurality of memory cells comprises a diode and a metal oxide antifuse dielectric layer arranged in series between the first and the second electrodes, and the diode comprises a polycrystalline silicon, germanium or silicon-germanium p-i-n pillar diode having a substantially cylindrical shape.
  • Fig. 1 is a circuit diagram illustrating the need for electrical isolation between memory cells in a memory array.
  • Figs. 2 and 16a are perspective views and Fig. 16b is a side cross sectional view of multi-state or rewriteable memory cells formed according to a embodiments of the present invention.
  • Fig. 3 is a perspective view of a portion of a memory level comprising the memory cells of Fig. 2.
  • Fig. 4 is a graph showing change in read current for a memory cell of the present invention as voltage in reverse bias across the diode increases.
  • Fig. 5 is a probability plot showing memory cells transformed from the V state to the P state, from the P state to the R state, and from the R state to the S state.
  • Fig. 6 is a probability plot showing memory cells transformed from the V state to the P state, from the P state to the S state, and from the S state to the R state.
  • Fig. 7 is a probability plot showing memory cells transformed from the V state to the R state, from the R state to the S state, and from the S state to the P state.
  • Fig. 8 is a perspective view of a vertically oriented p-i-n diode that may be used in embodiments of the present invention.
  • Fig. 9 is a probability plot showing memory cells transformed from the V state to the P state, and from the P state to the M state.
  • Fig. 10 is a plot of the current flowing through the diode versus the applied voltage for various diode states illustrated in Fig. 5.
  • Fig. 11 is a probability plot showing memory cells transformed from the V state to the P state, from the P state to the R state, and from the R state to the S state, then repeatably between the S state and the R state.
  • Fig. 12 is a circuit diagram showing a biasing scheme to bias the S cell in forward bias.
  • Fig. 13 is a circuit diagram showing one biasing scheme to bias the S cell in reverse bias.
  • Fig. 14 illustrates iterative read- verify- write cycles to move a cell into a data state.
  • Figs. 15a-15c are cross-sectional views illustrating stages in formation of a memory level formed according to an embodiment of the present invention.
  • Figs. 17a -17c are probability plots of various memory cells according to embodiments of the invention and according to comparative examples.
  • Leakage current can be greatly reduced by forming each memory cell as a two-terminal device including a diode.
  • a diode has a non-linear I-V characteristic, allowing very little current flow below a turn-on voltage, and substantially higher current flow above the turn-on voltage.
  • a diode also acts as one-way valves passing current more easily in one direction than the other.
  • a memory element formed of doped semiconductor material for example the semiconductor diode of the '549 application, can achieve three, four, or more stable resistivity states.
  • semiconductor material can be converted from an initial high-resistivity state to a lower-resistivity state; then, upon application of an appropriate electrical pulse, can be returned to a higher-resistivity state.
  • These embodiments can be employed independently or combined to form a memory cell which can have two or more data states, and can be one-time-programmable or rewriteable.
  • a diode between conductors in the memory cell allows its formation in a highly dense cross-point memory array.
  • a polycrystalline, amorphous, or microcrystalline semiconductor memory element either is formed in series with a diode or, more preferably, is formed as the diode itself.
  • transition from a higher- to a lower-resistivity state will be called a set transition, affected by a set current, a set voltage, or a set pulse; while the reverse transition, from a lower- to a higher-resistivity state, will be called a reset transition, affected by a reset current, a reset voltage, or a reset pulse.
  • a polycrystalline semiconductor diode is paired with a dielectric rupture antifuse, such as a high dielectric constant material antifuse layer, as will be described in more detail below.
  • Fig. 2 illustrates a memory cell formed according to a preferred embodiment of the present invention.
  • a bottom conductor 12 is formed of a conductive material, for example tungsten, and extends in a first direction. Barrier and adhesion layers may be included in bottom conductor 12.
  • Polycrystalline semiconductor diode 2 has a bottom heavily doped n-type region 4; an intrinsic region 6, which is not intentionally doped; and a top heavily doped region 8, though the orientation of this diode may be reversed. Such a diode, regardless of its orientation, will be referred to as a p-i-n diode.
  • Dielectric rupture antifuse 14 is provided in series with the diode 2.
  • Top conductor 16 may be formed in the same manner and of the same materials as bottom conductor 12, and extends in a second direction different from the first direction.
  • Polycrystalline semiconductor diode 2 is vertically disposed between bottom conductor 12 and top conductor 16.
  • Polycrystalline semiconductor diode 2 is formed in a high-resistivity state.
  • This memory cell can be formed above a suitable substrate, for example above a monocrystalline silicon wafer.
  • Fig. 3 shows a portion of a memory level of such devices formed in a cross-point array, where diodes 2 are disposed between bottom conductors 12 and top conductors 16 (antifuses 14 are omitted in this view.)
  • Multiple memory levels can be stacked over a substrate to form a highly dense monolithic three dimensional memory array.
  • an intrinsic region may in fact include a low concentration of p-type or n-type dopants. Dopants may diffuse into the intrinsic region from adjacent regions, or may be present in the deposition chamber during deposition due to contamination from an earlier deposition. It will further be understood that deposited intrinsic semiconductor material (such as silicon) may include defects which cause it to behave as if slightly n-doped. Use of the term "intrinsic" to describe silicon, germanium, a silicon-germanium alloy, or some other semiconductor material is not meant to imply that this region contains no dopants whatsoever, nor that such a region is perfectly electrically neutral.
  • the resistivity of doped polycrystalline or microcrystalline semiconductor material can be changed between stable states by applying appropriate electrical pulses. It has been found that in preferred embodiments, set transitions are advantageously performed with the diode under forward bias, while reset transitions are most readily achieved and controlled with the diode under reverse bias. In some instances, however, set transitions may be achieved with the diode under reverse bias, while reset transitions are achieved with the diode under forward bias.
  • Switching under reverse bias shows a distinct behavior.
  • a polysilicon p-i-n diode like the one shown in Fig. 2 is subjected to a relatively large switching pulse under reverse bias.
  • a smaller read pulse for example 2 volts
  • the read current is measured.
  • the subsequent read current at two volts changes as shown in Fig. 4. It will be seen that initially as the reverse voltage and current of the switching pulse are increased, the read current, when a read voltage is applied after each switching pulse, increases; i.e.
  • the initial transition of the semiconductor material (silicon, in this case) is in the set direction toward lower resistivity.
  • the switching pulse reaches a certain reverse bias voltage, at point K in Fig. 4, about -14.6 volts in this example, the read current abruptly begins to drop as reset is achieved and resistivity of the silicon increases.
  • the switching voltage at which the set trend is reversed and the silicon of the diode begins to reset varies, depending on, for example, the resistivity state of the silicon making up the diode when application of the reverse bias switching pulse is begun. It will be seen, then, that by selecting appropriate voltages, either set or reset of the semiconductor material making up the diode can be achieved with the diode under reverse bias.
  • Distinct data states of the memory cell of the present invention correspond to resistivity states of polycrystalline or microcrystalline semiconductor material making up the diode, which are distinguished by detecting current flow through the memory cell (between top conductor 16 and bottom conductor 12) when a read voltage is applied.
  • the current flowing between any one distinct data state and any different distinct data state is at least a factor of two, to allow the difference between the states to be readily detectable.
  • the memory cell can be used as a one-time programmable cell or a rewriteable memory cell, and may have two, three, four, or more distinct data states.
  • the cell can be converted from any of its data states to any other of its data states in any order, and under either forward or reverse bias.
  • the diode acts as a read / write element of the memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias
  • the read current of the programmed diode can be increased by the use of high dielectric constant (k) antifuses. These antifuses are shown to result in a 50% increase in the programmed read current at a given read voltage, such as at a 2V read voltage, compared to the lower dielectric constant SiO 2 antifuses. This results in a larger difference between the programmed and reset state currents for a reverse write memory cell.
  • k dielectric constant
  • the antifuse is composed of a metal oxide antifuse dielectric layer, such as a layer having a dielectric constant higher than 3.9, such as for example about 4.5 to about 8. Other dielectric layers having a dielectric constant above 3.9 may also be used.
  • the metal oxide material may be a stoichiometric or non- stoichiometric material.
  • the metal oxide may be selected from one or a blend of more than one of the following materials: hafnium oxide, aluminum oxide, titanium oxide, lanthanum oxide, tantalum oxide, ruthenium oxide, zirconium silicon oxide, aluminum silicon oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium silicon oxynitride, zirconium silicon aluminum oxide, hafnium aluminum silicon oxide, hafnium aluminum silicon oxynitride, or zirconium silicon aluminum oxynitride.
  • These materials may have the following chemical formulas: HfO 2 , Al 2 O 3 , ZrO 2 , TiO 2 , La 2 O 3 , Ta 2 O 5 , RuO 2 , ZrSiO x , AlSiO x , HfSiO x , HfAlO x , HfSiON, ZrSiAlO x , HfSiAlO x , HfSiAlON, and ZrSiAlON, and may be combined with SiO 2 and/or SiN x .
  • Hafnium oxide or aluminum oxide are preferred.
  • the metal oxide antifuse dielectric layer is located adjacent to a p-type region of the diode.
  • the antifuse dielectric layer preferably has a thickness of about 10 to about 100 Angstroms, such as about 30 to about 40 Angstroms.
  • a diode formed of polycrystalline semiconductor material and a dielectric rupture antifuse are arranged in series disposed between a top and bottom conductor.
  • the two-terminal device is used as a one-time-programmable multilevel cell, in preferred embodiments having three or four distinct data states.
  • Diode 2 is preferably formed of a polycrystalline or microcrystalline semiconductor material, for example silicon, germanium, or an alloy of silicon and/or germanium. Diode 2 is most preferably polysilicon. In this example, bottom heavily doped region 4 is n-type and top heavily doped region 8 is p-type, though the polarity of the diode may be reversed.
  • the memory cell comprises a portion of the top conductor, a portion of the bottom conductor, and a diode, the diode disposed between the conductors.
  • Fig. 5 is a probability plot showing current of a plurality of memory cells containing silicon dioxide antifuse dielectric layers in various states.
  • a read voltage for example 2 volts
  • the read current flowing between top conductor 16 and bottom conductor 12 is preferably in the range of nanoamps, for example less than about 5 nanoamps.
  • Area V on the graph of Fig. 5 corresponds to a first data state of the memory cell. For some memory cells in the array, this cell will not be subjected to set or reset pulses, and this state will be read as a data state of the memory cell. This first data state will be referred to as the V state.
  • a first electrical pulse preferably with diode 2 under forward bias, is applied between top conductor 16 and bottom conductor 12.
  • This pulse is, for example, between about 8 volts and about 12 volts, for example about 10 volts.
  • the current is, for example, between about 80 and about 200 microamps.
  • the pulse width is preferably between about 100 and about 500 nsec.
  • This first electrical pulse ruptures dielectric rupture antifuse 14 and switches the semiconductor material of diode 2 from a first resistivity state to a second resistivity state, the second state lower resistivity than the first.
  • This second data state will be referred to as the P state, and this transition is labeled "V ⁇ P" in Fig. 5.
  • the current flowing between top conductor 16 and bottom conductor 12 at a read voltage of 2 volts is about 10 microamps or more.
  • the resistivity of the semiconductor material making up diode 2 is reduced by a factor of about 1000 to about 2000. In other embodiments the change in resistivity will be less, but between any data state and any other data state will be at least a factor of two, preferably at least a factor of three or five, and more typically a factor of 100 or more. Some memory cells in the array will be read at this data state, and will not be subjected to additional set or reset pulses. This second data state will be referred to as the P state.
  • the read current at 2 V can increase from IxIO "8 A in the unprogrammed state to at least IxIO "5 A after the programming pulse.
  • the table below shows that increasing the programming voltage results in a higher read current.
  • the last column in the table shows the standard deviation of the read current.
  • the read currents shown in the table above are for a cell shown in Fig. 2 with the interconnects and a silicon oxide antifuse. If the interconnects are excluded and a metal oxide antifuse is used, then the read current is even higher. For example, for a programming voltage of 8.4V, the read current of the cell without the interconnects is at least 3.5x10 "5 A at a read voltage of at least +1.5V, such as +1.5 to +2 V. It is expected that further increases in programming voltage would provide a further increase in the read current.
  • the programming voltage from 8.4V to 10V is expected to generate an about 70% increase in read current, such that the read current for a cell without the interconnects is about 6 x 10 "5 A at 2 V read voltage.
  • multiple programming pulses such as 2 to 10 pulses, for example 3-5 pulses, may be applied to the diode.
  • the use of a metal oxide antifuse dielectric layer further increases the read current, as will be discussed below with respect to Figs. 17a- 17c.
  • a second electrical pulse preferably with diode 2 under reverse bias, is applied between top conductor 16 and bottom conductor 12.
  • This pulse is, for example, between about -8 volts and about -14 volts, preferably about between about -10 and about -12 volts, preferably about -11 volts.
  • the current is, for example, between about 80 and about 200 microamps.
  • the pulse width is, for example, between about 100 nanosec and about 10 microseconds; preferably between about 100 nsec and about 1 microsecond, most preferably between about 200 and about 800 nsec.
  • This second electrical pulse switches the semiconductor material of diode 2 from the second resistivity state to a third resistivity state, the third resistivity state higher resistivity than the second.
  • the current flowing between top conductor 16 and bottom conductor 12 at a read voltage of 2 volts is between about 10 and about 500 nanoamps, preferably between about 100 and about 500 nanoamps.
  • Some memory cells in the array will be read at this data state, and will not be subjected to additional set or reset pulses.
  • This third data state will be referred to as the R state, and this transition is labeled "P ⁇ R" in Fig. 5.
  • Fig. 10 is a plot of read current versus read voltage for various diode states illustrated in Fig. 5.
  • the diode initially starts in a low read current state V (referred to as the unprogrammed or "virgin” state).
  • the diode is put the in the programmed state P by the high forward bias pulse, preferably at the factory where the diode is made before the product is sold, where power is not a consideration.
  • the diode is subsequently put in the reset state R by a reverse bias programming pulse.
  • the difference between the read currents of the programmed and reset states P and R constitutes the "window" for the memory cell, as shown in Fig. 10.
  • the large programming voltage and/or multiple programming pulses allow this window to be as large as possible for manufacturing robustness.
  • a third electrical pulse preferably with diode 2 under forward bias, is applied between top conductor 16 and bottom conductor 12.
  • This pulse is, for example, between about 8 volts and about 12 volts, for example about 10 volts, with current between about 5 and about 20 microamps.
  • This third electrical pulse switches the semiconductor material of diode 2 from the third resistivity state to a fourth resistivity state, the fourth resistivity state lower resistivity than the third, and preferably higher resistivity than the second resistivity state.
  • the current flowing between top conductor 16 and bottom conductor 12 at a read voltage of 2 volts is between about 1.5 and about 4.5 microamps.
  • the difference in current at the read voltage is preferably at least a factor of two between any two adjacent data states.
  • the read current of any cell in data state R is preferably at least two times that of any cell in data state V
  • the read current of any cell in data state S is preferably at least two times that of any cell in data state R
  • the read current of a cell in data state P is preferably at least two times that of any cell in data state S.
  • the read current at data state R may be two times the read current at data state V
  • the read current at data state S may be two times the read current at data state R
  • the read current at data state P may be two times the read current at data state S.
  • the difference could be considerably larger; for example, if the highest-current V state cell can have a read current of 5 nanoamps and the lowest- current R state call can have a read current of 100 nanoamps, the difference in current is at least a factor of 20. By selecting other limits, it can be assured that the difference in read current between adjacent memory states will be at least a factor of three.
  • an iterative read- verify- write process may be applied to assure that a memory cell is in one of the defined data states after a set or reset pulse, and not between them.
  • a memory cell having four distinct data states has been described. To aid in distinguishing between the data states, it may be preferred for three rather than four data states to be selected. For example, a three-state memory cell can be formed in data state V, set to data state P, then reset to data state R. This cell will have no fourth data state S. In this case the difference between adjacent data states, for example between the R and P data states, can be significantly larger.
  • the cells may be programmed in a variety of ways, however.
  • the memory cell of Fig. 2 may be formed in a first state, the V state.
  • a first electrical pulse preferably under forward bias, ruptures antifuse 14 and switches the polysilicon of the diode from a first resistivity state to a second resistivity state lower than the first, placing the memory cell in the P state, which in this example is the lowest resistivity state.
  • a second electrical pulse preferably under reverse bias, switches the polysilicon of the diode from the second resistivity state to a third resistivity state, the third resistivity state higher resistivity than the second, placing the memory cell in the S state.
  • a third electrical pulse preferably also under reverse bias, switches the polysilicon of the diode from the third resistivity state to a fourth resistivity state, the third resistivity state higher resistivity than the second, placing the memory cell in the R state.
  • any of the data states, the V state, the R state, the S state, and the P state can be read as a data state of the memory cell.
  • Each transition is labeled in Fig. 6. Four distinct states are shown; there could be three or more than four states as desired.
  • each successive electrical pulse can switch the semiconductor material of the diode to a successively lower resistivity state.
  • the memory cell can proceed from the initial V state to the R state, from the R state to the S state, and from the S state to the P state, where for each state the read current is at least two times the read current at the previous state, each corresponding to a distinct data state.
  • the pulses may be applied under either forward or reverse bias. In alternative embodiments there may be three data states or more than four data states.
  • a memory cell includes the polysilicon or microcrystalline diode 2 shown in Fig. 8, including bottom heavily doped p-type region 4, middle intrinsic or lightly doped region 6, and top heavily doped n-type region 8.
  • this diode 2 can be arranged in series with a dielectric rupture antifuse, the two disposed between top and bottom conductors.
  • Bottom heavily doped p-type region 4 may be in situ doped, i.e. doped by flowing a gas that provides a p-type dopant such as boron during deposition of the polysilicon, such that dopant atoms are incorporated into the film as it forms.
  • this memory cell is formed in the V state, where the current between top conductor 16 and bottom conductor 12 is less than about 80 nanoamps at a read voltage of 2 volts.
  • a first electrical pulse preferably applied under forward bias of, for example, about 8 volts, ruptures dielectric rupture antifuse 14, and switches the polysilicon of diode 2 from a first resistivity state to a second resistivity state, the second resistivity state lower than the first, placing the memory cell in data state P.
  • data state P the current between top conductor 16 and bottom conductor 12 at the read voltage is between about 1 microamp and about 4 microamps.
  • a second electrical pulse preferably applied in reverse bias, switches the polysilicon of diode 2 from the second resistivity state to a third resistivity state, the third resistivity state lower than the first.
  • the third resistivity state corresponds to data state M.
  • data state M the current between top conductor 16 and bottom conductor 12 at the read voltage is above about 10 microamps.
  • the difference in current between any cell in adjacent data states is preferably at least a factor of two, preferably a factor of three or more. Any of the data states V, P, or M can be detected as a data state of the memory cell.
  • Fig. 4 showed that when a semiconductor diode is subjected to reverse bias, in general the semiconductor material initially undergoes a set transition to lower resistivity, then, as voltage is increased, undergoes a reset transition to higher resistivity.
  • the switch from set transition to reset transition with increasing reverse bias voltage does not occur as abruptly or as steeply as with other embodiments of the diode. This means a set transition under reverse bias is easier to control with such a diode.
  • the memory cell behaves as a rewriteable memory cell, which is repeatably switchable between two or between three data states.
  • the memory cell is formed in a high resistivity state V, with current at 2 volts about 5 nanoamps or less.
  • the plot shown in Figure 11 is for a cell with a silicon oxide antifuse.
  • the initial V state does not serve as a data state of the memory cell.
  • a first electrical pulse preferably with diode 2 under forward bias, is applied between top conductor 16 and bottom conductor 12. This pulse is, for example, between about 8 and about 12 volts, preferably about 10 volts.
  • This first electrical pulse switches the semiconductor material of diode 2 from a first resistivity state to a second resistivity state P, the second state lower resistivity than the first.
  • the P state also will not serve as a data state of the memory cell. In other embodiments, the P state will serve as a data state of the memory cell.
  • a second electrical pulse preferably with diode 2 under reverse bias, is applied between top conductor 16 and bottom conductor 12.
  • This pulse is, for example, between about -8 and about -14 volts, preferably between about -9 and about -13 volts, more preferably about -10 or -11 volts.
  • the voltage required will vary with the thickness of the intrinsic region.
  • This second electrical pulse switches the semiconductor material of diode 2 from the second resistivity state to a third resistivity state R, the third state higher resistivity than the second.
  • the R state corresponds to a data state of the memory cell.
  • a third electrical pulse can be applied between top conductor 16 and bottom conductor 12, preferably under forward bias.
  • This pulse is, for example, between about 5.5 and about 9 volts, preferably about 6.5 volts, with current between about 10 and about 200 microamps, preferably between about 50 and about 100 microamps.
  • This third electrical pulse switches the semiconductor material of diode 2 from the third resistivity state R to a fourth resistivity state S, the fourth state lower resistivity than the third.
  • the S state corresponds to a data state of the memory cell.
  • the R state and the S state are sensed, or read, as data states. The memory cell can repeatedly be switched between these two states.
  • a fourth electrical pulse preferably with diode 2 under reverse bias, switches the semiconductor material of the diode from the fourth resistivity state S to the fifth resistivity state R, which is substantially the same as the third resistivity state R.
  • a fifth electrical pulse preferably with diode 2 under forward bias, switches the semiconductor material of the diode from the fifth resistivity state R to the sixth resistivity state S, which is substantially the same as the fourth resistivity state S, and so on. It may be more difficult to return the memory cell to the initial V state and the second P state; thus these states may not be used as data states in a rewriteable memory cell.
  • both the first electrical pulse, which switches the cell from the initial V state to the P state, and the second electrical pulse, which switches the cell from the P state to the R state, may be performed before the memory array reaches the end user, for example in a factory or test facility, or by a distributor before sale.
  • the difference between current flow under read voltage, for example of 2 volts, between top conductor 16 and bottom conductor 12 between any cell in one data state and any cell in an adjacent data states, in this case the R data state (between about 10 and about 500 nanoamps) and the S data state (between about 1.5 and about 4.5 microamps), is at least a factor of three.
  • the difference may be a factor of two, three, five, or more.
  • a rewriteable memory cell can be switched between three or more data states, in any order. Either set or reset transitions can be performed with the diode under either forward or reverse bias.
  • the data state corresponds to the resistivity state of polycrystalline or microcrystalline semiconductor material making up a diode.
  • the data states does not correspond to the resistivity state of a resistivity-switching metal oxide or nitride, as in Herner et al., US Patent Application No. 11/395,995, "Nonvolatile Memory Cell Comprising a Diode and a Resistance-Switching Material," filed March 31, 2006, owned by the assignee of the present invention and hereby incorporated by reference.
  • any step in which cells are subjected to large voltages in reverse bias has reduced leakage current as compared to a forward bias step.
  • Bitline BO is set at 10 volts and wordline WO is set at ground.
  • wordline Wl is set less than but relatively close to the voltage of bitline BO; for example wordline Wl may be set to 9.3 volts, so that 0.7 volts is applied across the F cells (only one F cell is shown, but there may be hundreds, thousands or more.)
  • bitline Bl is set higher than but relatively close to the voltage of wordline WO; for example bitline Bl may be set to 0.7 volts, so that 0.7 volts is applied across cell H (again, there may be thousands of H cells.)
  • the unselected cells U which share neither wordline WO or bitline BO with selected cell S, are subjected to -8.6 volts. As there may be millions of unselected cells U, this results in significant leakage current within the array.
  • Fig. 13 shows an advantageous biasing scheme to apply a large reverse bias across a memory cell, for example as a reset pulse.
  • Bitline BO is set at -5 volts and wordline WO at 5 volts, so that -10 volts is applied across selected cell S; the diode is in reverse bias.
  • Setting wordline Wl and bitline Bl at ground subjects both half-selected cells F and H to -5 volts, at a reverse bias low enough not to cause unintentional set or reset of these cells.
  • Set or reset in reverse bias generally seems to take place at or near the voltage at which the diode goes into reverse breakdown, which is generally higher than -5 volts. With this scheme, there is no voltage across the unselected cells U, resulting in no reverse leakage.
  • bitline BO can be set at 0 volts, wordline WO at - 10 volts, and bitline Bl and wordline Wl at -5 volts.
  • the voltage across selected cell S, half-selected cells H and F, and unselected cells U will be the same as in the scheme of Fig. 13.
  • bitline BO is set at ground, wordline WO at 10 volts, and bitline Bl and wordline Wl each at 5 volts.
  • the difference between current flow during read in adjacent data states is preferably at least a factor of two; in many embodiments, it may be preferred to establish current ranges for each data state which are separated by a factor of three, five, ten, or more.
  • data state V may be defined as read current of 5 nanoamps or less at a read voltage of 2 volts, data state R as read current between about 10 and about 500 nanoamps, data state S as read current between about 1.5 and about 4.5 microamps, and data state P as read current above about 10 microamps.
  • data state V may be defined in a smaller range, with read current about 5 nanoamps or less at a read voltage of 2 volts. Actual read currents will vary with characteristics of the cell, construction of the array, read voltage selected, and many other factors.
  • a one-time programmable memory cell is in data state P.
  • An electrical pulse in reverse bias is applied to the memory cell to switch the cell into data state S.
  • the read current is not in the desired range; i.e. the resistivity state of the semiconductor material of the diode is higher or lower than intended.
  • the read current of the memory cell is at the point on the graph shown at Q, in between the S state and P state current ranges.
  • the memory cell may be read to determine if the desired data state was reached. If the desired data state was not reached, an additional pulse is applied. For example, when the current Q is sensed, an additional reset pulse is applied to increase the resistivity of the semiconductor material, decreasing the read current into the range corresponding to the S data state. As described earlier, this set pulse may be applied in either forward or reverse bias. The additional pulse or pulses may have a higher amplitude (voltage or current) or longer or shorter pulse width than the original pulse. After the additional set pulse, the cell is read again, then set or reset pulses applied as appropriate until the read current is in the desired range.
  • a two-terminal device such as the memory cell including a diode described, it will be particularly advantageous to read in order to verify the set or reset and to adjust if necessary. Applying a large reverse bias across the diode may damage the diode; thus when performing a set or reset with the diode under reverse bias, it is advantageous to minimize the reverse bias voltage.
  • an amorphous or microcrystalline silicon material is crystallized not in contact with a silicon having a suicide with which it has a good lattice match, for example in contact only with materials such as silicon dioxide and titanium nitride, with which it has a significant lattice mismatch, the resulting polysilicon will have many more defects, and doped polysilicon crystallized this way will be much less conductive as formed.
  • the semiconductor material forming a diode is switched between two or more resistivity states, changing the current flowing through the diode at a given read voltage, the different currents (and resistivity states) corresponding to distinct data states. It has been found that diodes formed of high- defect silicon (or other appropriate semiconductor materials such as germanium or silicon-germanium alloys) which has not been crystallized adjacent to a suicide or analogous material providing a crystallization template exhibit the most advantageous switching behavior.
  • the polycrystalline or microcrystalline material forming the diode is not crystallized adjacent to a material with which it has a small lattice mismatch.
  • a small lattice mismatch is, for example, a lattice mismatch of about three percent or less.
  • a substrate 100 can be any semiconducting substrate as known in the art, such as monocrystalline silicon, IV-IV compounds like silicon-germanium or silicon- germanium-carbon, III-V compounds, II-VII compounds, epitaxial layers over such substrates, or any other semiconducting material.
  • the substrate may include integrated circuits fabricated therein.
  • An insulating layer 102 is formed over substrate 100.
  • the insulating layer 102 can be silicon oxide, silicon nitride, high-dielectric film, Si-C-O-H film, or any other suitable insulating material.
  • the first conductors 200 are formed over the substrate and insulator.
  • An adhesion layer 104 may be included between the insulating layer 102 and the conducting layer 106 to help conducting layer 106 adhere to insulating layer 102. If the overlying conducting layer is tungsten, titanium nitride is preferred as adhesion layer 104.
  • Conducting layer 106 can comprise any conducting material known in the art, such as tungsten, or other materials, including tantalum, titanium, copper, cobalt, or alloys thereof.
  • the layers will be patterned and etched using any suitable masking and etching process to form substantially parallel, substantially coplanar conductors 200, shown in Fig. 15a in cross-section.
  • photoresist is deposited, patterned by photolithography and the layers etched, and then the photoresist removed using standard process techniques.
  • Conductors 200 could be formed by a Damascene method instead.
  • Dielectric material 108 is deposited over and between conductor rails 200.
  • Dielectric material 108 can be any known electrically insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In a preferred embodiment, silicon dioxide is used as dielectric material 108.
  • a barrier layer 110 is deposited as the first layer after planarization of the conductor rails.
  • Any suitable material can be used in the barrier layer, including tungsten nitride, tantalum nitride, titanium nitride, or combinations of these materials.
  • titanium nitride is used as the barrier layer.
  • the barrier layer is titanium nitride, it can be deposited in the same manner as the adhesion layer described earlier.
  • the semiconductor material can be silicon, germanium, a silicon- germanium alloy, or other suitable semiconductors, or semiconductor alloys.
  • silicon germanium
  • a silicon- germanium alloy or other suitable semiconductors, or semiconductor alloys.
  • this description will refer to the semiconductor material as silicon, but it will be understood that the skilled practitioner may select any of these other suitable materials instead.
  • the pillar comprises a semiconductor junction diode.
  • junction diode is used herein to refer to a semiconductor device with the property of non-ohmic conduction, having two terminal electrodes, and made of semiconducting material which is p-type at one electrode and n-type at the other. Examples include p-n diodes and n-p diodes, which have p-type semiconductor material and n-type semiconductor material in contact, such as Zener diodes, and p-i-n diodes, in which intrinsic (undoped) semiconductor material is interposed between p- type semiconductor material and n-type semiconductor material.
  • Bottom heavily doped region 112 can be formed by any deposition and doping method known in the art.
  • the silicon can be deposited and then doped, but is preferably doped in situ by flowing a donor gas providing n-type dopant atoms, for example phosphorus, during deposition of the silicon.
  • Heavily doped region 112 is preferably between about 100 and about 800 angstroms thick.
  • Pillars 300 should have about the same pitch and about the same width as conductors 200 below, such that each pillar 300 is formed on top of a conductor 200. Some misalignment can be tolerated.
  • the pillars 300 can be formed using any suitable masking and etching process.
  • photoresist can be deposited, patterned using standard photolithography techniques, and etched, then the photoresist removed.
  • a hard mask of some other material for example silicon dioxide, can be formed on top of the semiconductor layer stack, with bottom antireflective coating (BARC) on top, then patterned and etched.
  • BARC bottom antireflective coating
  • DARC dielectric antireflective coating
  • Dielectric material 108 is deposited over and between the semiconductor pillars 300, filling the gaps between them.
  • Dielectric material 108 can be any known electrically insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In a preferred embodiment, silicon dioxide is used as the insulating material.
  • the dielectric material on top of the pillars 300 is removed, exposing the tops of pillars 300 separated by dielectric material 108, and leaving a substantially planar surface.
  • This removal of dielectric overfill can be performed by any process known in the art, such as CMP or etchback.
  • CMP or etchback ion implantation is performed, forming heavily doped p-type top region 116.
  • the p-type dopant is preferably boron or BCl 3 .
  • This implant step completes formation of diodes 111.
  • the resulting structure is shown in Fig. 15b. In the diodes just formed, bottom heavily doped regions 112 are n-type while top heavily doped regions 116 are p-type; clearly the polarity could be reversed.
  • an antifuse dielectric layer 1 18 is formed on top of each heavily doped region 116.
  • Antifuse 118 is preferably a 10 to 100 Angstrom thick metal oxide layer formed by any suitable deposition method, such as sputtering. If desired, the pillar 300 patterning step may alternatively take place after the deposition of the antifuse dielectric layer 118 deposition step such that layer 118 becomes part of the pillar 300.
  • Top conductors 400 can be formed in the same manner as bottom conductors 200, for example by depositing adhesion layer 120, preferably of titanium nitride, and conductive layer 122, preferably of tungsten. Conductive layer 122 and adhesion layer 120 are then patterned and etched using any suitable masking and etching technique to form substantially parallel, substantially coplanar conductors 400, shown in Fig. 15c extending left-to-right across the page. In a preferred embodiment, photoresist is deposited, patterned by photolithography and the layers etched, and then the photoresist removed using standard process techniques.
  • the dielectric material can be any known electrically insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In a preferred embodiment, silicon oxide is used as this dielectric material.
  • first memory level Formation of a first memory level has been described. Additional memory levels can be formed above this first memory level to form a monolithic three dimensional memory array.
  • conductors can be shared between memory levels; i.e. top conductor 400 would serve as the bottom conductor of the next memory level.
  • an interlevel dielectric (not shown) is formed above the first memory level of Fig. 15c, its surface planarized, and construction of a second memory level begins on this planarized interlevel dielectric, with no shared conductors.
  • a monolithic three dimensional memory array is one in which multiple memory levels are formed above a single substrate, such as a wafer, with no intervening substrates.
  • the layers forming one memory level are deposited or grown directly over the layers of an existing level or levels.
  • stacked memories have been constructed by forming memory levels on separate substrates and adhering the memory levels atop each other, as in Leedy, US Patent No. 5,915,167, "Three dimensional structure memory.”
  • the substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three dimensional memory arrays.
  • a monolithic three dimensional memory array formed above a substrate comprises at least a first memory level formed at a first height above the substrate and a second memory level formed at a second height different from the first height. Three, four, eight, or indeed any number of memory levels can be formed above the substrate in such a multilevel array.
  • An alternative method for forming a similar array in which conductors are formed using Damascene construction is described in Radigan et al., US Patent Application No. 11/444,936, "Conductive Hard Mask to Protect Patterned Features During Trench Etch," filed May 31, 2006, assigned to the assignee of the present invention and hereby incorporated by reference. The methods of Radigan et al. may be used instead to form an array according to the present invention.
  • a memory cell having its data state stored in the resistivity state of polycrystalline or microcrystalline semiconductor material are possible and fall within the scope of the invention.
  • the positions of the p-type region 8 and the n-type region 4 in the diode 2 may be reversed such that the p-type region 8 is located on the bottom of the vertical diode and the n-type region 4 is located at the top of the diode 2.
  • Figs. 16a and 16b illustrate two different exemplary memory cells.
  • Fig. 16a illustrates a cell where the metal oxide antifuse dielectric layer 14 is located over the diode. Specifically, the antifuse dielectric layer 14 is located on the p-type region 8 of the diode.
  • the antifuse dielectric layer 14 is located below the diode 2. Specifically, the metal oxide (Al 2 O 3 ) antifuse dielectric layer 14 is separated from the n-type silicon region 4 of the diode by a titanium nitride layer 110. Thus, the Al 2 O 3 antifuse dielectric layer 14 is located between the W layer 106 and the TiN layer 1 10 in a MIM (metal-insulator-metal) structure underneath the diode in the cell shown in Fig. 16b. A titanium layer 124 is located between the p-type region of the diode 2 and the upper titanium nitride layer 120.
  • a titanium layer 124 is located between the p-type region of the diode 2 and the upper titanium nitride layer 120.
  • Fig. 17a is a probability plot comparing the read current of the memory cell shown in Fig. 16a containing a 10 Angstrom thick aluminum oxide antifuse dielectric layer (squares) with a similar memory cell containing a 16 Angstrom thick silicon dioxide antifuse dielectric layer (circles). Both cells were programmed with a +8V pulse. As can be seen in Fig. 17a, the read current of the programmed cell with the aluminum oxide antifuse dielectric layer was 30 microamperes at 2 V read voltage, while the read current of the programmed cell with the silicon dioxide antifuse dielectric layer was 20 microamperes at 2 V read voltage. Thus, the use of the aluminum oxide instead of silicon oxide antifuse dielectric layer provides a 50% improvement in the read current.
  • Fig. 17b is a probability plot showing the read current of the memory cell shown in Fig. 16a containing a 30 Angstrom thick hafnium oxide (HfO 2 ) antifuse dielectric layer.
  • the cell was programmed with a +10V pulse.
  • the read current of the programmed cell was 30 microamperes at 2 V read voltage.
  • Fig. 17c is a probability plot comparing the read current of the programmed memory cell shown in Fig. 16a to that of the programmed memory cell shown in Fig. 16b. While both cells have a similar thickness Al 2 O 3 antifuse, the architecture of Fig. 16a with the Al 2 O 3 on top of the diode in contact with the p+- doped silicon region 8 shows a much high forward current than the architecture of Fig. 16b.
  • the antifuse dielectric in the MIM configuration shown in Fig. 16b resulted in a decreased read current, as shown in Fig. 17c, and is not preferred for applications where a high read current is desired.
  • the present inventor believes that it is possible that the Al in Al 2 O 3 layer diffuses and mixes into the p-type silicon region 8 of the diode during programming, resulting in a higher forward current.
  • the p-type region of the diode contains aluminum diffused from the antifuse dielectric layer after the cell is programmed and the conductive link is formed through the dielectric layer. Since Al is a p-type dopant in silicon, this p-type dopant would increase the forward current of the diode due to the better ohmic contact of the p-type region 8 with an adjacent electrode due to the higher concentration of the p- type dopant in the region 8.
  • Hafnium is also a p-type dopant in silicon and can act in the same manner as aluminum, possibly accounting for the result shown in Fig. 17b.
  • metals other than aluminum from the metal oxide antifuse dielectric generally have much lower solubilities in silicon than aluminum. Thus, they should produce a lower p-type carrier concentration in silicon than aluminum if they diffused into the silicon from the antifuse dielectric layer.
  • Al has a solubility of greater than 1x10 20 cm "3 at 700C in Si
  • Hf is estimated to have a solubility of less than 1 ppm (less than 1x10 17 cm "3 ) at elevated temperatures in Si.

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Abstract

Un dispositif de mémoire non volatile comprend au moins une cellule de mémoire qui comprend une diode et une couche diélectrique anti-fusible d'oxyde métallique, et une première électrode et une seconde électrode en contact électrique avec ladite au moins une cellule de mémoire. En utilisation, la diode agit en tant qu'élément de lecture/écriture de la cellule de mémoire en commutant d'un premier état de résistivité vers un second état de résistivité différent du premier état de résistivité en réponse à une polarisation appliquée.
PCT/US2008/007802 2007-06-25 2008-06-23 Diodes à courant direct élevé pour une cellule 3d à écriture inverse et procédé de fabrication de ces diodes WO2009002477A1 (fr)

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JP2010513272A JP2010531543A (ja) 2007-06-25 2008-06-23 逆方向書き込み３次元セルに用いる高順方向電流ダイオードおよびその製造方法
CN200880021393A CN101720485A (zh) 2007-06-25 2008-06-23 用于反向写入3d单元的高正向电流二极管及其制造方法
EP08768726A EP2165336A1 (fr) 2007-06-25 2008-06-23 Diodes à courant direct élevé pour une cellule 3d à écriture inverse et procédé de fabrication de ces diodes

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