WO2008156282A2 - Etching method for next generation semiconductor process - Google Patents

Etching method for next generation semiconductor process Download PDF

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Publication number
WO2008156282A2
WO2008156282A2 PCT/KR2008/003411 KR2008003411W WO2008156282A2 WO 2008156282 A2 WO2008156282 A2 WO 2008156282A2 KR 2008003411 W KR2008003411 W KR 2008003411W WO 2008156282 A2 WO2008156282 A2 WO 2008156282A2
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WO
WIPO (PCT)
Prior art keywords
etching method
etching
process parameter
etch
next generation
Prior art date
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PCT/KR2008/003411
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French (fr)
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WO2008156282A3 (en
Inventor
Young Kim
Original Assignee
Nest Corp.
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Filing date
Publication date
Application filed by Nest Corp. filed Critical Nest Corp.
Publication of WO2008156282A2 publication Critical patent/WO2008156282A2/en
Publication of WO2008156282A3 publication Critical patent/WO2008156282A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Definitions

  • the present invention relates to a method for manufacturing semiconductor devices, and more particularly to an etching method for manufacturing next generation semiconductor devices, the critical dimension of which decreases gradually.
  • a recipe as a semiconductor manufacturing process is completed by performing a number of recipe steps.
  • a conventional recipe as an etching process for manufacturing semiconductor devices includes a BT (Breakthrough) step for removing the native oxide, etc. formed on the etch target layer, a ME (Main Etch) step for etching the etch target layer into a desired profile, and an OE (Over Etch) step for removing residues, etc. which may remain after the ME step, as depicted in FIG. 1.
  • Each recipe step (BT, ME, and OE steps) constituting the etch step is performed by using process parameters such as a flow rate, pressure, temperature, magnetic field, and RF power, each of which has a fixed physical quantity suited to the corresponding recipe step.
  • CD critical dimension
  • the conventional recipe construction algorithm e.g. etching method
  • the present invention has been made to solve the above-mentioned problems occurring in the prior art, and the present invention provides an etching method for a next generation semiconductor process so that a uniform CD can be realized by controlling process parameters more flexibly in each step for a given recipe without segmenting the recipe into tens or hundreds of recipe steps.
  • an etching method for a next generation semiconductor etching process conducted based on a fixed process parameter condition including the steps of (a) defining the fixed process parameter condition as a new condition having a predetermined range; and (b) changing a corresponding process parameter gradually over time within the range of the defined condition.
  • the process parameter may be controlled to change linearly as an example, or controlled to change non-linearly as another example.
  • an etching method for a next generation semiconductor etching process including a breakthrough step, a main etch step, and an over etch step, the etching method including the steps of: (a) setting a range of at least one of process parameters including a flow rate, pressure, temperature, magnetic field, and RF power in at least one of the breakthrough, main etch, and over etch steps; and (b) changing the corresponding process parameter gradually over time within the set range.
  • the process parameter may be controlled to change linearly as example, or controlled to change non-linearly as another example.
  • FIG. 1 is a diagram for describing an etching method according to the prior art
  • FIG. 2 is a diagram for describing an etching method for a next generation semiconductor process according to a first embodiment of the present invention
  • FIG. 3 is a diagram showing a comparison of etching profiles of current and next generation contact holes according to the etching methods shown in FIGs. 1 and 2, respectively;
  • FIG. 4 is a diagram for describing pressure conditions and resulting contact hole etching profiles in the ME step according to the first embodiment of the present invention
  • FIG. 5 is a diagram for describing flow rate conditions and resulting contact hole etching profiles in the ME step according to the first embodiment of the present invention
  • FIG. 6 is a diagram for describing source power conditions and resulting contact hole etching profiles in the ME step according to the first embodiment of the present invention
  • FIG. 7 is a diagram for describing an etching method for a next generation semiconductor process according to a second embodiment of the present invention.
  • FIG. 8 is a diagram showing a comparison of etching profiles of current and next generation contact holes according to the etching methods shown in FIGs. 1, 2 and 7, respectively;
  • FIG. 9 is a diagram for describing pressure conditions and resulting contact hole etching profiles in the ME step according to the second embodiment of the present invention.
  • FIG. 10 is a diagram for describing flow rate conditions and resulting contact hole etching profiles in the ME step according to the second embodiment of the present invention.
  • FIG. 11 is a diagram for describing source power conditions and resulting contact hole etching profiles in the ME step according to the second embodiment of the present invention.
  • FIG. 2 is a diagram for describing an etching method for a next generation semiconductor process according to a first embodiment of the present invention.
  • a recipe includes a BT step, a ME step, and an OE step, and process parameters in respective steps (BT, ME, and OE) are controlled to gradually increase or decrease linearly over time within a predetermined range.
  • the process parameter in the BT step is controlled to gradually increase linearly over time within a predetermined range as indicated by the line segment 21;
  • the process parameter in the ME step is controlled to gradually decrease linearly over time within a predetermined range as indicated by the line segment 22;
  • the process parameter in the OE step is controlled to gradually decrease linearly over time within a predetermined range as indicated by the line segment 23.
  • etching conditions including a flow rate, pressure, temperature, magnetic field, and RF power, for example.
  • the process parameter in the case of the embodiment shown in FIG. 2 corresponds to pressure.
  • the increasing line segment in each step (BT, ME, and OE) of FIG. 2 may be replaced with a decreasing line, or vice versa, and the corresponding slope may also be varied.
  • FIG. 3 is a diagram showing a comparison of etching profiles of current and next generation contact holes according to the etching methods shown in FIGs. 1 and 2, respectively.
  • etching is limited), but in the case of the etching profile of the contact hole of the next generation device obtained by the etching method according to the first embodiment of the present invention shown in FIG. 2, a contact hole is formed normally with no etch limit although the bottom CD is slightly narrower than the top CD.
  • FIG. 4 is a diagram for describing pressure conditions and resulting contact hole etching profiles in the ME step according to the prior art and the first embodiment of the present invention, respectively.
  • FIG. 5 is a diagram for describing flow rate conditions and resulting contact hole etching profiles in the ME step according to the prior art and the first embodiment of the present invention, respectively.
  • FIG. 6 is a diagram for describing source power conditions and resulting contact hole etching profiles in the ME step according to the prior art and the first embodiment of the present invention, respectively.
  • FIG. 7 is a diagram for describing an etching method for a next generation semiconductor process according to a second embodiment of the present invention.
  • a recipe includes a BT step, a ME step, and an OE step, and process parameters in respective steps (BT, ME and, OE) are controlled to gradually increase or decrease non-linearly over time within a predetermined range.
  • the process parameter in the BT step is controlled to gradually increase non-linearly over time within a predetermined range as indicated by the convex curve 71a or the concave curve 71b;
  • the process parameter in the ME step is controlled to gradually decrease non-linearly over time within a predetermined range as indicated by the convex curve 72a or the concave curve 72b;
  • the process parameter in the OE step is controlled to gradually decrease non-linearly over time within a predetermined range as indicated by the convex curve 73a or the concave curve 73b.
  • the process parameter in FIG. 7 may be one of etching conditions including a flow rate, pressure, temperature, magnetic field, and RF power, for example.
  • the process parameter in the case of the embodiment shown in FIG. 7 corresponds to pressure.
  • the increasing curve in each step (BT, ME, and OE) of FIG. 7 may be replaced with a decreasing curve, or vice versa, and the corresponding curvature may also be varied.
  • FIG. 8 is a diagram showing a comparison of etching profiles of current and next generation contact holes according to the etching methods shown in FIGs. 1, 2 and 7, respectively.
  • the bottom CD is slightly narrower than the top CD, but a contact hole is formed normally with no etch limit when the etching method according to the first embodiment of the present invention shown in FIG. 2 is used; and the bottom CD is broader when the etching method according to the second embodiment of the present invention shown in FIG. 7 is used than when the etching method according to the first embodiment is used.
  • FIG. 9 is a diagram for describing pressure conditions and resulting contact hole etching profiles in the ME step according to the prior art and the second embodiment of the present invention, respectively.
  • FIG. 10 is a diagram for describing flow rate conditions and resulting contact hole etching profiles in the ME step according to the prior art and the second embodiment of the present invention, respectively.
  • FIG. 11 is a diagram for describing source power conditions and resulting contact hole etching profiles in the ME step according to the prior art and the second embodiment of the present invention, respectively.
  • the etching method for a next generation semiconductor process according to the present invention is advantageous in that during a next generation semiconductor process, the etch rate, etch profile, selectivity, and contact etching process performance regarding the top/bottom CD are improved substantially, making it is possible to overcome the etch limit of the contact CD that is gradually becoming smaller and deeper.

Abstract

Disclosed is an etching method for a next generation semiconductor etching process including a breakthrough step, a main etch step, and an over etch step, the etching method including the steps of (a) setting a range of at least one of process parameters including a flow rate, pressure, temperature, magnetic field, and RF power in at least one of the breakthrough, main etch, and over etch steps; and (b) gradually changing the corresponding process parameter linearly or non- linearly over time within the set range. During a next generation semiconductor process, the etch rate, etch profile, selectivity, and contact etching process performance regarding the top/bottom CD are improved substantially, making it is possible to overcome the etch limit of the contact CD that is gradually becoming smaller and deeper.

Description

Description
ETCHING METHOD FOR NEXT GENERATION SEMICONDUCTOR PROCESS
Technical Field
[1] The present invention relates to a method for manufacturing semiconductor devices, and more particularly to an etching method for manufacturing next generation semiconductor devices, the critical dimension of which decreases gradually. Background Art
[2] Generally, a recipe as a semiconductor manufacturing process is completed by performing a number of recipe steps. For example, a conventional recipe as an etching process for manufacturing semiconductor devices includes a BT (Breakthrough) step for removing the native oxide, etc. formed on the etch target layer, a ME (Main Etch) step for etching the etch target layer into a desired profile, and an OE (Over Etch) step for removing residues, etc. which may remain after the ME step, as depicted in FIG. 1.
[3] Each recipe step (BT, ME, and OE steps) constituting the etch step is performed by using process parameters such as a flow rate, pressure, temperature, magnetic field, and RF power, each of which has a fixed physical quantity suited to the corresponding recipe step.
[4] The degree of integration of semiconductor devices has recently been increasing, and the critical dimension (hereinafter, referred to as CD) is becoming smaller. Therefore, in order to maintain etching uniformity, the process parameters need to be controlled precisely.
[5] The current recipe construction algorithm for more precise process parameters requires that a recipe be segmented into tens or hundreds of recipe steps, and that the process parameters be changed and controlled for respective steps, which is impractical.
[6] Although the conventional etching method depicted in FIG. 1 may be good for rough process performance, better process control requires that some parameters be changed for each recipe step.
[7] For example, it is assumed that the final bottom CD of a contact hole needs to be the same as the top one. The conventional recipe construction algorithm (e.g. etching method) then requires that the recipe be segmented into tens or hundreds of recipe steps to maintain uniform top and bottom CDs by controlling each of specific process parameters at a fixed value in each recipe step, which is impractical.
[8] In summary, the conventional recipe construction algorithm (e.g. etching method) has a problem in that it is very difficult to maintain uniform top and bottom CDs during a next generation semiconductor manufacturing process. Disclosure of Invention
Technical Solution
[9] Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and the present invention provides an etching method for a next generation semiconductor process so that a uniform CD can be realized by controlling process parameters more flexibly in each step for a given recipe without segmenting the recipe into tens or hundreds of recipe steps.
[10] In accordance with an aspect of the present invention, there is provided an etching method for a next generation semiconductor etching process conducted based on a fixed process parameter condition, the etching method including the steps of (a) defining the fixed process parameter condition as a new condition having a predetermined range; and (b) changing a corresponding process parameter gradually over time within the range of the defined condition. In step (b), the process parameter may be controlled to change linearly as an example, or controlled to change non-linearly as another example.
[11] In accordance with a more specific aspect of the present invention, there is provided an etching method for a next generation semiconductor etching process including a breakthrough step, a main etch step, and an over etch step, the etching method including the steps of: (a) setting a range of at least one of process parameters including a flow rate, pressure, temperature, magnetic field, and RF power in at least one of the breakthrough, main etch, and over etch steps; and (b) changing the corresponding process parameter gradually over time within the set range. In step (b), the process parameter may be controlled to change linearly as example, or controlled to change non-linearly as another example. Brief Description of the Drawings
[12] FIG. 1 is a diagram for describing an etching method according to the prior art;
[13] FIG. 2 is a diagram for describing an etching method for a next generation semiconductor process according to a first embodiment of the present invention;
[14] FIG. 3 is a diagram showing a comparison of etching profiles of current and next generation contact holes according to the etching methods shown in FIGs. 1 and 2, respectively;
[15] FIG. 4 is a diagram for describing pressure conditions and resulting contact hole etching profiles in the ME step according to the first embodiment of the present invention;
[16] FIG. 5 is a diagram for describing flow rate conditions and resulting contact hole etching profiles in the ME step according to the first embodiment of the present invention;
[17] FIG. 6 is a diagram for describing source power conditions and resulting contact hole etching profiles in the ME step according to the first embodiment of the present invention;
[18] FIG. 7 is a diagram for describing an etching method for a next generation semiconductor process according to a second embodiment of the present invention;
[19] FIG. 8 is a diagram showing a comparison of etching profiles of current and next generation contact holes according to the etching methods shown in FIGs. 1, 2 and 7, respectively;
[20] FIG. 9 is a diagram for describing pressure conditions and resulting contact hole etching profiles in the ME step according to the second embodiment of the present invention;
[21] FIG. 10 is a diagram for describing flow rate conditions and resulting contact hole etching profiles in the ME step according to the second embodiment of the present invention; and
[22] FIG. 11 is a diagram for describing source power conditions and resulting contact hole etching profiles in the ME step according to the second embodiment of the present invention.
Mode for the Invention
[23] Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In the following description and drawings, the same reference numerals are used to designate the same or similar components, and so repetition of the description on the same or similar components will be omitted. Furthermore, a detailed description of known functions and configurations incorporated herein is omitted to avoid making the subject matter of the present invention unclear.
[24] FIG. 2 is a diagram for describing an etching method for a next generation semiconductor process according to a first embodiment of the present invention.
[25] As depicted in FIG. 2, a recipe includes a BT step, a ME step, and an OE step, and process parameters in respective steps (BT, ME, and OE) are controlled to gradually increase or decrease linearly over time within a predetermined range. Particularly, the process parameter in the BT step is controlled to gradually increase linearly over time within a predetermined range as indicated by the line segment 21; the process parameter in the ME step is controlled to gradually decrease linearly over time within a predetermined range as indicated by the line segment 22; and the process parameter in the OE step is controlled to gradually decrease linearly over time within a predetermined range as indicated by the line segment 23. [26] The process parameter in FIG. 2 may be one of etching conditions including a flow rate, pressure, temperature, magnetic field, and RF power, for example. The process parameter in the case of the embodiment shown in FIG. 2 corresponds to pressure. When a process parameter other than pressure is to be controlled, the increasing line segment in each step (BT, ME, and OE) of FIG. 2 may be replaced with a decreasing line, or vice versa, and the corresponding slope may also be varied.
[27] FIG. 3 is a diagram showing a comparison of etching profiles of current and next generation contact holes according to the etching methods shown in FIGs. 1 and 2, respectively.
[28] It is clear from FIG. 3 that in the case of the etching profile of the contact hole of the current device obtained by the conventional etching method shown in FIG. 1, the bottom CD is much narrower than the top CD, but in the case of the etching profile of the contact hole of the current device obtained by the etching method according to the first embodiment of the present invention shown in FIG. 2, there is little difference between the top and bottom CDs. It is also clear from FIG. 3 that in the case of the etching profile of the contact hole of the next generation device, the CD of which is smaller than that of the current device, obtained by the conventional etching method shown in FIG. 1, the bottom CD radically decreases to 0 (i.e. etching is limited), but in the case of the etching profile of the contact hole of the next generation device obtained by the etching method according to the first embodiment of the present invention shown in FIG. 2, a contact hole is formed normally with no etch limit although the bottom CD is slightly narrower than the top CD.
[29] An application of the etching method according to the first embodiment of the present invention to a ME step to control a specific process parameter will now be described in detail with reference to FIGs. 4-6.
[30] FIG. 4 is a diagram for describing pressure conditions and resulting contact hole etching profiles in the ME step according to the prior art and the first embodiment of the present invention, respectively.
[31] It is clear from (a) of FIG. 4 that when etching is conducted for 40 seconds on the condition that the pressure is fixed at 9OmT in the ME step by using the etching method according to the prior art, the bottom CD is much narrower than the top CD. In contrast, it is clear from (b) of FIG. 4 that when etching is conducted for 40 seconds while controlling the pressure to change linearly from the initial pressure of 9OmT to the final pressure of 6OmT over time in the ME step by using the etching method according to the first embodiment of the present invention, there is little difference between the top and bottom CDs. In FIG. 4, Hl and H2 represent the etch depth, and H1≠H2.
[32] FIG. 5 is a diagram for describing flow rate conditions and resulting contact hole etching profiles in the ME step according to the prior art and the first embodiment of the present invention, respectively.
[33] It is clear from (a) of FIG. 5 that when etching is conducted for 60 seconds on the condition that the flow rate of C4F6 gas is fixed at 50sccm in the ME step by using the etching method according to the prior art, the etch rate decreases gradually over time, and that the bottom CD (d3) is much narrower than the top CD (D3) in the end. H3 represents the etch depth.
[34] In contrast, it is clear from (b) of FIG. 5 that when etching is conducted for 60 seconds on the condition that the flow rate of C4F6 gas is controlled to change linearly from the initial flow rate of 30sccm to the final flow rate of 60sccm over time in the ME step by using the etching method according to the first embodiment of the present invention, the etch rate increases gradually, and that there is little difference between the top CD (D4) and the bottom CD (d4) in the end. In FIG. 5, H4 represents the etch depth, and D3 > D4, d3 < d4, H4 < H3.
[35] FIG. 6 is a diagram for describing source power conditions and resulting contact hole etching profiles in the ME step according to the prior art and the first embodiment of the present invention, respectively.
[36] It is clear from (a) of FIG. 6 that when etching is conducted for 60 seconds on the condition that the source power is fixed at 2000W in the ME step by using the etching method according to the prior art, the etch rate decreases gradually over time, and that the bottom CD (d3) is much narrower than the top CD (D3) in the end.
[37] In contrast, it is clear from (b) of FIG. 6 that when etching is conducted for 60 seconds on the condition that the source power is controlled to change linearly from the initial source power of 1500W to the final source power of 2500W over time in the ME step by using the etching method according to the first embodiment of the present invention, the etch rate increases gradually, and that there is little difference between the top CD (D4) and the bottom CD (d4) in the end. In FIG. 6, H3 and H4 represent the etch depth, and D3 > D4, d3 < d4, H4 < H3.
[38] FIG. 7 is a diagram for describing an etching method for a next generation semiconductor process according to a second embodiment of the present invention.
[39] As shown in FIG. 7, a recipe includes a BT step, a ME step, and an OE step, and process parameters in respective steps (BT, ME and, OE) are controlled to gradually increase or decrease non-linearly over time within a predetermined range. Particularly, the process parameter in the BT step is controlled to gradually increase non-linearly over time within a predetermined range as indicated by the convex curve 71a or the concave curve 71b; the process parameter in the ME step is controlled to gradually decrease non-linearly over time within a predetermined range as indicated by the convex curve 72a or the concave curve 72b; and the process parameter in the OE step is controlled to gradually decrease non-linearly over time within a predetermined range as indicated by the convex curve 73a or the concave curve 73b.
[40] The process parameter in FIG. 7 may be one of etching conditions including a flow rate, pressure, temperature, magnetic field, and RF power, for example. The process parameter in the case of the embodiment shown in FIG. 7 corresponds to pressure. When a process parameter other than pressure is to be controlled, the increasing curve in each step (BT, ME, and OE) of FIG. 7 may be replaced with a decreasing curve, or vice versa, and the corresponding curvature may also be varied.
[41] FIG. 8 is a diagram showing a comparison of etching profiles of current and next generation contact holes according to the etching methods shown in FIGs. 1, 2 and 7, respectively.
[42] It is clear from FIG. 8 that in the case of the etching profile of the contact hole of the current device, the bottom CD is much narrower than the top CD when the etching method according to the prior art shown in FIG. 1 is used; there is little difference between the top and bottom CDs when the etching method according to the first embodiment of the present invention shown in FIG. 2 is used; and there is similarly little difference between the top and bottom CDs when the etching method according to the second embodiment of the present invention is used. In the case of the etching profile of the contact hole of the next generation device, the CD of which is smaller than that of the current device, the bottom CD radically decreases to 0 (i.e. etching is limited) when the etching method according to the prior art shown in FIG. 1 is used; the bottom CD is slightly narrower than the top CD, but a contact hole is formed normally with no etch limit when the etching method according to the first embodiment of the present invention shown in FIG. 2 is used; and the bottom CD is broader when the etching method according to the second embodiment of the present invention shown in FIG. 7 is used than when the etching method according to the first embodiment is used.
[43] An application of the etching method according to the second embodiment of the present invention to a ME step to control a specific process parameter will now be described in detail with reference to FIGs. 9-11.
[44] FIG. 9 is a diagram for describing pressure conditions and resulting contact hole etching profiles in the ME step according to the prior art and the second embodiment of the present invention, respectively.
[45] It is clear from (a) of FIG. 9 that when etching is conducted for 40 seconds on the condition that the pressure is fixed at 9OmT in the ME step by using the etching method according to the prior art, the bottom CD is much narrower than the top CD. In contrast, it is clear from (b) of FIG. 9 that when etching is conducted for 40 seconds while controlling the pressure to change non-linearly from the initial pressure of 9OmT to the final pressure of 6OmT over time in the ME step by using the etching method according to the second embodiment of the present invention, there is little difference between the top and bottom CDs. In FIG. 9, Hl and H2 represent the etch depth, and H2>H1.
[46] FIG. 10 is a diagram for describing flow rate conditions and resulting contact hole etching profiles in the ME step according to the prior art and the second embodiment of the present invention, respectively.
[47] It is clear from (a) of FIG. 10 that when etching is conducted for 60 seconds on the condition that the flow rate of C4F6 gas is fixed at 50sccm in the ME step by using the etching method according to the prior art, the etch rate decreases gradually over time, and that the bottom CD (d3) is much narrower than the top CD (D3) in the end. H3 represents the etch depth.
[48] In contrast, it is clear from (b) of FIG. 10 that when etching is conducted for 60 seconds on the condition that the flow rate of C4F6 gas is controlled to change non- linearly from the initial flow rate of 30sccm to the final flow rate of 60sccm over time in the ME step by using the etching method according to the second embodiment of the present invention, the etch rate increases gradually, and that there is little difference between the top CD (D4) and the bottom CD (d4) in the end. In FIG. 10, H4 represents the etch depth, and D3 > D4, d3 < d4, H4 < H3.
[49] FIG. 11 is a diagram for describing source power conditions and resulting contact hole etching profiles in the ME step according to the prior art and the second embodiment of the present invention, respectively.
[50] It is clear from (a) of FIG. 11 that when etching is conducted for 60 seconds on the condition that the source power is fixed at 2000W in the ME step by using the etching method according to the prior art, the etch rate decreases gradually over time, and that the bottom CD (d3) is much narrower than the top CD (D3) in the end.
[51] In contrast, it is clear from (b) of FIG. 11 that when etching is conducted for 60 seconds on the condition that the source power is controlled to change non-linearly from the initial source power of 1500W to the final source power of 2500W over time in the ME step by using the etching method according to the second embodiment of the present invention, the etch rate increases gradually, and that there is little difference between the top CD (D4) and the bottom CD (d4) in the end. In FIG. 11, H3 and H4 represent the etch depth, and D3 > D4, d3 < d4, H4 < H3.
[52] Although exemplary embodiments of the present invention have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. Therefore, the disclosed embodiments of the present invention are not for limiting the technical idea of the invention, but for describing it, and do not limit the scope of the present invention in any manner. The scope of the present invention is to be interpreted by the accompanying claims, and any technical idea in the equivalent range is to be regarded as included in the scope of the present invention. Industrial Applicability
[53] As described above, the etching method for a next generation semiconductor process according to the present invention is advantageous in that during a next generation semiconductor process, the etch rate, etch profile, selectivity, and contact etching process performance regarding the top/bottom CD are improved substantially, making it is possible to overcome the etch limit of the contact CD that is gradually becoming smaller and deeper.

Claims

Claims
[I] An etching method for a next generation semiconductor etching process conducted based on a fixed process parameter condition, the etching method comprising the steps of:
(a) defining the fixed process parameter condition as a new condition having a predetermined range; and
(b) changing a corresponding process parameter gradually over time within the range of the defined condition.
[2] The etching method as claimed in claim 1, wherein, in step (b), the process parameter is changed linearly. [3] The etching method as claimed in claim 1, wherein, in step (b), the process parameter is changed non-linearly. [4] The etching method as claimed in claim 2 or 3, wherein the semiconductor etching process is a main etch step. [5] The etching method as claimed in claim 4, wherein the process parameter is pressure. [6] The etching method as claimed in claim 5, wherein the pressure decreases gradually. [7] The etching method as claimed in claim 4, wherein the process parameter is a flow rate. [8] The etching method as claimed in claim 7, wherein the flow rate increases gradually. [9] The etching method as claimed in claim 4, wherein the process parameter is source power. [10] The etching method as claimed in claim 9, wherein the source power increases gradually.
[I I] The etching method as claimed in claim 2 or 3, wherein the semiconductor etching process is a breakthrough step.
[12] The etching method as claimed in claim 2 or 3, wherein the semiconductor etching process is an over etch step. [13] The etching method as claimed in claim 1, wherein the process parameter is at least one of a flow rate, pressure, temperature, magnetic field, and RF power. [14] An etching method for a next generation semiconductor etching process comprising a breakthrough step, a main etch step, and an over etch step, the etching method comprising the steps of:
(a) setting a range of at least one of process parameters comprising a flow rate, pressure, temperature, magnetic field, and RF power in at least one of the steps; and
(b) changing the corresponding process parameter gradually over time within the set range. [15] The etching method as claimed in claim 14, wherein, in step (b), the process parameter is changed linearly. [16] The etching method as claimed in claim 14, wherein, in step (b), the process parameter is changed non-linearly.
PCT/KR2008/003411 2007-06-19 2008-06-17 Etching method for next generation semiconductor process WO2008156282A2 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990057280A (en) * 1997-12-29 1999-07-15 김영환 Etching method of semiconductor manufacturing process
JP2003077782A (en) * 2001-08-31 2003-03-14 Toshiba Corp Manufacturing method for semiconductor device
JP2003100610A (en) * 2001-09-26 2003-04-04 Dainippon Screen Mfg Co Ltd Control system for substrate treatment apparatus and substrate treatment apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990057280A (en) * 1997-12-29 1999-07-15 김영환 Etching method of semiconductor manufacturing process
JP2003077782A (en) * 2001-08-31 2003-03-14 Toshiba Corp Manufacturing method for semiconductor device
JP2003100610A (en) * 2001-09-26 2003-04-04 Dainippon Screen Mfg Co Ltd Control system for substrate treatment apparatus and substrate treatment apparatus

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WO2008156282A3 (en) 2009-02-26

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