CN109841475A - Preprocess method and wafer processing - Google Patents
Preprocess method and wafer processing Download PDFInfo
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- CN109841475A CN109841475A CN201711214717.6A CN201711214717A CN109841475A CN 109841475 A CN109841475 A CN 109841475A CN 201711214717 A CN201711214717 A CN 201711214717A CN 109841475 A CN109841475 A CN 109841475A
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Abstract
It includes: pre-treatment step that the present invention, which provides a kind of preprocess method and wafer processing, the preprocess method, forms protective layer in chamber inner wall；Protective layer modification step increases protective layer in the thickness in excessively thin region, and/or reduces protective layer in the thickness in blocked up region.Preprocess method provided by the invention; it not only can prevent metal and particle on chamber wall from fallen in technical process in wafer surface by forming protective layer; but also the uniformity of the protective layer can be improved, so as to improve defective workmanship and reduce because protective layer missing caused by component deterioration.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, and in particular, to a kind of preprocess method and wafer processing.
Background technique
In the semiconductor manufacturing industry, with the continuous renewal of integrated circuit manufacture process, process node is constantly progressive, to quarter
The requirement of the consistency of the critical size of the uniformity of etching technique and etching cavity, stability and process results etc. is increasingly
It is high.
But etching cavity carry out technique during, due to process residues, the loss and aging of hardware and cause
Process results offset (including etch rate offset, critical size offset), since defects count increases caused by particulate accumulation
Add etc. is all the problem of not can avoid during volume production, therefore, how to keep chamber stability and the technique between different chips
The consistency of initial environment, and the amounts of particles of chamber is reduced, it is one during process node constantly advances
Major issue.
Currently used scheme is guaranteed during volume production in such a way that dry method between piece is cleaned and is periodically safeguarded
Cavity environment between different chips reaches unanimity as far as possible, still, since chamber interior environment can in the long-term use constantly
Variation, causes chamber wall to have residue that can not remove, and chamber member occurs certain under the long-term bombardment effect of plasma
The consume of degree.
Summary of the invention
The present invention is directed at least solve one of the technical problems existing in the prior art, propose a kind of preprocess method and
Wafer processing not only can prevent metal and particle on chamber wall from falling in technical process by forming protective layer
Wafer surface is fallen in, but also the uniformity of the protective layer can be improved, so as to improve defective workmanship and reduce because of protection
Component deterioration caused by break loses.
A kind of preprocess method is provided to achieve the purpose of the present invention, comprising:
Pre-treatment step forms protective layer in chamber inner wall；
Protective layer modification step increases the protective layer in the thickness in excessively thin region, and/or reduces the protective layer in mistake
The thickness in thick region.
Preferably, in the protective layer modification step, compensation layer is formed in the chamber inner wall, and the compensation layer exists
The thickness in the excessively thin region is greater than the thickness in remaining region.
Preferably, it according to the excessively thin region in the indoor position of the chamber, sets chamber pressure and/or is passed through excitation line
Electric current in circle, so that thickness of the compensation layer in the excessively thin region is greater than the thickness in remaining region.
Preferably, in the protective layer modification step, the protective layer is performed etching, and etches the blocked up region
Protective layer thickness be greater than remaining region protective layer thickness.
Preferably, the process gas for performing etching use to the protective layer includes O2、NF3、SF6At least one of.
Preferably, the value range of the flow of process gas is in 10~2000sccm；The value range of radio-frequency power is 100
~5000W；The value range of chamber pressure is in 5~400mT；The value range of process time is in 5~60s.
Preferably, described pre- if the protective layer modification step is thickness of the increase protective layer in excessively thin region
The process time of processing step shortens relative to Conventional Time；
The Conventional Time is the process time for individually carrying out the pre-treatment step.
Preferably, described pre- if the protective layer modification step is thickness of the reduction protective layer in blocked up region
The process time of processing step is identical as Conventional Time；
The Conventional Time is the process time for individually carrying out the pre-treatment step.
Preferably, in the pre-treatment step, process gas include carbon containing fluorine gas perhaps siliceous gas or
Including mixed gas, the mixed gas includes the gas or siliceous gas of argon gas and/or oxygen and carbon containing fluorine.
Preferably, in the pre-treatment step, the value range of the flow of process gas is in 10~2000sccm；Radio frequency
The value range of power is in 100~5000W；The value range of chamber pressure is in 5~100mT；The value range of process time is 5
~60s.
As another technical solution, the present invention also provides a kind of wafer processings, comprising:
Carry out above-mentioned preprocess method provided by the invention；
Chip to be processed is passed in chamber；
It treats processed wafer and carries out technique；
The chip for completing technique is spread out of into the chamber；
Remove remaining by-product and the protective layer in the chamber.
Preferably, the preprocess method is carried out using identical process conditions and process time to different chips.
The invention has the following advantages:
Preprocess method provided by the invention comprising pre-treatment step and protective layer modification step, wherein pretreatment step
Rapid to be used to form protective layer in chamber inner wall, which can prevent metal and particle on chamber wall from falling in technical process
Wafer surface is fallen in, so as to improve product yield.Protective layer modification step is for increasing protective layer in the thickness in excessively thin region
Degree, and/or protective layer is reduced in the thickness in blocked up region, so as to improve the thickness uniformity of protective layer, and then can change
The kind defective workmanship generated because protective layer is blocked up, and/or component deterioration caused by being lacked because of protective layer, to improve portion
Part utilization rate reduces the time of periodic maintenance maintenance, improves utilization rate of equipment and installations.
Wafer processing provided by the invention not only may be used by using above-mentioned preprocess method provided by the invention
To prevent metal on chamber wall and particle from fallen in technical process in wafer surface by forming protective layer, so as to
To improve product yield；But also component deterioration caused by defective workmanship can be improved and reduced because of protective layer missing, thus
Element usage is improved, reduces the time of periodic maintenance maintenance, improves utilization rate of equipment and installations.
Detailed description of the invention
Fig. 1 is the flow diagram of preprocess method provided by the invention；
Fig. 2A is the chamber cross-sectional view carried out before preprocess method；
Fig. 2 B is the chamber cross-sectional view completed after pre-treatment step；
Fig. 2 C is the chamber cross-sectional view completed after protective layer modification step；
Fig. 3 is the flow diagram of wafer processing provided by the invention；
Fig. 4 A is chamber cross-sectional view when carrying out technique to workpiece to be processed chip；
Fig. 4 B is the chamber cross-sectional view completed after cleaning.
Specific embodiment
To make those skilled in the art more fully understand technical solution of the present invention, come with reference to the accompanying drawing to the present invention
The preprocess method and wafer processing of offer are described in detail.
Also referring to Fig. 1 to Fig. 2 C, preprocess method provided by the invention comprising:
Pre-treatment step forms protective layer 107 in chamber inner wall 103；
Protective layer modification step increases the protective layer 107 in the thickness in excessively thin region, and/or reduces protective layer 107 in mistake
The thickness in thick region.
By above-mentioned protective layer 107, it can prevent metal and particle on chamber inner wall 103 from falling in technical process
Wafer surface, so as to improve product yield.
By the way that the thickness uniformity of protective layer 107 can be improved by above-mentioned protective layer modification step, so as to improve
The defective workmanship generated because protective layer is blocked up, and/or because protective layer missing caused by component deterioration, to improve component
Utilization rate reduces the time of periodic maintenance maintenance, improves utilization rate of equipment and installations.
Here, excessively thin region refers to that the thickness of some region of protective layer 107 is lower than the thickness of process requirement, causes right
When chip carries out technique, the infiltration and defective component of plasma can not be prevented.Blocked up region refers to some region of protective layer
107 thickness is higher than the thickness of process requirement, causes in subsequent carry out cleaning process, to remove the time mistake of the protective layer 107
It is long, influence process efficiency.
If only carrying out above-mentioned pre-treatment step, and subsequent can be had the following problems without protective layer modification step: by
It is unevenly distributed in plasma, therefore will lead to the protective layer 107 being covered on quartz window 102 or chamber inner wall 103
It is in uneven thickness, to cause following problems: needing to extend the process time to increase the thickness of protective layer 107, at least to make to protect
The smallest region of the thickness of sheath 107 meets process requirement, but the biggish region of thickness of protective layer 107 can further result in
Subsequent cleaning processes are extended with removing the time of the protective layer 107.
In order to solve the above technical problem, the present invention provides pretreating process increase protective layer modification step, can
To be thickened to excessively thin region existing for protective layer 107, and blocked up region existing for protective layer 107 is carried out it is thinned, from
And the defective workmanship generated because protective layer is blocked up can be improved, and/or because protective layer missing caused by component deterioration.
Specifically, in above-mentioned protective layer modification step, compensation layer (not shown) is formed in chamber inner wall 103, and
Thickness of the compensation layer in excessively thin region is greater than the thickness in remaining region, so as to play the protective layer for thickening excessively thin region
107 effect.Further, it can set chamber pressure according to excessively thin region in the indoor position of chamber and/or be passed through excitation line
Electric current in circle 101, so that the thickness in the excessively thin region of compensation layer is greater than the thickness in remaining region.For example, if covering chamber inner wall
103 or the thickness of protective layer 107 of edge of quartz window 102 need to increase, then can by setting chamber pressure and/or
The deposition rate of the edge of the electric current being passed through in excitation coil 101, Lai Zengjia chamber inner wall 103 or quartz window 102, thus
The compensation layer thickness deposited at the position is set to be greater than remaining position.
Carrying out thinned specific method to blocked up region existing for protective layer 107 can be with are as follows: carves to protective layer 107
Erosion, and the protective layer thickness for etching blocked up region is greater than the protective layer thickness in remaining region.It further, can be by adjusting work
Skill condition, increase the etch rate in blocked up region, to make the Reducing thickness of the thickness of the protective layer 107 at blocked up region most
Greatly.
Preferably, the process gas for performing etching use to protective layer 107 includes O2、NF3、SF6At least one of.Work
The value range of the flow of skill gas is in 10~2000sccm, preferably in 50~500sccm；The value range of radio-frequency power exists
100~5000W, preferably in 1000~1800W；The value range of chamber pressure is in 5~400mT, preferably in 10~250mT；Work
The value range of skill time is in 5~60s, preferably in 5~15s.
It is further preferred that if above-mentioned protective layer modification step is to increase protective layer 107 in the thickness in excessively thin region, in advance
The process time of processing step shortens relative to Conventional Time.The Conventional Time is the independent pre-treatment step that carries out (without protecting
Sheath modification step) process time.In this way, not only can be to avoid the protective layer 107 after completing protective layer modification step
Final thickness is excessive, but also can make the overall process time of pre-treatment step will not extend or extend very much, so as to
Improve process efficiency.
If above-mentioned protective layer modification step is the thickness for reducing protective layer 107 in blocked up region, the work of pre-treatment step
The skill time is identical as above-mentioned Conventional Time.In this manner it is ensured that after completing protective layer modification step protective layer 107 it is final
Thickness is met the requirements.
Preferably, in pre-treatment step, process gas include carbon containing fluorine gas perhaps siliceous gas or including
Mixed gas, the mixed gas include the gas or siliceous gas of argon gas and/or oxygen and carbon containing fluorine.Process gas
The value range of the flow of body is in 10~2000sccm；The value range of radio-frequency power is in 100~5000W；Chamber pressure takes
It is worth range in 5~100mT；The value range of process time is in 5~60s.
In conclusion preprocess method provided by the invention, pre-treatment step is used to form protective layer in chamber inner wall,
The protective layer can prevent metal and particle on chamber wall from fallen in technical process in wafer surface, produce so as to improve
Product yield.Protective layer modification step is used to increase protective layer in the thickness in excessively thin region, and/or reduces protective layer in blocked up region
Thickness, lacked so as to improve the thickness uniformity of protective layer, and then can improve the technique that generates because protective layer is blocked up
Fall into, and/or because caused by protective layer missing component deterioration reduce periodic maintenance maintenance to improve element usage
Time, improve utilization rate of equipment and installations.
As another technical solution, Fig. 3 to Fig. 4 B is please referred to, the present invention also provides a kind of wafer processings, comprising:
S1 carries out above-mentioned preprocess method provided by the invention；
That is, above-mentioned pre-treatment step and protective layer modification step are successively carried out, finally in chamber inner wall 103 and medium window
A 102 covering protective layer 107.
Chip 104 to be processed is passed in chamber by S2；
It is provided with pedestal 105 in chamber, is passed into the indoor chip 104 to be processed of chamber and is placed on pedestal 105.
S3 treats processed wafer 104 and carries out technique；
Above-mentioned technique can be etching technics or depositing operation etc..As shown in Figure 4 A, after completion, in chamber
Wall 103 and medium window 102 can remain the substance to be cleaned 108 of matcoveredn and byproduct of reaction etc..
The chip for completing technique is spread out of chamber by S4；
S5 removes remaining above-mentioned substance 108 to be cleaned in chamber.
Preferably, above-mentioned preprocess method S1 is carried out using identical process conditions and process time to different chips.
In this way, it is capable of forming uniform property and the identical protective layer 107 of thickness before each chip can be made to start technique, thus
It can guarantee the consistency of the cavity environment when technique starts, while the stability during volume production can also be improved.
Wafer processing provided by the invention not only may be used by using above-mentioned preprocess method provided by the invention
To prevent metal on chamber wall and particle from fallen in technical process in wafer surface by forming protective layer, so as to
To improve product yield；But also component deterioration caused by defective workmanship can be improved and reduced because of protective layer missing, thus
Element usage is improved, reduces the time of periodic maintenance maintenance, improves utilization rate of equipment and installations.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present and the exemplary implementation that uses
Mode, however the present invention is not limited thereto.For those skilled in the art, essence of the invention is not being departed from
In the case where mind and essence, various changes and modifications can be made therein, these variations and modifications are also considered as protection scope of the present invention.
Claims (12)
1. a kind of preprocess method characterized by comprising
Pre-treatment step forms protective layer in chamber inner wall；
Protective layer modification step increases the protective layer in the thickness in excessively thin region, and/or reduces the protective layer in blocked up area
The thickness in domain.
2. preprocess method according to claim 1, which is characterized in that in the protective layer modification step, described
Chamber inner wall forms compensation layer, and thickness of the compensation layer in the excessively thin region is greater than the thickness in remaining region.
3. preprocess method according to claim 2, which is characterized in that indoor in the chamber according to the excessively thin region
Position, the electric current for setting chamber pressure and/or being passed through in excitation coil, so that thickness of the compensation layer in the excessively thin region
Greater than the thickness in remaining region.
4. preprocess method according to claim 1, which is characterized in that in the protective layer modification step, to described
Protective layer performs etching, and the protective layer thickness for etching the blocked up region is greater than the protective layer thickness in remaining region.
5. preprocess method according to claim 4, which is characterized in that the technique for performing etching use to the protective layer
Gas includes O2、NF3、SF6At least one of.
6. preprocess method according to claim 4, which is characterized in that the value range of the flow of process gas 10~
2000sccm；The value range of radio-frequency power is in 100~5000W；The value range of chamber pressure is in 5~400mT；Process time
Value range in 5~60s.
7. preprocess method according to claim 1, which is characterized in that if the protective layer modification step is described in increase
Protective layer is in the thickness in excessively thin region, then the process time of the pre-treatment step shortens relative to Conventional Time；
The Conventional Time is the process time for individually carrying out the pre-treatment step.
8. preprocess method according to claim 1, which is characterized in that if the protective layer modification step is described in reduction
Protective layer is in the thickness in blocked up region, then the process time of the pre-treatment step is identical as Conventional Time；
The Conventional Time is the process time for individually carrying out the pre-treatment step.
9. preprocess method according to claim 1, which is characterized in that in the pre-treatment step, process gas packet
Including the gas of carbon containing fluorine perhaps siliceous gas or including mixed gas, the mixed gas includes argon gas and/or oxygen,
And the gas or siliceous gas of carbon containing fluorine.
10. preprocess method according to claim 1, which is characterized in that in the pre-treatment step, process gas
The value range of flow is in 10~2000sccm；The value range of radio-frequency power is in 100~5000W；The value model of chamber pressure
It is trapped among 5~100mT；The value range of process time is in 5~60s.
11. a kind of wafer processing characterized by comprising
Carry out preprocess method described in claim 1-10 any one；
Chip to be processed is passed in chamber；
It treats processed wafer and carries out technique；
The chip for completing technique is spread out of into the chamber；
Remove remaining by-product and the protective layer in the chamber.
12. wafer processing according to claim 11, which is characterized in that use identical technique to different chips
Condition and process time carry out the preprocess method.
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| CN111524785A (en) * | 2020-06-03 | 2020-08-11 | 上海邦芯半导体设备有限公司 | Processing method of dry etching cavity |
| CN112289669A (en) * | 2019-07-25 | 2021-01-29 | 中微半导体设备(上海)股份有限公司 | Method for coating film in wafer-free vacuum reaction chamber and wafer processing method |
| CN112885709A (en) * | 2021-01-13 | 2021-06-01 | 中电化合物半导体有限公司 | Preparation method of silicon carbide epitaxial structure and semiconductor device |
| CN117238743A (en) * | 2023-11-10 | 2023-12-15 | 合肥晶合集成电路股份有限公司 | Method for improving annular defect of wafer edge |
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