WO2008155833A1 - キャッシュメモリ制御装置およびキャッシュメモリ制御方法 - Google Patents

キャッシュメモリ制御装置およびキャッシュメモリ制御方法 Download PDF

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Publication number
WO2008155833A1
WO2008155833A1 PCT/JP2007/062400 JP2007062400W WO2008155833A1 WO 2008155833 A1 WO2008155833 A1 WO 2008155833A1 JP 2007062400 W JP2007062400 W JP 2007062400W WO 2008155833 A1 WO2008155833 A1 WO 2008155833A1
Authority
WO
WIPO (PCT)
Prior art keywords
data transfer
request
transfer request
cache memory
perform
Prior art date
Application number
PCT/JP2007/062400
Other languages
English (en)
French (fr)
Inventor
Naohiro Kiyota
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/062400 priority Critical patent/WO2008155833A1/ja
Priority to EP07767239.2A priority patent/EP2169554B1/en
Priority to JP2009520187A priority patent/JP4710024B2/ja
Publication of WO2008155833A1 publication Critical patent/WO2008155833A1/ja
Priority to US12/654,312 priority patent/US8677070B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G06F12/127—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning using additional replacement algorithms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

　ＦＰ２２は，処理を行う要求を保持する複数のエントリを有し，各エントリごとにデータ転送要求を一度行ったことを示す要求済みフラグを備える。ＦＰ－ＴＯＱ２３には，一番古い要求を保持するエントリを示す情報が保持される。データ転送要求抑止判定回路２５は，処理を行う要求の要求済みフラグとＦＰ－ＴＯＱ２３とをチェックし，処理を行う要求の対象となるデータの転送要求がすでに発行され，かつ処理を行う要求が保持されたエントリがＦＰ－ＴＯＱ２３で示されたエントリでなければ，該当データの転送要求を抑止する信号をデータ転送要求制御回路２７に送る。データ転送要求制御回路２７は，一次キャッシュＲＡＭ２１でキャッシュミスが発生しても，転送要求を抑止する信号を受けた場合にはデータ転送要求を発行しない。これにより，キャッシュ上のデータの不要な置換を防ぐ。
PCT/JP2007/062400 2007-06-20 2007-06-20 キャッシュメモリ制御装置およびキャッシュメモリ制御方法 WO2008155833A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2007/062400 WO2008155833A1 (ja) 2007-06-20 2007-06-20 キャッシュメモリ制御装置およびキャッシュメモリ制御方法
EP07767239.2A EP2169554B1 (en) 2007-06-20 2007-06-20 Cache memory controller and cache memory control method
JP2009520187A JP4710024B2 (ja) 2007-06-20 2007-06-20 キャッシュメモリ制御装置およびキャッシュメモリ制御方法
US12/654,312 US8677070B2 (en) 2007-06-20 2009-12-16 Cache memory control apparatus and cache memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/062400 WO2008155833A1 (ja) 2007-06-20 2007-06-20 キャッシュメモリ制御装置およびキャッシュメモリ制御方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/654,312 Continuation US8677070B2 (en) 2007-06-20 2009-12-16 Cache memory control apparatus and cache memory control method

Publications (1)

Publication Number Publication Date
WO2008155833A1 true WO2008155833A1 (ja) 2008-12-24

Family

ID=40155999

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/062400 WO2008155833A1 (ja) 2007-06-20 2007-06-20 キャッシュメモリ制御装置およびキャッシュメモリ制御方法

Country Status (4)

Country Link
US (1) US8677070B2 (ja)
EP (1) EP2169554B1 (ja)
JP (1) JP4710024B2 (ja)
WO (1) WO2008155833A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011134205A (ja) * 2009-12-25 2011-07-07 Fujitsu Ltd 情報処理装置およびキャッシュメモリ制御装置
US11740962B2 (en) 2017-09-13 2023-08-29 Google Llc Quantum error correction

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07311711A (ja) * 1994-01-31 1995-11-28 Internatl Business Mach Corp <Ibm> データ処理装置とその動作方法及びメモリ・キャッシュ動作方法
JP2006048181A (ja) * 2004-07-30 2006-02-16 Fujitsu Ltd 記憶制御装置、ムーブインバッファ制御方法およびプログラム

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5784586A (en) * 1995-02-14 1998-07-21 Fujitsu Limited Addressing method for executing load instructions out of order with respect to store instructions
US6349382B1 (en) 1999-03-05 2002-02-19 International Business Machines Corporation System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program order
US6499090B1 (en) * 1999-12-28 2002-12-24 Intel Corporation Prioritized bus request scheduling mechanism for processing devices
US6484254B1 (en) * 1999-12-30 2002-11-19 Intel Corporation Method, apparatus, and system for maintaining processor ordering by checking load addresses of unretired load instructions against snooping store addresses
US6839808B2 (en) * 2001-07-06 2005-01-04 Juniper Networks, Inc. Processing cluster having multiple compute engines and shared tier one caches
US6732242B2 (en) * 2002-03-28 2004-05-04 Intel Corporation External bus transaction scheduling system
JP4180569B2 (ja) * 2003-01-27 2008-11-12 富士通株式会社 記憶制御装置、データキャッシュ制御装置、中央処理装置、記憶装置制御方法、データキャッシュ制御方法およびキャッシュ制御方法
US20050210204A1 (en) * 2003-01-27 2005-09-22 Fujitsu Limited Memory control device, data cache control device, central processing device, storage device control method, data cache control method, and cache control method
US8544008B2 (en) * 2004-12-10 2013-09-24 Nxp B.V. Data processing system and method for cache replacement using task scheduler

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07311711A (ja) * 1994-01-31 1995-11-28 Internatl Business Mach Corp <Ibm> データ処理装置とその動作方法及びメモリ・キャッシュ動作方法
JP2006048181A (ja) * 2004-07-30 2006-02-16 Fujitsu Ltd 記憶制御装置、ムーブインバッファ制御方法およびプログラム

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011134205A (ja) * 2009-12-25 2011-07-07 Fujitsu Ltd 情報処理装置およびキャッシュメモリ制御装置
US11740962B2 (en) 2017-09-13 2023-08-29 Google Llc Quantum error correction

Also Published As

Publication number Publication date
JPWO2008155833A1 (ja) 2010-08-26
JP4710024B2 (ja) 2011-06-29
EP2169554B1 (en) 2013-07-10
US8677070B2 (en) 2014-03-18
US20100106913A1 (en) 2010-04-29
EP2169554A4 (en) 2011-08-31
EP2169554A1 (en) 2010-03-31

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