WO2008155825A1 - 演算処理装置および演算処理方法 - Google Patents

演算処理装置および演算処理方法 Download PDF

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Publication number
WO2008155825A1
WO2008155825A1 PCT/JP2007/062338 JP2007062338W WO2008155825A1 WO 2008155825 A1 WO2008155825 A1 WO 2008155825A1 JP 2007062338 W JP2007062338 W JP 2007062338W WO 2008155825 A1 WO2008155825 A1 WO 2008155825A1
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WO
WIPO (PCT)
Prior art keywords
address
tsb
operation processing
storing
conversion
Prior art date
Application number
PCT/JP2007/062338
Other languages
English (en)
French (fr)
Inventor
Masaharu Maruyama
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/062338 priority Critical patent/WO2008155825A1/ja
Priority to EP07767196.4A priority patent/EP2159706B1/en
Priority to JP2009520179A priority patent/JP4608011B2/ja
Publication of WO2008155825A1 publication Critical patent/WO2008155825A1/ja
Priority to US12/624,531 priority patent/US8296518B2/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/681—Multi-level TLB, e.g. microTLB and main TLB

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

　仮想アドレスを物理アドレスに変換するアドレス変換対を記憶したＴＳＢ領域が格納された記憶手段にアクセスを行う演算処理装置であって、ＴＳＢ領域の一部を記憶するＴＬＢと、アドレス変換対を一時的に記憶するキャッシュメモリと、記憶手段に格納されたアドレス変換対の開始物理アドレスであるＴＳＢ基底物理アドレスを記憶するＴＳＢ基底物理アドレス記憶手段とを備え、ＴＳＢ基底物理アドレスと変換対象の仮想アドレスに基づいて、アドレス変換対をＴＳＢ領域から取得する際に用いられるＴＳＢポインタを算出し、変換対象の仮想アドレスに対応するアドレス変換対が、ＴＬＢ又はキャッシュメモリから検索されない場合には、算出されたＴＳＢポインタを用いて、変換対象の仮想アドレスに対応するアドレス変換対をＴＳＢ領域から取得して、キャッシュメモリに記憶させる。
PCT/JP2007/062338 2007-06-19 2007-06-19 演算処理装置および演算処理方法 WO2008155825A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2007/062338 WO2008155825A1 (ja) 2007-06-19 2007-06-19 演算処理装置および演算処理方法
EP07767196.4A EP2159706B1 (en) 2007-06-19 2007-06-19 Operation processing apparatus and operation processing method
JP2009520179A JP4608011B2 (ja) 2007-06-19 2007-06-19 演算処理装置および演算処理方法
US12/624,531 US8296518B2 (en) 2007-06-19 2009-11-24 Arithmetic processing apparatus and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/062338 WO2008155825A1 (ja) 2007-06-19 2007-06-19 演算処理装置および演算処理方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/624,531 Continuation US8296518B2 (en) 2007-06-19 2009-11-24 Arithmetic processing apparatus and method

Publications (1)

Publication Number Publication Date
WO2008155825A1 true WO2008155825A1 (ja) 2008-12-24

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ID=40155990

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PCT/JP2007/062338 WO2008155825A1 (ja) 2007-06-19 2007-06-19 演算処理装置および演算処理方法

Country Status (4)

Country Link
US (1) US8296518B2 (ja)
EP (1) EP2159706B1 (ja)
JP (1) JP4608011B2 (ja)
WO (1) WO2008155825A1 (ja)

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JP2019212167A (ja) * 2018-06-07 2019-12-12 富士通株式会社 演算処理装置、情報処理装置、及び演算処理装置の制御方法

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US10621092B2 (en) 2008-11-24 2020-04-14 Intel Corporation Merging level cache and data cache units having indicator bits related to speculative execution
US9672019B2 (en) 2008-11-24 2017-06-06 Intel Corporation Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads
US8775153B2 (en) * 2009-12-23 2014-07-08 Intel Corporation Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environment
JP2013073270A (ja) * 2011-09-26 2013-04-22 Fujitsu Ltd アドレス変換装置、演算処理装置及び演算処理装置の制御方法
WO2013048468A1 (en) 2011-09-30 2013-04-04 Intel Corporation Instruction and logic to perform dynamic binary translation
JP2013125355A (ja) * 2011-12-13 2013-06-24 Fujitsu Ltd 演算処理装置および演算処理装置の制御方法
KR101667772B1 (ko) * 2012-08-18 2016-10-19 퀄컴 테크놀로지스, 인크. 프리페칭을 갖는 변환 색인 버퍼
US9405551B2 (en) 2013-03-12 2016-08-02 Intel Corporation Creating an isolated execution environment in a co-designed processor
US9891936B2 (en) 2013-09-27 2018-02-13 Intel Corporation Method and apparatus for page-level monitoring
JP5974133B1 (ja) 2015-03-20 2016-08-23 株式会社東芝 メモリシステム
JP6740719B2 (ja) * 2016-06-03 2020-08-19 富士通株式会社 情報処理装置、情報処理方法、およびプログラム

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JPH01106149A (ja) * 1987-10-20 1989-04-24 Fujitsu Ltd 情報処理装置
JPH07200409A (ja) 1993-09-08 1995-08-04 Sun Microsyst Inc 仮想アドレスを物理アドレスに変換する方法及び装置
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US5222223A (en) * 1989-02-03 1993-06-22 Digital Equipment Corporation Method and apparatus for ordering and queueing multiple memory requests
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Publication number Priority date Publication date Assignee Title
JPS62151958A (ja) * 1985-12-25 1987-07-06 Matsushita Electric Ind Co Ltd 仮想アドレス変換装置
JPH01106149A (ja) * 1987-10-20 1989-04-24 Fujitsu Ltd 情報処理装置
US5465337A (en) 1992-08-13 1995-11-07 Sun Microsystems, Inc. Method and apparatus for a memory management unit supporting multiple page sizes
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US5956756A (en) 1993-09-08 1999-09-21 Sun Microsystems, Inc. Virtual address to physical address translation of pages with unknown and variable sizes
US6490658B1 (en) 1997-06-23 2002-12-03 Sun Microsystems, Inc. Data prefetch technique using prefetch cache, micro-TLB, and history file
EP1204029A2 (en) 2000-11-06 2002-05-08 Fujitsu Limited Microprocessor and address translation method for microprocessor
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See also references of EP2159706A4

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019212167A (ja) * 2018-06-07 2019-12-12 富士通株式会社 演算処理装置、情報処理装置、及び演算処理装置の制御方法
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JP7155629B2 (ja) 2018-06-07 2022-10-19 富士通株式会社 演算処理装置、情報処理装置、及び演算処理装置の制御方法

Also Published As

Publication number Publication date
EP2159706B1 (en) 2014-09-10
JPWO2008155825A1 (ja) 2010-08-26
US8296518B2 (en) 2012-10-23
JP4608011B2 (ja) 2011-01-05
US20100070708A1 (en) 2010-03-18
EP2159706A1 (en) 2010-03-03
EP2159706A4 (en) 2010-11-03

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