Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
  • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
  • G11C19/02—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
  • G11C19/08—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
  • G11C19/02—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
  • G11C19/08—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
  • G11C19/0808—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure using magnetic domain propagation
  • G11C19/0816—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure using magnetic domain propagation using a rotating or alternating coplanar magnetic field

Definitions

• the present invention relates to data storage, more especially but not exclusively to mass storage memory devices capable of storing GBytes of data, and of storing data at high densities.
• Hard drives with magnetic disks are the dominant technology for mass data storage and retrieval in personal computers (PCs). With current technology hard disk drives have storage capacities of up to around 100-200 GBytes, although smaller capacity miniature units are used in some devices, such as portable music players, video players and other portably multimedia devices which typically have drive capacities in the range 30-40 GBytes, or even smaller devices for digital cameras of sub- 10 GBytes.
• the basic structure of a hard drive can trace its heritage back to a 19th century gramophone, in that it is fundamentally a mechanical device based on a spinning disk with a pivotally mounted arm that can be positioned over the disk to read (and write) data stored on the disk in generally circular tracks.
• Optical storage devices such as CD and DVD read/write devices, adopt a similar construction at a basic level in that a spinning disk (whose storage mechanism may be based on a variety of physical mechanisms) is accessed optically using a head that emits a laser beam downwardly onto the disk.
• a spinning disk whose storage mechanism may be based on a variety of physical mechanisms
• Non-volatile serial memory based on semiconductor integrated circuits continues to develop strongly in terms of reduced cost and increased capacity.
• Serial memory that stores data serially, i.e. filewise, and is thus suitable for file storage, is to be contrasted with Random Access Memory (RAM) which stores data individually, i.e. bitwise, and is thus suitable to high speed access of small data segments, such as for processing operations.
• Serial semiconductor memory is typically some form of EEPROM (Electrically Erasable Programmable Read-Only Memory). Flash memory is the non-volatile semiconductor memory of choice, being used widely in devices such as USB memory sticks, CF/SD memory cards for digital cameras, mobile phones and MP3 players. However, with current technology semiconductor memory is still too costly to displace hard drives.
• flash memory has a life cycle of up to approximately 1000 write operations before degradation of reliability and performance occurs. Also, the write latency for flash memory is high due to the need to charge a large capacitance for the data storage. Additionally, flash memory has a storage density limit of approximately 40Mbit/mm 2 (approximately 25Gbit/in ).
• flash memory has important limitations in the density of information that they can store by today's state-of-the-art lithography.
• lithography defines the basic storage cell; a typical cell is roughly 1OF 2 in area, where F is the minimum feature size that can be produced by the generation of lithography in use (90 nm today, soon 65 nm).
• lithography is used to define the gap in the write head which defines how well focused the writing magnetic field is, and hence the smallest bit size that can be written. Storage densities of both of these technologies will thus be unable to make order of magnitude leaps without a sudden (and unexpected) change in lithography performance.
• a step-increase in data storage densities is highly desirable for several reasons.
• Magneto-electric devices have the potential to fulfil this requirement, since they are (i) non-volatile and (ii) can be acted upon by magnetic fields, which can be created and sensed at a distance.
• Magneto-electric devices for data storage that have been proposed can broadly be classified into two classes: single domain devices and domain wall devices.
• Single domain devices such as magnetic RAM cells, attempt to keep all of the spins within a device element tightly locked together.
• Domain wall devices use manipulation of the location of the domain wall itself to signify different data states.
• 3D magnetic memory device has been developed by Parkin and Chen at International Business Machines Corporation (IBM) [1-6].
• This magnetic memory device is based on ferromagnetic nanowires which are referred to by this group as data tracks or race tracks. Specifically, it uses domain walls in the nanowires to encode data serially in a plurality of alternately directed single domains along the nanowires.
• the device uses spin-based electronics to write and read data.
• An electric current is applied to the nanowires to move the magnetic domains along the track in the direction of the electric current, past reading or writing elements.
• the electric current passed across the domain wall acts to move the domain walls in the direction of the current flow. As the current passes through a domain, it becomes "spin polarised".
• any inhomogeneity along the nanowires may affect the propagation speed of the domain walls leading to differential motion between adjacent domain walls.
• To achieve the necessary control of the propagation speed in such devices will become increasingly challenging from a fabrication point of view as such devices is scaled up from a prototype stage to a production device. Consequently, in our view at least, it is by no means certain that this type of device can successfully be developed into a commercial product.
• nanostructures can be made in which the (threshold) domain wall nucleation field is significantly higher than the (threshold) domain wall propagation field.
• nanowires can be fabricated with a nucleation field of about 200 Oersted (Oe) and a propagation field of only about 3 Oe. This means that that domain walls can be propagated within the nanostructures using appropriate drive fields having a magnitude between the propagation field and the nucleation field without causing additional domain walls to be nucleated.
• new domain walls can be selectively nucleated in a controlled manner in localised parts of the nanostructure by applying a local field having a magnitude greater than the nucleation field. Consequently, nanostructures have been demonstrated in which domain walls are nucleated (i.e. created), moved and annihilated in a controlled, stable and reproducible manner.
• the presence (or absence) of domain walls can be sensed at localised parts of the nanostructure using a suitable sensor, such as a magneto-optical Kerr effect (MOKE) device [11] or an anisotropic magneto resistance (AMR) device [12].
• MOKE magneto-optical Kerr effect
• AMR anisotropic magneto resistance
• traps can be provided by nanowire corners [9, 10] and inward or outward notches in the nanowires [9], wherein inward and outward notches are domain wall pinning site created by a local narrowing and widening of a nanowire respectively.
• traps provide a localised increase in the threshold propagation field.
• a domain wall By applying a field greater than the propagation field for the nanowire and less than the local propagation field for the trap, a domain wall can be moved along the wire and into the trap where it will remain pinned. The domain wall can then be depinned and moved along the wire again by increasing the field beyond the local propagation field for the trap.
• a further example of domain wall traps in nanowires is known from Hara and co-workers [15].
• a magnetic NiFe-alloy nanowire is abutted on either side by a pair of ferromagnetic wires of the same width as the nanowire, these being referred to as "gate" wires in the article.
• the gate wires are constricted to one third of their width at the junction with the nanowire so that the domain in each gate wire stays pinned at the nanowire junction.
• Hara et al also note that the domain walls in their nanowires are of the vortex type, i.e. not transverse, owing to the dimensions of the nanowires used (see reference [14] for an explanation of vortex and transverse domain wall types).
• FIGS. IA to ID of the accompanying drawings illustrate such a junction, more specifically four possible states of such a junction, these being provided by the four permutations of up and down domain alignment in the first and second gate wires.
• a nanowire 10 of width w which at an intermediate position along its extent has first and second gate wires 20 and 21, also of width w, abutting its sides which serve to pin a domain wall 16 of the nanowire 10 which separates magnetic domains 114 that are illustrated with arrows indicating the magnetic moment in the conventional way.
• the gate wires 20 and 21 each have constrictions at their junction with the nanowire 10.
• FIG. 1 The magnetostatic charge accumulations associated with the different domain walls are illustrated by the encircled plus and minus symbols for positive and negative charge.
• Figures IB to ID are similar illustrations, each with different permutations of alignments of the domains in the two gate wires.
• the domains in the nanowire 10 are the same in all cases showing a head-to-head domain wall pinned at the junction of the gate wires.
• Figures IA to ID illustrate the cases labelled A to D respectively by Hara et al.
• the drawings also show the example of a head-to-head domain wall at the cross, which is what was modelled by Hara et al. (The other alternative would be a tail-to- tail domain wall.)
• Hara et al showed that the trapping or pinning field of domains in the nanowire at the gate depended strongly on whether the domains in the two gate wire sections either side of the nanowire were parallel to each other (cases A and C) or anti-parallel (cases B and D).
• the experimental observation is logical given the fact that the respective magnetostatic charge accumulations associated with the two gate wire domains terminating at either side of the nanowire will be of the same charge for the anti-parallel cases B and D and different charge for the parallel cases A and C.
• the anti-parallel cases will thus provide a junction that displays a greater repulsion from or attraction to a domain wall in the nanowire than the parallel cases where the magnetostatic charge accumulations effectively cancel out.
• nanowires with notch pinning sites along their length can be used as non-volatile serial memory devices operable at room temperature in which data is encoded in the magnetic domains.
• Data is read into the nanowire serially, by nucleating domains at one end of the nanowire and then moving the domains along the nanowire under the action of an operating field and synchronised electrode drive signal.
• the magnetic domains defined are used to encode data.
• Data is read out of the opposite end of the nanowire by a suitable magnetic sensor, such as a tunnel junction, spin valve or a Hall effect sensor.
• FIG. 2 of the accompanying drawings schematically shows such a nanowire 10 comprising notches 12 and supporting magnetic domains 14 separated by head-to- head and tail-to-tail domain walls 16 and 18 respectively [16].
• An operating field H that alternates between being aligned and anti-aligned with the direction of extent of the nanowire (+y and -y in the figure) is driven in synchrony with a drive current that is passed through selected ones of the electrodes 12 that extend orthogonal to the nanowire (z direction in the figure) to alternately heat notches 12 hosting head-to- head and tail-to-tail domain walls in synchrony with the alignment and anti-alignment of the operating field.
• the heating is provided by Joule heating from the electrodes that are arranged adjacent to the notches.
• the effect of the heating is to temporarily lower the locally enhanced propagation field at the heated notch to below the operating field.
• the separate actuation of head-to-head and tail-to-tail domain walls is achieved by using three groups of heating electrodes, labelled A, B and C, attached in repeated series to directly adjacent notches. Between clocking cycles, this arrangement means that all the head-to-head domain walls are hosted by notches addressed by one of the electrode groups, all the tail-to-tail domain walls are hosted by notches addressed by another one of the electrode groups, and the notches addressed by the remaining electrode group are "empty", i.e. do not host any domain walls.
• the magnetic domains can thus be moved along the nanowire by alternate movement of the head-to-head and tail-to-tail domain walls.
• a feature of our previously proposed serial memory device is that the heating electrodes need to be arranged close to the nanowire notches, so fabrication of the electrodes becomes an important part of the manufacturing process.
• one encoding scheme is that a 1 is coded by a head-to-head domain wall followed by a tail-to-tail domain wall spread across 3 notches, while a 0 is coded by the absence of any domain walls across the same length.
• the data density per unit length of nanowire (in terms of numbers of notches) is thus limited by the encoding scheme.
• the aim of the invention is to provide a non-volatile serial memory device based on manipulation of magnetic domains in nanowires with a simplified addressing scheme to that previously proposed in our unpublished work and a higher data density [16].
• a method of manipulating a domain wall in a first nanowire crossed by a second nanowire to form a junction comprising: attracting a domain wall into the junction by aligning a magnetic domain in the second nanowire where it crosses the first nanowire with the domain wall in the first nanowire so that the domain wall becomes pinned at the junction; and repelling the domain wall from the junction by reversing the alignment of the magnetic domain in the second nanowire so that it becomes anti-aligned with the domain wall in the first nanowire and ejects it from the junction.
• a magnetic memory device for serially storing data encoded in magnetic domains pinned at a succession of pinning sites spaced apart along a nanowire, wherein each pinning site is formed by a junction between the nanowire and another nanowire crossing it.
• a magnetic memory device in which data is encoded in the chirality of the domain walls that separate magnetic domains in a nanowire.
• a magnetic memory device comprising: a plurality of data-carrying nanowires made of magnetic material and extending in a first direction crossed by a plurality of data-clocking nanowires also made of magnetic material and extending in a second direction, collectively forming a network of cross junctions; a data read-in part arranged adjacent to respective data read-in portions of the data-carrying nanowires and operable to nucleate magnetic domains with domain walls of pre-determined chirality in the data-carrying nanowires, wherein the chirality of the domain walls encodes the data to be stored; a magnetic field source operable to generate a clocking field that alternates between alignment and anti-alignment with the data-clocking nanowires, which serves to move the data-carrying domain walls along the data-carrying nanowires from one cross junction to the next by successively releasing the data- carrying domain walls from the cross junctions where they are pinned and causing them to move to said
• data can be clocked through the device with a global externally applied field, i.e. the clocking field.
• a global externally applied field i.e. the clocking field.
• No addressing of individual pinning sites, i.e. nanowire crosses, or groups of pinning sites is needed.
• the novel clocking mechanism provided by the combination of nanowire crosses and clocking field is not sensitive to the charge state of the domain wall, i.e. whether the domain wall is a head-to-head domain wall or a tail-to-tail domain wall.
• the same field can thus be applied to all pinning sites to move the data incrementally through the nanowire pinning sites.
• the structure is readily scalable in three dimensions in that multiple layers of nanowire networks can be arranged on top of each other, thus providing a very high storage density.
• This scalability in the vertical dimension is simplified by the fact that data can be clocked through the device with a global externally applied field.
• the novel approach of encoding the data in the chirality of the domain walls allows for relatively dense data storage in comparison with previously proposed magnetic nanowire serial memories which use properties of the domains themselves, such as domain length, to encode the data.
• a further magnetic field source may be provided which is operable to generate an operating field aligned with the data-carrying nanowires, which serves to assist movement of the data-carrying domain walls along the data-carrying nanowires between cross junctions.
• the data read-in part preferably comprises a plurality of nucleation field generators, one for each data-carrying nanowire, each arranged to selectively create the magnetic domains of pre-defined chirality by locally applying a field of at least the nucleation field in the data-carrying nanowire at the read-in portion.
• the data read-out part preferably comprises a plurality of magnetic field detectors, one for each data-carrying nanowire, each arranged to sense the chirality of the domain walls in the data-carrying nanowire at the data read-out portion.
• the data-carrying nanowires are dimensioned so that domain walls that form therein are transverse domain walls, the chirality of the domain walls that encode the data thus being up or down.
• the data-clocking nanowires are dimensioned so that domain walls that form therein are transverse domain walls. It may also be possible to make a functioning device in which the data- clocking nanowires are dimensioned so that domain walls that form therein are vortex domain walls. However, this option has not been experimentally tested, and vortex domain walls may or may not provide the necessary attractive and repulsive properties for domain walls pinned at the cross junctions.
• the device preferably further comprises a clocking domain generation part arranged adjacent to respective clocking portions of the data-clocking nanowires and operable to nucleate magnetic domains in the data-clocking nanowires.
• the clocking domain generation part can be made so it is operable to nucleate domain walls of pre-determined chirality.
• the clocking domain generation part may comprise a plurality of further nucleation field generators, one for each data-clocking nanowire, each arranged to selectively create the magnetic domains by locally applying a field of at least the nucleation field in the data-clocking nanowire at the clocking portion.
• the device will typically be fabricated on a substrate and the network of cross junctions will be arranged on the substrate as a magnetic layer formed of magnetic material for the nanowires interspersed with islands of non-magnetic material to separate them.
• the nanowire structure may be fabricated as a layer in a conventional lithography process.
• the device may be fabricated as a multi-layer, three-dimensional memory. Namely, multiple magnetic layers can be arranged on top of one another, each separated by a non-magnetic layer.
• the device will thus have a plurality of crossed nanowire planes extending in the vertical direction.
• the pairs of magnetic and non-magnetic layers may terminate in a stepwise manner on one side of the data-carrying nanowires to form terraces extending in the direction of the data-clocking nanowires.
• the magnetic layer that terminates to form each terrace may in each case either be the lowermost nanowire layer or the uppermost nanowire layer.
• the magnetic layer that terminates to form each terrace is preferably the lowermost nanowire layer on one side and the uppermost nanowire layer on the other side, since this structure lends itself to fabrication using a stepped shadow mask process.
• a method of serially storing data encoded in magnetic domains in a nanowire each magnetic domain being bounded by a domain wall, and the nanowire having a plurality of crossing nanowires along its length forming a plurality of cross junctions along the nanowire
• the method comprising: reading a stream of bits of data into the nanowire by nucleating respective magnetic domains with domain walls of pre-determined chirality at an input portion of the nanowire, wherein the chirality of the domain walls encodes the bits; supplying a clocking field that alternates between alignment and anti-alignment with the crossing nanowires to move the domain walls, and thus the bit stream, along the nanowire from one cross junction to the next by successively releasing the domain walls from the cross junctions where they are pinned and causing them to move to said next cross junction where they are pinned again; and reading the bit stream out of the nanowire by sensing the chirality of the domain walls at an output portion of the nanowire.
• Domain wall an interface between magnetic domains of oppositely aligned magnetisation.
• Transverse domain wall a domain wall in which the magnetisation is predominantly aligned in a single direction in the plane of the domain wall.
• the magnetisation alignment will be in one of two states aligned or anti-aligned with the long dimension of the cross-section [13]. These two states are referred to as states of 'up' and 'down' chirality, or 'left' and 'right' chirality, with reference to the principal magnetisation direction.
• Transverse domain walls will tend to form in smaller cross-section nanowires [13].
• Vortex domain wall a domain wall in which the magnetisation forms a vortex or spiral pattern at the domain wall. Vortex domain walls will have a clockwise or counter-clockwise orientation of their magnetization patterns in plan view, these two states being referred to as clockwise or counter-clockwise chirality [13]. Vortex domain walls will tend to form in larger cross-section nanowires [13].
• Head-to-head domain wall a domain wall between "north" ends or heads of adjacent magnetic domains generally associated with a positive magnetostatic charge accumulation.
• Tail-to-tail domain wall a domain wall between "south” ends or tails of adjacent magnetic domains generally associated with a negative magnetostatic charge accumulation.
• Nanowire a domain wall conduit made of magnetic material having sufficient shape anisotropy that magnetisation aligns with the longitudinal axis of the nanowire. Typically made of soft magnetic material such as Permalloy (NigoFe 2 o).
• Domain nucleation field a threshold field, being the minimum field that need be applied to reverse magnetisation in a nanowire if no reverse domain already exists in the wire.
• Domain propagation field a threshold field, being the minimum field that need be applied to move a domain wall along a nanowire.
• Domain wall pinning site a location along a nanowire at which the nanowire has a locally enhanced propagation field caused by a pre-fabricated (Le. not naturally occurring) modulation of the energy of a domain wall present at that location.
• Depinning field the locally enhanced domain propagation field needed to render domain walls mobile across (and out of) pinning sites.
• Operating field a field having a strength between the propagation field and the depinning field.
• Depinning energy the energy that needs to be applied to a pinning site to temporarily lower the locally enhanced propagation field to below the operating field.
• Figures IA to ID are schematic plan view representations of nanowire structures according to the prior art
• Figure 2 is a schematic plan view representation of a nanowire according to a previously proposed device
• Figure 3A is a schematic plan view representation of a nanowire structure embodying to the invention to illustrate a first basic state exploited by devices according to the invention
• Figure 3B is a schematic plan view representation of a nanowire structure embodying to the invention to illustrate a second basic state exploited by devices according to the invention
• Figure 4A to 4H show a sequence of configurations of the cross structure in the case of a head-to-head domain wall with a 'down' chirality.
• Figure 5A to 5H show a sequence of configurations of the cross structure in the case of a head-to-head domain wall with an 'up' chirality.
• Figure 6A to 6H show a sequence of configurations of the cross structure in the case of a tail-to-tail domain wall with an 'down' chirality.
• Figure 7A to 7H show a sequence of configurations of the cross structure in the case of a tail-to-tail domain wall with an 'up' chirality.
• Figures 8A to 8C show a sequence of three successive timing intervals for a data nanowire crossed by multiple clocking nanowires.
• Figure 9 is a schematic plan view system-level representation of a single layer device embodying the invention.
• Figure 10 is a schematic side section view of a magnetic field source for a memory device embodying the invention in the yz plane;
• Figure 1 IA is a schematic plan view representation of a nanowire structure embodying the invention showing a data read-in part for nucleating domain walls of defined chirality.
• Figure 1 IB is a schematic plan view representation of a nanowire structure embodying the invention showing an alternative data read-in part.
• Figure 12 is a schematic plan view representation of a nanowire structure embodying the invention showing a data read-out part for sensing the chirality of transverse domain walls.
• Figure 13 is schematic side section view in the xz plane of an input side of a multi-layer memory device according to a further embodiment of the invention.
• Figure 14 is schematic side section view in the xz plane of an output side of the multi-layer memory device of Figure 13;
• Figures 15A and 15B are schematic side section views in the xz plane showing fabrication of an input side of the multi-layer memory device;
• Figures 16A and 16B are schematic side section views in the xz plane showing fabrication of an output side of the multi-layer memory device
• Figure 17A is a schematic plan view in the xy plane of a shadow mask and wafer used in the fabrication process of the multi-layer memory device;
• Figure 17B is schematic side view in the xz plane of the same features as shown in Figure 17A;
• Figure 18 shows simulation results of a head-to-head domain wall with an 'up' chirality initially in the left arm of a data nanowire being captured at a junction by a transverse domain wall of 'left' chirality passing down the clocking nanowire;
• Figure 19 shows simulation results of a head-to-head domain wall with an 'up' chirality initially captured at the junction and then being ejected from the cross by a transverse domain wall of 'right' chirality passing down the clocking nanowire.
• Figure 3A is a schematic plan view representation of a magnetic nanowire structure embodying to the invention.
• the following convention is adopted throughout for the axes.
• the z axis is the vertical axis, the x and y axes are horizontal.
• the basic structure is a cross formed by a first nanowire 100 extending in the x direction and a second nanowire 110 extending in the y direction which cross each other at a junction 115.
• the magnetic domains 114 hosted in the nanowires 100 and 110 are illustrated with arrows indicating the magnetic moment in the conventional way.
• Each domain is bounded by a domain wall 112.
• the nanowire domain walls fall into two types, head-to-head domain walls, such as the illustrated domain wall 112 and tail-to-tail domain walls, the meaning of which will be self-explanatory.
• Head-to-head domain walls carry positive magnetostatic charge
• tail-to-tail domain walls carry negative magnetostatic charge.
• the positive and negative charges associated with the domain walls are also schematically illustrated.
• the nanowires 100 and 110 constitute domain wall conduits made of magnetic material having sufficient shape anisotropy that the magnetic moment of the domains aligns with the principal axis of the nanowire. It will be appreciated that the magnetic alignment in the region of the domain walls is more complex as will be understood from the prior art [13, 14] and described in more detail further below.
• the first and second nanowires 100 and 110 are co-planar.
• the first and second nanowires can be of the same widths and same thicknesses, or they may differ.
• the illustrated portion of the first nanowire 100 has a domain wall 112, illustrated as a head-to-head domain wall, located on the left hand side of the cross structure to the left of the junction 115.
• the -x aligned domain to the right of the domain wall 112 extends through the region of the junction 115.
• the domain wall 112 is a transverse domain wall and has a +y chirality as indicated by the small arrow located at the domain wall 112, which is referred to as an 'up' chirality throughout the following.
• the second nanowire 110 has a single domain aligned in the +y direction extending through the junction 115. It can thus be seen that the domain in the second nanowire is aligned with the domain wall in the first nanowire. With this aligned configuration it is energetically favoured for the domain wall to move from the arm of the nanowire to the junction, where it will become pinned.
• the junction is a pinning site that forms a potential well for a domain wall in the aligned configuration. Experiments by the inventors have shown that this potential well is of moderate strength, somewhat smaller than the nucleation field, but larger than the operating field.
• Figure 3B is a schematic plan view representation of the same nanowire structure as Figure 3A, but shows a different configuration of the various domains.
• the only difference between Figure 3A and 3B is in the chirality of the transverse domain wall.
• the domain wall 112 is a transverse domain wall with -y chirality, which is referred to as a 'down' chirality throughout the following.
• the domain in the second nanowire is anti-aligned with the domain wall in the first nanowire. With this anti-aligned configuration, experiments by the inventors have shown that the junction forms a potential barrier of relatively high strength, larger than the nucleation field. It is thus energetically favoured for a domain wall in this configuration to remain offset from the junction in the position schematically illustrated.
• the alignment or anti-alignment between the domain in the second nanowire and the domain wall in the first nanowire determines whether the cross junction constitutes an (attractive) potential well or a (repulsive) barrier to domain walls in the first nanowire.
• Figure 4A to 4H show a sequence of configurations of the cross structure in the case of a head-to-head domain wall with a 'down' chirality.
• Figure 4A illustrates the same configuration as Figure 3B in which the first nanowire has a head-to-head domain wall with a 'down' chirality to the left of the junction which is anti-aligned with a domain in the second nanowire with a field pointing in the +y direction.
• Figure 4B shows a domain wall in the second nanowire that is moving in the
• Figure 4C shows the situation after this domain wall has passed through the junction, now being located above the junction.
• the domain in the second nanowire in the region of the junction is now reversed in polarity and has a field pointing in the -y direction, which is now aligned with the field associated with the transverse domain wall in the first nanowire.
• this means that the junction is now a potential well for the domain wall in the first nanowire, which thus moves to the junction where it is pinned, as illustrated.
• Figure 4D illustrates this situation with the head-to-head domain wall with a down chirality pinned in the junction.
• the mobile domain wall in the second nanowire has passed further upwards out of view.
• Figures 4A to 4D collectively show how reversal of the domain in the second nanowire from up to down can attract and pin, or 'suck', a head-to-head domain wall of down chirality into the junction.
• the time sequence now continues further in Figures 4E to 4H.
• Figure 4E shows appearance of the next upwardly travelling further domain wall in the second nanowire as it approaches the junction, wherein the junction has the head-to-head domain wall of down chirality pinned at it.
• Figure 4F shows the instance where the two domain walls coincide. At this point there is a complex interaction that is schematically illustrated by a single net field arrow pointing in the south-east direction, i.e. down and to the right.
• Figure 4G shows the situation after this domain wall has passed through the junction, now being located above the junction.
• the domain in the second nanowire in the region of the junction is now reversed in polarity and has a field pointing in the +y direction, which is now anti-aligned with the field associated with the transverse domain wall in the first nanowire.
• the upwardly pointing domain field in the second nanowire thus now forms a repelling potential barrier at the junction for the first nanowire's head-to-head domain wall, resulting in depinning of that domain wall and its ejection from the junction.
• Figure 4H shows the final step in the sequence in which the mobile domain wall in the second nanowire has passed further upwards out of view and the first nanowire's head-to-head domain wall has moved further to the right to an offset position from the junction.
• Figures 4E to 4H collectively show how reversal of the domain in the second nanowire from down to up can repel and eject, or 'spit out 1 , a head-to-head domain wall of down chirality from the junction.
• the domain wall in the second nanowire is a transverse domain wall. In the illustrated example, it is aligned in the +x direction, which is referred to as 'right' chirality. The opposite alignment would be a 'left' chirality pointing in the -x direction.
• a +x, right chirality domain wall will tend to cause ejection of a pinned domain wall from the junction in the +x direction (the illustrated example). This is believed to follow from the fact that when the two domain walls coincide at the junction, the field of the pinned domain wall will tend to rotate towards the alignment of the domain wall arriving from the second nanowire, causing the domain wall boundary effectively to be displaced in the direction in which the field of the domain wall of the second nanowire is pointing.
• a +x, right chirality domain wall will thus displace the head-to-head down chirality domain wall in the +x direction.
• the second nanowires may be made larger in cross- section, e.g. wider, than the first nanowires so that they preferentially form vortex domain walls and not transverse domain walls. It may be the case that the sensitivity of the transverse domain wall in the first nanowire to chirality of the domain wall in the second nanowire during ejection does not occur when the second nanowire hosts vortex domain walls.
• Figure 5A to 5H show a sequence of configurations of the cross structure in the case of a head-to-head domain wall with an 'up' chirality.
• Figure 5A illustrates a configuration in which the first nanowire has a head-to- head domain wall with 'up' chirality to the left of the junction which is anti-aligned with a domain in the second nanowire with a field pointing in the -y direction.
• Figure 5B shows a domain wall in the second nanowire that is moving in the +y direction and approaching the junction.
• Figure 5C shows the situation after this domain wall has passed through the junction, now being located above the junction.
• the domain in the second nanowire in the region of the junction is now reversed in polarity and has a field pointing in the +y direction, which is now aligned with the field associated with the transverse domain wall in the first nanowire.
• this means that the junction is now a potential well for the domain wall in the first nanowire, which thus moves to the junction where it is pinned, as illustrated.
• Figure 5D illustrates this situation with the head-to-head domain wall with up chirality pinned in the junction.
• the mobile domain wall in the second nanowire has passed further upwards out of view.
• Figures 5 A to 5D collectively show how reversal of the domain in the second nanowire from down to up can attract and pin, or 'suck', a head-to-head domain wall of up chirality into the junction.
• Figure 5E shows appearance of the next upwardly travelling further domain wall in the second nanowire as it approaches the junction, wherein the junction has the head-to-head domain wall of up chirality pinned at it.
• Figure 5F shows the instance where the two domain walls coincide. At this point there is a complex interaction that is schematically illustrated by a single net field arrow pointing in the north-east direction, i.e. up and to the right. The field of the pinned domain wall has thus rotated towards the alignment of the right chirality transverse domain wall arriving from the second nanowire.
• Figure 5G shows the situation after this domain wall has passed through the junction, now being located above the junction.
• the domain in the second nanowire in the region of the junction is now reversed in polarity and has a field pointing in the -y direction, which is now anti-aligned with the field associated with the transverse domain wall in the first nanowire.
• the downwardly pointing domain field in the second nanowire thus now forms a repelling potential barrier at the junction for the first nanowire's head-to-head domain wall, resulting in depinning of that domain wall and its ejection from the junction.
• Figure 5 H shows the final step in the sequence in which the mobile domain wall in the second nanowire has passed further upwards out of view and the first nanowire's head-to-head domain wall has moved further to the right to an offset position from the junction.
• Figures 5E to 5H collectively show how reversal of the domain in the second nanowire from up to down can repel and eject, or 'spit out', a head-to-head domain wall of up chirality from the junction.
• Figure 6A to 6H show a sequence of configurations of the cross structure in the case of a tail-to-tail domain wall with an 'down' chirality.
• the magnetic domains can encode a bit of data through the chirality of the transverse domain wall, since the suck-and-spit action is insensitive to chirality of the transverse domain wall in the first nanowire.
• the first nanowires we refer to the first nanowires as data nanowires and the second nanowires as clocking nanowires.
• the domain walls in the first nanowires as data-carrying domain walls, and the domain walls in the second nanowires as clocking domain walls, since they serve to clock the data-carrying domain walls through the junctions. Clocking of data through a data nanowire is now described with reference to the following figures.
• Figures 8A to 8C show a sequence of three successive timing intervals for a data nanowire crossed by multiple clocking nanowires.
• the only fields indicated are the domain field in the clocking nanowires and the chirality field in the data-carrying domain walls in the data nanowire.
• the domain fields in the clocking nanowires are all aligned in the same way at any given time. More specifically, at the first time shown in Figure 8A the domain fields in the clocking nanowires are up, then they are reversed to down in Figure 8B and again reversed to up in Figure 8C.
• FIG. 8A six data-carrying domain walls are shown and carry the bit sequence 010011, this sequence being arbitrarily selected by way of example only.
• the data-carrying domain walls are located at every second junction.
• the aligned configuration, attractive junctions, which are the l's in Figure 8 A, have the data-carrying domain walls located at the junction, whereas the anti-aligned configuration, repelling junctions, which are the O's in Figure 8A, have the data- carrying domain walls offset from the junction.
• O's as well as l's are associated with one of the junctions, as illustrated by the locations of the O's and l's in the figure.
• domain walls swept through the clocking nanowires should alternate appropriately between +x and -x chirality to ensure that they can propagate through the junction in the desired manner.
• Figure 9 is a schematic plan view system-level representation of a memory device embodying the invention.
• the main central area of the device is formed of a two-dimensional array of I data-carrying nanowires 100 extending parallel to each other in the x direction, labelled as rows R 1 , R 2 , R 3 ... Ri .... Ri, and J clocking nanowires 110 extending parallel to each other in the y direction, labelled as columns Ci, C 2 , C 3 ... C j .... Cj, which together form a junction grid extending over an area 125 indicated by the dashed line box.
• the nanowires 100 and 110 are co-planar and cross at junctions 115, labelled nodes N y to indicate the row and column number of the crossing nanowires.
• the nanowire grid is fabricated together as a single deposited layer, wherein the magnetic material for the nanowires is separated by islands of non- magnetic material 123, such as SiO 2 for example.
• Standard lithographic techniques can be used to etch a grid in a, for example, SiO 2 layer followed by deposition of the, for example, Py, and lift off of the excess Py that covers the SiO 2 islands to complete the illustrated structure.
• Each data-carrying nanowire Rj has a data source or read-in element 126/DSj and a data receiver or read-out element 128/DR; positioned respectively to the left and right sides of the junction grid 125 on data input and output sides of the device respectively.
• the read-in elements DS are operable to nucleate a domain in the row R; bounded by a transverse domain wall of a predetermined chirality that encodes the data bit being read in.
• the data read-in elements DSi collectively form a data read-in part 127 of the device.
• the data read-out elements DR are operable to sense the chirality of a transverse domain wall once it is ejected from the Jth junction, i.e. the last junction in the grid 125.
• the data read-out elements DRj collectively form a data read-out part 129 of the device.
• Each clocking nanowire C j has a clocking source CSj arranged adjacent the grid 125.
• Each clocking source C j is operable to nucleate a domain in the column C j bounded by a transverse domain wall of a pre-determined chirality selected to ensure that head-to-head and tail-to-tail domain walls that appear alternately at the nodes Ny of a given row are clocked with right and left chirality transverse domain walls respectively.
• the clocking sources CS j collectively form a clocking domain generation part 131 of the device. It will be understood that the nanowire array and associated circuit elements will be fabricated on a substrate using lithographic processes.
• a clocking field H y which is pulsed with a square wave modulation to alternate between +y and -y alignment at a constant magnitude which is above the operation field for the clocking nanowires, but below the nucleation field thereof.
• a drive field H x may also be provided, as shown, which is for applying a force in the +x direction to data-carrying domain walls to ensure that they propagate exclusively in the intended left-to-right direction through the device.
• the drive field will have a strength greater than the operation field for the data-carrying nanowires and less then the depinning field for aligned crosses, i.e. crosses that form potential wells, as described above with reference to Figure 3A.
• the drive field may be constant or if desired pulsed in synchronisation with the clocking field.
• a drive field may not be required if the data-carrying domain walls propagate naturally through the structure. If a drive field is provided, this may obviate the need to control the chirality of the domain walls in the clocking nanowires, as mentioned previously.
• Figure 10 is a schematic side section view in the yz plane of a magnetic field source 130 for providing the clocking field.
• the substrate 124 which bears the previously described nanowire array and associated read-in, read-out and clocking elements is also shown.
• the source 130 provides a linear magnetic field B in the +y direction as determined by the current flow direction through the source.
• the source is of the well known strip line design with an array of elements 132 extending in the z- direction.
• the source 130 may be integrated with the substrate 124 through flip chip bonding or other techniques. If a drive field is also needed by the device, a second strip line source of this kind can be provided, which will be orthogonally aligned, i.e. an equivalent figure to Figure 10 would be in the xz plane to provide a linear magnetic field in the +x direction.
• Figure 1 IA is a schematic plan view representation of a nanowire structure embodying the invention showing a data read-in part DSj for nucleating domain walls of defined chirality.
• the data read-in part DSi has the nanowire 100/R; extending through it and comprises first and second current wires 102 and 104 having portions that cross over the nanowire at opposite slanting angles.
• the wires 102 and 104 are also isolated from each other by a suitable insulating layer (not shown). They may be both above or both below the nanowire, or one below and one above.
• a magnetic field B at right angles to the wire is induced as illustrated. If this field results in a field greater than the nucleation field being applied to the nanowire, a domain is formed in the nanowire, with a domain wall aligned with the B field component, i.e. in the +x direction (up chirality) in the illustrated example. This is because the slanted portion of wire 102 results in the induced B field having a component in the +y direction. Similarly the opposite slant of the portion of wire 104 will result in a domain wall of the other chirality being induced, i.e. in the -x direction (down chirality).
• Figure 1 IB is a schematic plan view representation of a nanowire structure embodying the invention showing an alternative data read-in part DS; for nucleating domain walls of defined chirality.
• the data read-in part DS has the nanowire 100/R; extending through it and comprises a single current wire 103 having a portion that crosses over the nanowire at right angles thereto, i.e. in the y direction.
• a magnetic field B x at right angles to the wire is induced as illustrated. If this field is greater than the nucleation field of the nanowire, a domain is formed in the nanowire.
• the domain wall thereby created is equally likely to be of up or down chirality.
• the chirality of the domain wall be selected by the direction of that field component.
• the clocking field generated by the above-described magnetic field source 130 may also be used for this purpose, since it is in the y direction and can be alternated between +y and -y alignment.
• a further, independently actuatable magnetic field source may be provided for setting the chirality of the domain walls nucleated by the wire 103.
• Figure 12 is a schematic plan view representation of a nanowire structure embodying the invention showing a data read-out part 128/DR; for sensing the chirality of transverse domain walls.
• a nanowire 100 arranged on the substrate 124 has, in the region of its termination to the right side of the device, a magnetic field detector 128 embedded in the substrate 124.
• the magnetic detectors are integrated in the silicon (or other semiconductor) of the substrate.
• substrate is used loosely as an umbrella term for the underlying semiconductor structure including conventional epitaxial layers, doping regions and so forth, rather than in a strict sense to refer to a bare unprocessed wafer portion.
• the magnetic detectors 28i of the rows Rj serve to detect the presence either of a domain wall, including its chirality, by detecting stray field from the end portion of their associated nanowire 100. It will be appreciated that the nanowire pipeline is thus providing a FIFO type serial memory in that the data is input at one end of the nanowire and read out of the other end.
• the magnetic detectors may be based on magnetic tunnel junctions, spin valves or the Hall effect (e.g. Bismuth or InSb) for example as is known in the art.
• Another alternative would be to have a magnetic detector in direct electrical contact with the nanowires, such that the nanowires form the so-called free layer of a magnetic tunnel junction or spintronic device.
• FIG. 13 is schematic side section view in the xz plane of an input side of a multi-layer memory device according to a further embodiment of the invention. The figure shows a stack of nanowire grids.
• Each layer 120 is formed by the nanowire grid of magnetic material separated by islands 123 of non-magnetic material.
• the nanowire grid layers 120 are separated from each other in the z-direction by non- magnetic material layers 122 which may be made of the same material as the islands.
• Three pairs of magnetic and non-magnetic layers are shown by way of example.
• the nanowires may be made of Permalloy or other magnetic material.
• the non-magnetic material may be any conveniently fabricated materials with suitable electrical and thermal insulating properties that are compatible with the magnetic material and the various connecting wires for inducing domain nucleation.
• the non-magnetic material may be silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ), aluminium oxide (Al 2 O 3 ), aluminium nitride (AlN) or some other material generally compatible with the device integration.
• the thickness of the non-magnetic spacer layers 122 between the nanowire grid layers 120 should be large enough to minimise magnetostatic interlay er coupling between domains in neighbouring layers. However, it should not be thicker than necessary, since it will merely increase the total thickness of the stack without benefit, thus making it more difficult to fabricate.
• a non-magnetic layer thickness of around 50 nm, e.g. 30-70 nm or 20-80 nm is probably close to the optimum.
• nanowire grid layers 120 there may be any desired number of nanowire grid layers 120.
• the device structure is inherently scalable in the z-direction, which is one of its key advantages, so a large number of nanowire layers may be provided.
• 10-1000 or 100-1000 or more nanowire grid layers may be provided in a device.
• the memory storage capacity will scale essentially linearly with the number of layers so will influence the choice of the number of layers in any given device.
• each nanowire layer terminates in the -x-direction before the end of the nanowire layer below it, so the nanowire layers are staggered in the x- direction to form a terracing or stepped structure through successive termination of the uppermost pair of layers.
• a single metal or metallic electrode 126 that extends in the y-direction (out of the plane of the figure). These are the electrodes forming the nucleation inducing wires of the data read-in units described above.
• One such electrode is provided for each nanowire, so there are as many electrodes 126 on each step as there are nano wires per layer.
• Each electrode will have a relatively short portion extending in the y-direction over the end of the associated nanowire (the illustrated portion) and two relatively long portions leading to the interconnects that extend generally in the x-direction.
• the illustrated short portion of each electrode 126 is thus arranged on the non-magnetic layer and above an end portion of an associated nanowire.
• the electrodes 126 are examples of nucleation field generators and can be variously referred to as domain wall injection electrodes, data input electrodes or read-in electrodes to indicate their function in the device.
• the data input function is now described.
• the nucleation field of a nanowire reduces towards its end. Consequently, if a magnetic field is applied along the length of a nanowire which is above the locally reduced nucleation field at the nanowire end portion, but below the nucleation field in the main body of the nanowire, then a domain wall (or domain) can be created at the end portion of the nanowire.
• the current can be selected so that the magnetic field it generates in the nanowire 12O 2 is above the locally reduced nucleation field at the nanowire end portion, but below the nucleation field in the main body of the nanowire.
• the peak magnetic field generated by the current flowing in the electrode 126 2 is incapable of creating a domain wall in the bottom nanowire 12O 3 , since to do so it would need to exceed the nucleation field for the main body of the nanowire in view of the fact that the end of the bottom nanowire 12O 3 is well separated from the electrode 126 2 . It will thus be appreciated that the stepped structure means that each electrode
• 126 n creates a field that is local to the end region of its associated nanowire layer 12O n and so can selectively create domain walls only in that nanowire layer by exploiting the locally reduced nucleation field caused by end effects. Moreover, it will be appreciated that this is achieved without having to resort to 3D contacting or addressing scheme.
• the whole contacting and addressing scheme is kept planar, i.e. 2D, even though the memory structure, i.e. the nanowires, are arranged in 3D.
• the benefits of a 3D memory are thus achieved, i.e. increased memory capacity per unit chip area, without additional complexity associated with having to use a 3D contacting and addressing scheme.
• each nanowire on the input side with its own electrode 126 may be the limiting factor in the packing density of the nanowires in the y-direction.
• the nanowires may need to be separated by 1-10 ⁇ m or more at least at the external contacting location for the lead frame to provide room for the input addressing. Splaying of the wires may be used so the separation is sufficiently large at the lead frame, but reduces to a nanoscale separation where the electrodes 126 cross the nanowire end portions.
• the electrodes 128, and other electrodes necessary for the device are a pure or alloy of a metal (e.g. aluminium, gold, silver or copper) or metallic (e.g. suicide or degenerately doped semiconductor), preferably one that is non-magnetic or only weakly magnetic.
• a metal e.g. aluminium, gold, silver or copper
• metallic e.g. suicide or degenerately doped semiconductor
• Figure 14 is schematic side section view in the xz plane of an output side of the multi-layer memory device of Figure 13.
• the same nanowire layers 120 and non- magnetic layers 122 as shown in Figure 13 are evident.
• the nanowire layers 120 and their associated non-magnetic layers 122 terminate in a staggered manner, whereby the lowest layers 12Oi and 122] terminate first, as viewed in the +x- direction.
• This termination causes each of the overlying pairs of layers 120 and 122 to lower or step down by the combined thickness of the terminated bottom layer. This is schematically illustrated as stepping down over a relatively limited extent in the x- direction in the form of a ramp.
• a magnetic detector 128 n is shown embedded in the substrate 124. These magnetic detectors operate in the same manner as described above for the single layer embodiment, and the same comments apply regarding the types of detector that may be employed and so forth.
• Figures 15A and 15B are schematic side section views in the xz plane showing fabrication of an input side of the multi-layer memory device.
• an edge portion of a shadow mask 134 is used to define the end terminations of the pairs of nanowire and non-magnetic layers 120, 122 and is advanced in increments between deposition of each pair of layers by an amount 's' in the x-direction.
• the advances will typically be kept constant, but in principle these could be varied from step to step if desired.
• Figure 15A shows deposition of the first pair of nanowire and non-magnetic layers 12O 1 , 122i in which the shadow mask edge portion 134 is in a first position. It will be appreciated that the ends of the nanowires in layer 12Oi will not be precise ends, but rather may well have some tapering caused by penumbra shadowing or other effects at the edge of the shadow mask and as a result of the vertical separation between the substrate and the mask.
• Figure 15B illustrates this deposition of the second pair of nanowire and nonmagnetic layers 12O 2 , 122 2 in which the shadow mask 134 is in a second position. It will thus be understood how a succession of many pairs of layers can be formed to create multiple layers of nanowire grids with steps of width V in the x-direction separating each nanowire layer.
• the previously described data input electrodes 126 are then fabricated, but are not shown in the present figures.
• Figures 16A and 16B are schematic side section views in the xz plane showing fabrication of an output side of the multi-layer memory device.
• Figures 16A and 16B are comparable schematic side section views to Figures 15A and 15B showing the other ends of the data-carrying nanowires, namely the data output end of the memory device. These figures are in the xz plane, the same as Figures 15A and 15B. It will be understood that Figure 16A is showing the same instant in time as Figure 15 A. Similarly, Figure 16B is showing the same instant in time as Figure 15B.
• a shadow mask edge portion 136 is also used which may be part of the same shadow mask as used to define the terraces on the input side, or part of an independent separate shadow mask. Like the data input side shadow mask it is advanced in increments in the +x-direction between deposition of successive pairs of layers 120, 122.
• the advance distance is shown as being of distance V in the x- direction. This may be different for each step if desired, although it is envisaged that it will be held constant for ease of design. Moreover, the step size V may be the same as V (e.g. if the shadow masks edge portions 134 and 136 are part of the same mask structure) or different. They can be different, since the choice of x separation of adjacent data input electrodes 126 may be independent of the choice of x separation of the magnetic detectors at the data output end. In any case, the advance distance V defines the extent in the x-direction of the steps or terraces between the ramps that are created by the successive termination of the data-carrying nanowires in each layer in turn, starting from the bottom nanowire grid layer.
• Figure 17A is a schematic plan view in the xy plane of a shadow mask 140 and wafer 142 used in the fabrication process of the multi-layer memory device.
• Figure 17B is schematic side view in the xz plane of the same features as shown in Figure 17A.
• the mask 140 is generally of circular shape to match the shape of a wafer 142 of the desired diameter.
• the mask 140 has an array of apertures or holes 144 distributed over the mask 140 which are illustrated as being generally square, but may be rectangular or any other shape with well defined leading and trailing edge portions as viewed in the x-direction to form the mask end portions 134 and 136 respectively described further above.
• the apertures are illustrated highly schematically and it will be appreciated that they may each have a more complex structure to provide conventional lithography features.
• the mask will be moved in stepwise fashion in the x-direction during fabrication to allow fabrication of the terraced structure of the device through deposition of material flux in the -z- direction as schematically illustrated by the downward arrows in Figure 17B.
• the mask will be mounted a short distance, e.g. approximately
• the shadow mask can either be made by micromachining a silicon wafer such that there are etched holes in it defined by photolithography, or by traditional mechanical machining of a thin metal plate. A given mask can be used for the production of several wafers. The lifetime limit of a mask will be determined by build-up of deposited material on the edges of the apertures in the mask, causing them to become roughened.
• the wafer is coated with photoresist and lines defining the magnetic nanowires exposed, developed and etched in the normal photolithography process.
• the photomask needs to define data-carrying nanowires that are long enough to completely traverse all of the steps in the terrace.
• Each nanowire has a length T, a width W, and a depth 'd'.
• the nanowire width is typically in the submicron range, such as less than 0.2 ⁇ m (200 nm), more especially a width of the order of what is achievable with conventional lithography (currently 130 nm - 65 nm but ever reducing).
• the nanowire depth 'd' is defined by thickness of the magnetic material.
• the nanowires will be fabricated by some form of deposition process, such as chemical vapour deposition (CVD), physical vapour deposition (PVD), thermal evaporation or sputtering and have a thickness typically in the range 1 nm to 100 nm.
• the magnetic material may be homogenous or inhomogeneous. Homogeneous magnetic materials include ferromagnetic materials and ferrimagnetic materials. Specific examples are Permalloy, other nickel-iron alloys, a cobalt-iron alloy, or nickel-cobalt-iron alloys. Further examples are alloys containing one or more of Ni, Co and Fe optionally including one or more of Si, B, Zr, Hf, Cr, Pd, and Pt.
• the nanowires will be deposited on a suitable substrate material, typically a silicon (Si) or other semiconductor substrate for integration with integrated circuit elements.
• a suitable substrate material typically a silicon (Si) or other semiconductor substrate for integration with integrated circuit elements.
• the electrodes can be made of any suitable conductors, including Au, Cu, Al,
• data-carrying nanowires of length up to the chip size, which may be of the order of 1 mm to 1 cm or perhaps a few em's.
• the clocking nanowires could be of similar length or may be shorter.
• the grid spacing is envisaged to be down to the minimum achievable with then-current state of the art lithography processing, e.g. 90 run today, soon to be 65 nm.
• grid spacings of down to twice the nanowire width are topographically possible, so that the grid spacing could be as low as twice the lithography limited dimension.
• grid spacings of a larger multiple of the lithographic limit are desirable, e.g. at least 3, 4, 5, 6, 7, 8, 9 or 10 times the nanowire width to provide data-carrying nanowires with perhaps 1000 - 100,000 crosses with the clocking nanowires, most likely between a few thousand and tens of thousands of crossing nodes.
• the nanowires need not be straight. In this respect it is known that shallow bends of less than about 30 degrees in nanowires do not create significant domain wall pinning effects. Bends thus may be incorporated, for example when this is convenient for device integration.
• Figure 18 shows simulation results of a head-to-head (i.e. positively charged) data domain wall with an 'up' chirality initially in the left arm of a data nanowire being captured at a junction by a tail-to-tail (i.e. negatively charged) transverse domain wall of 'left' chirality passing down the clocking nanowire.
• Six panels are shown of the magnetisation in the cross region at six successive time intervals.
• a 'suck' action is shown which is similar to that shown schematically in Figures 5A-D except that the domain wall in the clocking nanowire passes downwards (not upwards) in the simulation. This difference is however not relevant to device action.
• a head-to-head (data) domain wall with an 'up' chirality is visible in the left arm and a tail-to-tail (clocking) domain wall with a 'left' chirality is visible in the top arm.
• the clocking domain wall arrives at the junction and attracts the data domain wall.
• the data domain wall remains at the junction and the clocking domain wall emerges into the bottom arm.
• the 'suck' action is complete with the data domain wall stably pinned at the junction, and the clocking nanowire having no domain wall in the vicinity of the junction.
• Figure 19 shows simulation results of a head-to-head (i.e. positively charged) data domain wall with an 'up' chirality initially captured at the junction and then ejected from the cross to the right by a head-to-head (i.e. positively charged) transverse domain wall of 'right' chirality passing down the clocking nanowire.
• Five panels are shown of the magnetisation in the cross region at five successive time intervals
• a 'spit' action is shown which is similar to that shown schematically in Figures 5E-H except that the domain wall in the clocking nanowire passes downwards (not upwards) in the simulation. This difference is however not relevant to device action.
• the terminations of the nanowires at the data input side of the device need not be as described above, but could instead be similar to the read out structure, with the field generating electrodes being embedded in or otherwise integrated with the semiconductor substrate.
• the magnetic field generator need not be arranged above the magnetic nanowire structure, i.e. above the substrate. It could instead be arranged below the substrate, for example bonded to the underside of the substrate, which may be etched away to allow the magnetic field generator to be arranged closer to the nanowire array. Indeed if two magnetic field generators are desired for generating fields in the x and y directions respectively, it may be convenient if one is bonded above the substrate and the other below.
• the distance that the generated magnetic field will remain homogenous in strength above a field generating chip is roughly equal to the lateral size of the chip itself. So if there is a 1 cm square field generator chip, as long as the storage layers are within approximately 1 cm of the surface of the field generator, field intensity will be maintained. In this case, it would be easy to fix the field generator underneath the storage chip. However, it is not necessary to activate all of the nanowires at a given time. Rather, the data storage can be sectored so that only the sector containing the file of interest is shifted. This allows the field generator to be segmented, so that it is not necessary to energise the entire generator, thus dramatically reducing power dissipation.
• a serial magnetic mass storage device and associated data storage method is provided based on magnetic nanowires that support single magnetic domains separated by domain walls.
• Each data-storing nanowire has a plurality of crossing nanowires along its length, forming cross junctions that constitute domain wall pinning sites.
• Data is fed through each data-storing nanowire by moving the magnetic domains under the action of a field that alternates between alignment and anti-alignment with the crossing nanowires.
• the data is encoded in the chirality of the domain walls, with up and down chirality transverse domain walls being used to encode O's and l's.
• Data is clocked into each nanowire with suitable nucleation generators capable of nucleating domains with domain walls of pre-defined chirality.
• Data is clocked out of each nanowire with suitable magnetic field sensors that sense the chirality.

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  • 2008-03-31 WO PCT/GB2008/001116 patent/WO2008139131A1/en active Application Filing
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