WO2008126229A1 - 半導体集積回路および制御信号分配方法 - Google Patents

半導体集積回路および制御信号分配方法 Download PDF

Info

Publication number
WO2008126229A1
WO2008126229A1 PCT/JP2007/056967 JP2007056967W WO2008126229A1 WO 2008126229 A1 WO2008126229 A1 WO 2008126229A1 JP 2007056967 W JP2007056967 W JP 2007056967W WO 2008126229 A1 WO2008126229 A1 WO 2008126229A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
semiconductor integrated
control signal
distributing method
signal distributing
Prior art date
Application number
PCT/JP2007/056967
Other languages
English (en)
French (fr)
Inventor
Masato Susuki
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/056967 priority Critical patent/WO2008126229A1/ja
Priority to JP2009508779A priority patent/JP4774119B2/ja
Priority to EP07740405A priority patent/EP2136396A4/en
Publication of WO2008126229A1 publication Critical patent/WO2008126229A1/ja
Priority to US12/585,962 priority patent/US7999594B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

　チップ（半導体集積回路）１００は、ＲＡＭマクロ群１００ａ，１００ｂが同一のタイミングで同一の処理を実行しないように、フェイズ制御信号がオンオフとなるタイミングを各ＲＡＭマクロ群１００ａ，１００ｂごとに調整し、調整したフェイズ制御信号を各ＲＡＭマクロ群１００ａ，１００ｂにそれぞれ分配して出力する（例えば、オンオフの関係が逆となるフェイズ制御信号ｐｃ１，ｐｃ２をそれぞれＲＡＭマクロ群１００ａ，１００ｂに出力する）。
PCT/JP2007/056967 2007-03-29 2007-03-29 半導体集積回路および制御信号分配方法 WO2008126229A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2007/056967 WO2008126229A1 (ja) 2007-03-29 2007-03-29 半導体集積回路および制御信号分配方法
JP2009508779A JP4774119B2 (ja) 2007-03-29 2007-03-29 半導体集積回路および制御信号分配方法
EP07740405A EP2136396A4 (en) 2007-03-29 2007-03-29 INTEGRATED SEMICONDUCTOR CONTROL AND CONTROL SIGNAL DISTRIBUTION METHOD
US12/585,962 US7999594B2 (en) 2007-03-29 2009-09-29 Semiconductor integrated circuit and control signal distribution method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056967 WO2008126229A1 (ja) 2007-03-29 2007-03-29 半導体集積回路および制御信号分配方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/585,962 Continuation US7999594B2 (en) 2007-03-29 2009-09-29 Semiconductor integrated circuit and control signal distribution method

Publications (1)

Publication Number Publication Date
WO2008126229A1 true WO2008126229A1 (ja) 2008-10-23

Family

ID=39863410

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/056967 WO2008126229A1 (ja) 2007-03-29 2007-03-29 半導体集積回路および制御信号分配方法

Country Status (4)

Country Link
US (1) US7999594B2 (ja)
EP (1) EP2136396A4 (ja)
JP (1) JP4774119B2 (ja)
WO (1) WO2008126229A1 (ja)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5666322A (en) 1995-09-21 1997-09-09 Nec Electronics, Inc. Phase-locked loop timing controller in an integrated circuit memory
JPH1065124A (ja) * 1996-06-10 1998-03-06 Hitachi Ltd 半導体集積回路装置
JP2001273764A (ja) * 2000-03-29 2001-10-05 Hitachi Ltd 半導体記憶装置
US20060039227A1 (en) 2004-08-17 2006-02-23 Lawrence Lai Memory device having staggered memory operations
JP2006228325A (ja) * 2005-02-17 2006-08-31 Hitachi Ltd 半導体装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW318933B (en) 1996-03-08 1997-11-01 Hitachi Ltd Semiconductor IC device having a memory and a logic circuit implemented with a single chip
JP3620440B2 (ja) 2000-11-20 2005-02-16 日本電気株式会社 半導体集積回路とそのクロック分配方法
JPWO2004081450A1 (ja) 2003-03-10 2006-06-15 株式会社 リーテック ガス燃焼制御方法及びガス燃焼装置
KR100665232B1 (ko) * 2005-12-26 2007-01-09 삼성전자주식회사 동기식 반도체 메모리 장치
US7616043B2 (en) * 2008-02-12 2009-11-10 Sony Computer Entertainment Inc. Methods and apparatus for managing LSI power consumption and degradation using clock signal conditioning

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5666322A (en) 1995-09-21 1997-09-09 Nec Electronics, Inc. Phase-locked loop timing controller in an integrated circuit memory
JPH1065124A (ja) * 1996-06-10 1998-03-06 Hitachi Ltd 半導体集積回路装置
JP2001273764A (ja) * 2000-03-29 2001-10-05 Hitachi Ltd 半導体記憶装置
US20060039227A1 (en) 2004-08-17 2006-02-23 Lawrence Lai Memory device having staggered memory operations
JP2006228325A (ja) * 2005-02-17 2006-08-31 Hitachi Ltd 半導体装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2136396A4 *

Also Published As

Publication number Publication date
JPWO2008126229A1 (ja) 2010-07-22
JP4774119B2 (ja) 2011-09-14
EP2136396A1 (en) 2009-12-23
US7999594B2 (en) 2011-08-16
EP2136396A4 (en) 2010-06-02
US20100019823A1 (en) 2010-01-28

Similar Documents

Publication Publication Date Title
WO2002023358A3 (en) Digital system of adjusting delays on circuit boards
WO2006138425A3 (en) Chip spanning connection
WO2007011439A3 (en) Processor controlled interface
WO2005081316A3 (de) Halbleiterbauteil mit einem umverdrahtungssubstrat und verfahren zur herstellung desselben
WO2004097838A3 (de) Speicher-schaltungsanordnung und verfahren zur herstellung
EP2296276A3 (en) System with dual rail regulated locked loop
WO2005041251A3 (en) Digitally controlled delay cells
WO2007100529A3 (en) Spread-spectrum clocking
WO2004073175A3 (en) Adaptive input logic for phase adjustments
WO2003100829A3 (en) Forming a multi segment integrated circuit with isolated substrates
WO2007134589A3 (de) Hochleistungsschaltmodul und verfahren zur erzeugung von schaltsynchronität bei einem hochleistungsschaltmodul
AU2003240534A1 (en) Memory buffer arrangement
WO2007123908A3 (en) Droplet-based multiwell operations
WO2002033570A3 (en) Digital signal processing apparatus
WO2007124517A3 (en) Detonator system
AU2003291553A1 (en) Structure to reduce signal cross-talk through semiconductor substrate for system on chip applications
WO2009040179A3 (de) Schaltungsanordnung zur signalaufnahme und -erzeugung sowie verfahren zum betreiben dieser schaltungsanordnung
ATE524889T1 (de) Verfahren und vorrichtung zum digital- teilnehmeranschlusszugriffsmultiplexer-stacking
EP1618442A4 (en) METHOD AND SYSTEM FOR POWER SHARING BETWEEN SEVERAL POWER MODULES
TW200719734A (en) Video delay stabilization system and method
ATE531131T1 (de) Verfahren und vorrichtung zum verteilen mehrerer signaleingänge an mehrere integrierte schaltungen
WO2005069333A8 (en) Switching device module
WO2008043427A3 (en) Device and method for synchronizing the states of a plurality of sequential processing units
TW200644590A (en) Boot systems and methods and related devices
GB2436505A (en) A single chip having a magnetoresistive memory

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07740405

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2009508779

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2007740405

Country of ref document: EP