WO2008124998A1 - Méthode et dispositif d'ajustement dynamique de la largeur de bande d'un canal hdlc - Google Patents

Méthode et dispositif d'ajustement dynamique de la largeur de bande d'un canal hdlc Download PDF

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Publication number
WO2008124998A1
WO2008124998A1 PCT/CN2008/000579 CN2008000579W WO2008124998A1 WO 2008124998 A1 WO2008124998 A1 WO 2008124998A1 CN 2008000579 W CN2008000579 W CN 2008000579W WO 2008124998 A1 WO2008124998 A1 WO 2008124998A1
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WIPO (PCT)
Prior art keywords
hdlc
control frame
shared memory
channel
processing unit
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PCT/CN2008/000579
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English (en)
Chinese (zh)
Inventor
Yu Chen
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Huawei Technologies Co., Ltd.
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Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Publication of WO2008124998A1 publication Critical patent/WO2008124998A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/08—Configuration management of networks or network elements
    • H04L41/0896—Bandwidth or capacity management, i.e. automatically increasing or decreasing capacities
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/70—Admission control; Resource allocation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/70—Admission control; Resource allocation
    • H04L47/76—Admission control; Resource allocation using dynamic resource allocation, e.g. in-call renegotiation requested by the user or requested by the network in response to changing network conditions
    • H04L47/762—Admission control; Resource allocation using dynamic resource allocation, e.g. in-call renegotiation requested by the user or requested by the network in response to changing network conditions triggered by the network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC

Definitions

  • the present invention relates to the field of communications, and in particular to a method and apparatus for dynamically adjusting the bandwidth of an advanced data link control channel. Background technique
  • HDLC High Level Data Link Control
  • OSI Open Systems Interconnection
  • each HDLC channel When carried on an E1/T1 line, each HDLC channel can be carried in one or more consecutive time slots or sub-time slots fixed on the E1/T1 line. In an actual application, multiple HDLC channels are configured on an E1/T1 line. Different HDLC channels occupy different time slots or sub-time slots. The HDLC channels do not interfere with each other. Different HDLC channels can carry Data streams of the same or different application types.
  • FIG. 1 is a schematic diagram of a structure of an existing HDLC frame.
  • an HDLC data frame is identified by a hexadecimal number 0x7E as a start identifier and an end flag of an HDLC data frame, and includes a frame before the end of the HDLC data frame.
  • HDLC data frames are padded with 0x7E or OxFF. Two consecutive HDLC data frames can share a 0x7E as the end flag of the previous HDLC data frame and the start flag of the next HDLC data frame.
  • OxFF can indicate that the HDLC data frame has an error.
  • the HDLC processing unit finds more than 7 consecutive 1s in the received HDLC data frame, it determines that there is a frame suspension identifier in the HDLC data frame, indicating that the HDLC data frame has an error.
  • the HDLC processing unit that transmits the HDLC data frame needs to use the 0 insertion function, that is, if the field is found in the field other than the frame identifier in the HDLC data frame.
  • the HDLC processing unit that receives the HDLC data frame needs to use the 0 delete function, ie if In the HDLC data frame, five consecutive 1s are found in the field except the frame identifier, and the 5 consecutive 1s are followed by a 0, and this 0 is removed.
  • the HDLC protocol processing device includes: a physical layer interface unit, a shared memory, a service processing unit, an HDLC configuration management unit, and an HDLC processing unit.
  • the physical layer interface unit is configured to perform bit stream forwarding between the E1/T1 port and the HDLC processing unit.
  • Shared memory is used to buffer data frames to be sent or received.
  • the service processing unit is configured to cache the data frame to be sent in the shared memory, and obtain the received data frame buffered in the shared memory. Further, the service processing unit may be configured to provide the received data frame to other units in the telecommunication network element. To perform data processing by other units.
  • the HDLC configuration management unit is configured to configure an HDLC channel, and a mapping relationship between the HDLC channel and the physical layer time slot or the sub-time slot, and provide corresponding channel configuration information and time slot channel mapping configuration information to the HDLC processing unit.
  • Channel configuration information refers to the information about the currently configured HDLC channel, such as the number of HDLC channels currently configured.
  • the HDLC processing unit is configured to read a data frame to be sent from the shared memory in the sending direction, and perform HDLC protocol processing on the corresponding data frame, for example, generating a frame identifier such as a start flag, an end flag, and a frame abort identifier of the HDLC data frame. And completing the filling between the data frames, generating the frame check, completing the 0 insertion, performing the high and low bit swapping in the byte, and inverting the port data, and generating the HDLC data frame to be sent on the HDLC channel, according to the time slot channel.
  • a frame identifier such as a start flag, an end flag, and a frame abort identifier of the HDLC data frame.
  • mapping the configuration information to map the bit stream in the HDLC data frame on the HDLC channel to the corresponding time slot or sub-time slot, and send it to the E1/T1 port of the corresponding time slot or sub-time slot through the physical layer interface unit; And mapping the bit stream on the time slot or the sub-time slot from the physical layer interface unit to the corresponding HDLC channel according to the configuration information, performing HDLC protocol processing on the bit stream, for example, detecting a start flag, an end flag, and a frame of the HDLC data frame.
  • the time slot or subslot corresponding to an HDLC channel it may be necessary to adjust the time slot or subslot corresponding to an HDLC channel. For example, the number of timeslots or subslots configured for an HDLC channel is insufficient, causing the HDLC channel to fail to meet the bandwidth requirement, and another HDLC channel on the same E1/T1 line is too idle, resulting in bandwidth resources.
  • the time slots or sub-time slots corresponding to the two HDLC channels can be adjusted, so that the two HDLC channels can avoid the bandwidth resources while meeting the requirements of the respective bandwidth applications. waste.
  • the two ends of the HDLC communication agree to divide one or consecutive multiple time slots or sub-time slots on the E1/T1 line as dedicated control links.
  • the device is initiated by the HDLC communication device.
  • the initiator sends a control command to the peer through the dedicated control link.
  • the control command has a pre-agreed format.
  • Information that needs to be modified on the HDLC channel such as the modification time, the mapping relationship between the modified HDLC channel and the time slot or sub-timeslot, etc., and the receiving end performs corresponding modification according to the content of the received control command, thus, To a lesser extent, the impact of bandwidth adjustment of the HDLC channel on data stream transmission is reduced.
  • the dedicated control link always needs to occupy a certain number of time slots or sub-time slots, especially when the bandwidth adjustment of the HDLC channel is infrequent, and the dedicated control link is set.
  • the utilization rate itself is very low, resulting in waste of time slots or sub-slot resources.
  • FIG. 3 is a schematic diagram of the principle of dynamically adjusting the bandwidth of the HDLC channel.
  • three communication devices are connected to the transmission time slot switching device through one E1 line, and the transmission time slot switching device will Part of the time slot of the El-1 line is mapped to the time slot of the El-2 line, and part of the time slot of the E1-1 line is mapped to the time slot of the E1-3 line.
  • a plurality of HDLC channels can be configured between the communication device 1 and the communication device 2, hereinafter referred to as HDLC channel group A
  • a plurality of HDLC channels can be configured between the communication device 1 and the communication device 3, hereinafter referred to as HDLC channel group B.
  • the embodiments of the present invention provide a method and an apparatus for dynamically adjusting the bandwidth of an advanced data link control channel, which avoids waste of time slots or sub-slot resources, and does not affect normal service processing.
  • the apparatus for dynamically adjusting the bandwidth of the advanced data link control channel includes: an HDLC configuration management unit, an HDLC processing unit, a shared memory, and a physical layer interface unit, where the HDLC of the originating side is
  • the configuration management unit is configured to modify the slot channel mapping configuration information in the receiving direction, and write the channel adjustment notification to be sent to the shared memory, and modify the slot channel mapping configuration information in the sending direction of the local end according to the obtained channel adjustment response;
  • the HDLC configuration management unit on the responsive end side is configured to modify the bidirectional channel channel mapping configuration information of the local end transceiver according to the obtained channel adjustment notification, and write the channel adjustment response to be sent to the shared memory;
  • the HDLC processing unit is configured to receive the HDLC frame according to the slot channel mapping configuration information in the receiving direction, send a channel adjustment notification in the shared memory, write the received channel adjustment response into the shared memory, and configure the configuration information according to the slot channel mapping in the sending direction.
  • the unit is configured to write the received channel adjustment notification into the shared memory, receive and send the HDLC frame according to the bidirectional time slot channel mapping configuration information, and send a channel adjustment response in the shared memory; the shared memory is used for buffering to be sent and / or received data stream;
  • the physical layer interface unit is configured to perform bitstream forwarding between the E1/T1 port and the HDLC processing unit.
  • the apparatus for dynamically adjusting the bandwidth of the advanced data link control channel includes: an HDLC configuration management unit, an HDLC processing unit, a shared memory, and a physical layer interface unit, where the HDLC configuration management unit at the originating end side is used for Modifying the slot channel mapping configuration information in the receiving direction, and writing the channel adjustment notification to be sent to the shared memory, and modifying the slot channel mapping configuration information in the sending direction of the local end according to the obtained channel adjustment response;
  • the HDLC processing unit is configured to receive an HDLC frame according to the slot channel mapping configuration information in the receiving direction, send a channel adjustment notification in the shared memory, write the received channel adjustment response into the shared memory, and configure the slot channel mapping according to the sending direction.
  • the information is sent to the HDLC frame;
  • the shared memory is used to buffer the data stream to be transmitted and/or received; and the physical layer interface unit is configured to perform bit stream forwarding between the E1/T1 port and the HDLC processing unit.
  • the apparatus for dynamically adjusting the bandwidth of the advanced data link control channel includes: an HDLC configuration management unit, an HDLC processing unit, a shared memory, and a physical layer interface unit, where the HDLC configuration management unit on the response end side is used for Modifying the bidirectional channel channel mapping configuration information of the local end to send and receive according to the obtained channel adjustment notification, and writing the channel adjustment response to be sent to the shared memory; the HDLC processing unit on the response end side is configured to notify the received channel adjustment Writing to the shared memory, receiving and transmitting the HDLC frame according to the bidirectional time slot channel mapping configuration information, and transmitting the channel adjustment response in the shared memory; the shared memory is used to buffer the data stream to be sent and/or received;
  • the layer interface unit is configured to perform bit stream forwarding between the E1/T1 port and the HDLC processing unit.
  • the method for dynamically adjusting the bandwidth of the advanced data link control channel includes: the HDLC processing unit at the originating end receives the HDLC frame according to the slot channel mapping configuration information in the receiving direction, and sends a channel adjustment notification;
  • the HDLC configuration management unit modifies the bidirectional channel channel mapping configuration information of the local end transceiver according to the acquired channel adjustment notification, and the HDLC processing unit on the response end receives and transmits the HDLC frame according to the slot channel mapping configuration information in the sending and receiving direction, and sends the channel.
  • the HDLC configuration management unit on the originating side is obtained according to The channel adjustment response is modified to the slot channel mapping configuration information in the sending direction of the local end, and the HDLC processing unit on the initiating end transmits the HDLC frame in the slot channel mapping configuration information in the sending direction.
  • the method for dynamically adjusting the bandwidth of the advanced data link control channel includes: the HDLC processing unit at the originating end receives the HDLC frame according to the slot channel mapping configuration information in the receiving direction, and sends a channel adjustment notification;
  • the HDLC configuration management unit modifies the slot channel mapping configuration information of the local end transmission direction according to the obtained channel adjustment response, and the HDLC processing unit of the originating end sends the HDLC frame according to the slot channel mapping configuration information in the sending direction.
  • the method for dynamically adjusting the bandwidth of the advanced data link control channel includes: the HDLC configuration management unit on the response end side modifies the bidirectional channel channel mapping configuration information of the local end transceiver according to the obtained channel adjustment notification, and the response end side
  • the HDLC processing unit receives and transmits the HDLC frame according to the slot channel mapping configuration information of the sending and receiving direction, and transmits a channel adjustment response.
  • the HDLC processing unit on the initiating end receives the HDLC frame according to the modified slot direction channel mapping configuration information, and sends a channel adjustment notification;
  • the HDLC configuration management unit on the response end side obtains the The channel adjustment notification modifies the two-way time slot channel mapping configuration information of the local end transceiver, and the HDLC processing unit on the response end receives and transmits the HDLC frame according to the modified time slot channel mapping configuration information of the sending and receiving direction, and sends a channel adjustment response;
  • the HDLC configuration management unit of the end side modifies the slot channel mapping configuration information of the local end transmission direction according to the obtained channel adjustment response, and the HDLC processing unit of the originating end sends the HDLC frame according to the modified slot direction channel mapping configuration information in the sending direction.
  • DRAWINGS 1 is a schematic structural diagram of a conventional HDLC frame
  • FIG. 2 is a schematic structural diagram of an existing HDLC protocol processing apparatus
  • FIG. 3 is a schematic diagram showing the principle of dynamically adjusting the bandwidth of the HDLC channel
  • FIG. 4 is a schematic structural diagram of an apparatus for realizing dynamic adjustment of bandwidth of an HDLC channel according to Embodiment 1 of the present invention
  • FIG. 5 is a schematic structural diagram of an apparatus for realizing dynamic bandwidth adjustment of an HDLC channel according to Embodiment 2 of the present invention.
  • FIG. 6 is a flowchart of realizing dynamic adjustment of bandwidth of an HDLC channel according to Embodiment 3 of the present invention
  • FIG. 7 is a schematic structural diagram of an apparatus for realizing dynamic adjustment of bandwidth of an HDLC channel according to Embodiment 4 of the present invention
  • FIG. 8 is a schematic structural diagram of an apparatus for realizing dynamic bandwidth adjustment of an HDLC channel according to Embodiment 5 of the present invention.
  • FIG. 9 is a schematic structural diagram of an apparatus for realizing dynamic bandwidth adjustment of an HDLC channel according to Embodiment 6 of the present invention.
  • FIG. 10 is a flowchart of implementing dynamic adjustment of HDLC channel bandwidth according to Embodiment 7 of the present invention. detailed description
  • the peer end of the communication in the dynamic adjustment process of the bandwidth of the HDLC channel, includes the HDLC configuration management unit and the HDLC processing unit, and either end can serve as the initiator of the HDLC channel bandwidth adjustment or the bandwidth of the HDLC channel.
  • the responding end side includes the HDLC configuration management unit and the HDLC processing unit, and the response end side also includes at least the HDLC configuration management unit and the HDLC processing unit.
  • the HDLC processing unit of the initiating end receives the HDLC frame according to the modified slot direction mapping configuration information of the receiving direction, and sends a channel adjustment notification.
  • the HDLC configuration management unit on the responding end adjusts the bidirectional time according to the obtained channel adjustment notification.
  • the channel mapping configuration information is modified, and the HDLC processing unit on the responding end receives and transmits the HDLC frame according to the modified slot channel mapping configuration information of the sending and receiving direction, and sends a channel adjustment response; the HDLC configuration management unit of the originating end side acquires Channel adjustment response
  • the slot channel mapping configuration information of the local end sending direction is modified, and the HDLC processing unit of the initiating end sends the HDLC frame according to the modified slot direction channel mapping configuration information in the sending direction.
  • the device for dynamically adjusting the bandwidth of the HDLC channel includes an HDLC configuration management unit, an HDLC processing unit, a shared memory, and a physical layer interface unit.
  • the HDLC configuration management unit on the initiating end side is configured to modify the slot channel mapping configuration information in the receiving direction, send a channel adjustment notification to the shared memory, and adjust the response to the slot channel mapping configuration information in the sending direction of the local end according to the acquired channel. The modification is performed.
  • the HDLC configuration management unit on the response end side is configured to modify the bidirectional channel channel mapping configuration information of the local end transceiver according to the obtained channel adjustment notification, and send a channel adjustment response to the shared memory.
  • the HDLC processing unit on the initiating end side is configured to receive the HDLC frame according to the slot channel mapping configuration information in the modified receiving direction, send a channel adjustment notification in the shared memory, and receive the channel adjustment response, according to the modified transmission direction slot channel.
  • the mapping configuration information is sent to the HDLC frame;
  • the HDLC processing unit on the response end side is configured to send and receive the channel adjustment notification to the shared memory, and receive and send the HDLC frame according to the modified bidirectional time slot channel mapping configuration information, and send the shared memory.
  • Channel adjustment response is used for forwarding the bit stream between the E1/T1 port and the HDLC processing unit.
  • the apparatus for dynamically adjusting bandwidth of an HDLC channel in this embodiment includes an HDLC configuration management unit, shared memory, and HDLC processing. unit.
  • the HDLC configuration management unit on the initiating end side is configured to modify the slot channel mapping configuration information in the receiving direction, directly write the channel adjustment initiation control frame into the shared memory, and adjust the response to the local end according to the channel read from the shared memory.
  • the slot channel mapping configuration information in the sending direction is modified; the HDLC configuration management unit on the responding end side is configured to adjust the originating control frame according to the channel read from the shared memory, and modify the bidirectional channel channel mapping configuration information of the local end transceiver. Write channel adjustment responses directly to shared memory.
  • the HDLC configuration management unit is further configured to configure a mapping relationship between the HDLC channel and the HDLC channel and the physical layer time slot or the sub-time slot, and provide corresponding channel configuration information and time slot channel mapping configuration information to the HDLC processing unit.
  • the HDLC processing unit on the initiating end side is configured to receive the HDLC frame according to the slot channel mapping configuration information in the modified receiving direction, and send the channel adjustment initiation control in the shared memory.
  • the frame is configured to receive the channel adjustment response, and send the HDLC frame according to the modified slot direction channel mapping configuration information; the HDLC processing unit on the response end side is configured to write the received channel adjustment initiation control frame into the shared memory, according to the modified
  • the transmitting and receiving bidirectional time slot channel mapping configuration information receives and transmits the HDLC frame, and transmits the channel adjustment response in the shared memory.
  • the HDLC configuration management unit on the initiating side is further configured to directly write the channel adjustment completion control frame to the shared memory; and the HDLC configuration management unit on the response end side is further configured to read the channel adjustment completion control frame from the shared memory.
  • the HDLC processing unit on the initiating end side is further configured to send a channel adjustment completion control frame in the shared memory; the HDLC processing unit on the response end side is further configured to directly write the received channel adjustment completion control frame into the shared memory.
  • the apparatus further includes: a physical layer interface unit for forwarding the bit stream between the E1/T1 port and the HDLC processing unit.
  • the apparatus may further include a service processing unit, configured to write the data frame to be sent to the shared memory, and read the received data frame buffered in the shared memory; further, the service processing unit may be used in the telecommunication network element.
  • Other units provide received data frames for data processing by other units.
  • a shared memory is divided into a data frame transmission area, a data frame reception area, and a control frame transmission area.
  • a control frame receiving area the data frame sending area is used for storing the data frame to be sent, the data frame receiving area is used for buffering the received data frame, the control frame sending area is used for storing the control frame to be sent, and the control frame receiving area is used for Store the received control frame.
  • the HDLC configuration management unit on the initiating end side is configured to modify the slot channel mapping configuration information in the receiving direction, directly write the channel adjustment initiation control frame into the control frame sending area of the shared memory, and directly read from the control frame receiving area of the shared memory.
  • the channel adjustment response is taken, and the slot channel mapping configuration information of the local end sending direction is modified according to the channel adjustment response;
  • the HDLC configuration management unit of the response end side is configured to directly read the channel adjustment initiation control frame from the control frame receiving area of the shared memory.
  • the bidirectional channel channel mapping configuration information of the local end transceiver is modified, and the channel adjustment response is directly written into the control frame receiving area of the shared memory.
  • the channel adjustment initiation control frame and the channel adjustment response are control frames.
  • the HDLC processing unit is configured to write the received control frame to the control frame receiving area of the shared memory.
  • the HDLC processing unit includes a memory, a first in first out (FIFO) buffer, a FIFO buffer control unit, an HDLC protocol processing unit, and a slot channel mapping processing unit.
  • FIFO first in first out
  • the memory is used to store the transmission direction slot channel mapping configuration table, the reception direction slot channel mapping configuration table, and the HDLC channel configuration table.
  • the transmission direction slot channel mapping configuration table, the reception direction slot channel mapping configuration table, and the HDLC channel configuration table stored in the memory are configured by the HDLC configuration management unit.
  • the transmission direction slot channel mapping configuration table and the reception direction slot channel mapping configuration table constitute the slot channel mapping configuration information.
  • the FIFO buffer is divided into two areas: a transmission area for buffering frames to be transmitted (data frames and/or control frames), and a reception area for buffering received frames (data frames and/or control frames) ).
  • the FIFO buffer control unit is configured to receive, in the sending direction, the transmission area of the FIFO buffer according to the HDLC channel configuration table stored in the memory, to receive the frame to be transmitted from the shared memory (the data frame from the shared memory data frame transmission area and/or from The control frame of the shared memory control frame transmission area), that is, the frame to be transmitted in the shared memory is written into the transmission area of the FIFO buffer, and the frame is a control frame, or a data frame, or a control frame and a data frame, and the FIFO buffer is determined.
  • the HDLC protocol processing unit is provided with the data stream constituting the complete frame; and the receiving area of the FIFO buffer is determined in the receiving direction.
  • the control area of the FIFO buffer is controlled according to the HDLC channel configuration table stored in the memory to output a control frame to the control frame receiving area of the shared memory, that is, in the receiving area of the FIFO buffer.
  • the control frame is written into the control frame receiving area of the shared memory, and the number of buffers in the receiving area of the FIFO buffer is determined.
  • the receiving area of the FIFO buffer is controlled according to the HDLC channel configuration table stored in the memory to output a data frame to the data frame receiving area of the shared memory, that is, the data frame in the receiving area of the FIFO buffer is written.
  • the data frame receiving area into the shared memory.
  • the FIFO cache control unit can distinguish between control frames and data frames by the control words contained in the frame. Since the data streams of different application types are transmitted on different HDLC channels, the data streams transmitted on the HDLC channels need to be separately processed. Therefore, when the FIFO buffer control unit controls the input and output of the FIFO buffer, it needs to be based on the HDLC channel. Configure the table to proceed.
  • the processing may include: a data frame transmission area of the shared memory outputs the data frame to be transmitted to a transmission area of the FIFO buffer, and the control frame transmission area of the shared memory outputs the control frame to be transmitted to the transmission area of the FIFO buffer.
  • the HDLC protocol processing unit is configured to perform HDLC protocol processing in the sending direction of the frame to be sent, for example, to generate a frame identifier such as a start flag, an end flag, a frame abort identifier of the HDLC frame, complete padding between frames, and generate frame check.
  • the 0 insertion, the high and low bit swapping in the byte, and the inversion of the port data are performed, and the HDLC frame to be transmitted on the HDLC channel is generated according to the HDLC channel configuration table stored in the memory, and the HDLC is sent to the slot channel mapping processing unit.
  • HDLC protocol processing on the received bit stream from the slot channel mapping processing unit, for example, detecting a frame identifier such as a start flag, an end flag, a frame abort identifier of the HDLC data frame, and detecting an HDLC data frame.
  • a frame identifier such as a start flag, an end flag, a frame abort identifier of the HDLC data frame
  • detecting an HDLC data frame for example, detecting a frame identifier such as a start flag, an end flag, a frame abort identifier of the HDLC data frame.
  • the HDLC configuration management unit on the initiating end side is further configured to directly write the channel adjustment completion control frame to the control frame sending area of the shared memory; the HDLC configuration management unit on the response end side is further configured to directly read from the control frame receiving area of the shared memory.
  • the channel adjustment completes the control frame.
  • the configuration table maps the bit stream in the HDLC frame on the HDLC channel to the corresponding time slot or sub-time slot, and sends it to the E1/T1 port of the corresponding time slot or sub-time slot through the physical layer interface unit, according to the reception stored in the memory.
  • the direction slot channel mapping configuration table maps bitstreams on time slots or sub-slots from the physical layer interface unit to respective HDLC channels, and transmits the bitstream of each HDLC channel to the HDLC protocol processing unit.
  • the physical layer interface unit is used for forwarding the bit stream between the E1/T1 port and the slot channel mapping processing unit.
  • FIG. 6 is a flowchart of the dynamic adjustment of the bandwidth of the HDLC channel in the third embodiment of the present invention.
  • the process of dynamically adjusting the bandwidth of the HDLC channel includes the following steps: Step 601: Initiating the HDLC of the end side
  • the configuration management unit determines that the bandwidth adjustment of the HDLC channel is required
  • the configuration of the receiving channel slot mapping configuration table of the local end is modified, and the channel adjustment initiation control frame is directly written into the control frame sending area of the shared memory.
  • Step 602 The HDLC processing unit on the initiating end receives the HDLC frame according to the modified receiving direction slot channel mapping configuration table, and sends the HDLC frame according to the original sending direction slot channel mapping configuration table, and reads from the control frame sending area of the shared memory.
  • the channel adjustment initiation control frame is adopted, and the channel control adjustment frame is processed by the HDLC protocol, and then the channel adjustment initiation control frame processed by the HDLC protocol is sent to the HDLC processing unit on the response side.
  • Step 603 The HDLC processing unit on the responding end performs HDLC protocol processing on the received channel adjustment initiation control frame, and determines that the received data stream can form a complete control frame, that is, the channel adjustment initiation control frame, and adjusts the channel to initiate the control frame.
  • a control frame receive area that is written directly to shared memory.
  • the HDLC processing unit on the initiating end side and the HDLC processing unit on the responding end side read the data frame to be sent from the data frame sending area of the shared memory, and the data frame to be sent is processed by the HDLC protocol, and then sent out;
  • the received data frame is processed by the HDLC protocol, and when it is determined that the received data stream can form a complete data frame, the data frame is written into the data frame receiving area of the shared memory.
  • Step 604 The HDLC configuration management unit on the response end directly reads the channel adjustment initiation control frame from the control frame receiving area of the shared memory, and adjusts the initiation control frame according to the channel to modify the bidirectional channel channel mapping configuration table of the local end transceiver, and then The channel adjustment response is written directly to the control frame transmission area of the shared memory.
  • Step 605 The HDLC processing unit on the responding end receives and transmits the HDLC frame according to the modified bidirectional time slot channel mapping configuration table, and reads the channel adjustment response from the control frame sending area of the shared memory, and performs HDLC on the channel adjustment response.
  • the protocol processes, and then sends the channel adjustment response processed by the HDLC protocol to the HDLC processing unit on the originating side.
  • Step 606 The HDLC processing unit of the initiating end performs HDLC protocol processing on the received channel adjustment response, and determines that the channel adjustment response is directly written into the shared memory when the received data stream can form a complete control frame, that is, the channel adjustment response. Control frame reception area.
  • Step 607 The HDLC configuration management unit of the initiating end directly reads the channel adjustment response from the control frame receiving area of the shared memory, and adjusts the response to the local receiving direction slot channel mapping according to the channel.
  • the configuration table is modified, and then the channel adjustment completion control frame is directly written into the control frame transmission area of the shared memory.
  • Step 608 The HDLC processing unit on the initiating end receives and transmits the HDLC frame according to the modified bidirectional time slot channel mapping configuration table, and reads the channel adjustment completion control frame from the control frame sending area of the shared memory, and the channel adjustment is completed.
  • the control frame performs HDLC protocol processing, and then sends a channel adjustment completion control frame processed by the HDLC protocol to the HDLC processing unit on the responding side.
  • Step 609 The HDLC processing unit on the responding end performs HDLC protocol processing on the received channel adjustment completion control frame, and determines that the received data stream can form a complete control frame, that is, when the channel adjustment completes the control frame, and the channel adjustment completes the control frame.
  • a control frame receive area that is written directly to shared memory.
  • Step 610 The HDLC configuration management unit on the response end directly reads the channel adjustment completion control frame from the control frame receiving area of the shared memory. At this point, the initiator and the response end cooperate to complete the dynamic adjustment of the HDLC channel bandwidth.
  • control frame and the data frame are buffered in different areas of the shared memory, and the identified control frame or data frame is written by the HDLC processing unit to the corresponding area of the shared memory.
  • the HDLC configuration management unit writes the control frame directly to the control frame transmission area of the shared memory, or reads the control frame from the control frame reception area of the shared memory.
  • the shared memory can be divided into a data sending area and a data receiving area, and different storage areas are no longer distinguished for the data frame and the control frame, but the data frame and the control frame to be sent are uniformly buffered in the data sending area, and the receiving will be received.
  • the data frame and the control frame are uniformly buffered in the data receiving area. As shown in FIG.
  • the HDLC configuration management unit distinguishes the data frame and the control frame, and reads the control frame detected in the data receiving area of the shared memory. And follow-up operations according to the corresponding control frame.
  • the HDLC configuration management unit directly writes the control frame to be sent to the data transmission area of the shared memory.
  • the processing flow of the HDLC channel bandwidth dynamic adjustment based on the device shown in FIG. 7 is basically the same as that of FIG. 6, except that the shared memory no longer divides the data frame transmission area, the data frame reception area, the control frame transmission area, and the control frame reception area.
  • the storage area is divided into two storage areas, a data transmission area and a data reception area, and the HDLC configuration management unit directly writes the corresponding control frame to the data of the shared memory.
  • the transmission area reads the corresponding control frame from the data receiving area of the shared memory.
  • FIG. 8 is a schematic structural diagram of an apparatus for dynamically adjusting bandwidth of an HDLC channel according to Embodiment 5 of the present invention.
  • the apparatus for dynamically adjusting bandwidth of an HDLC channel in this embodiment includes an HDLC configuration management unit, a service processing unit, and a shared Memory and HDLC processing unit.
  • the HDLC configuration management unit on the initiating end side is configured to modify the slot channel mapping configuration information in the receiving direction, send a channel adjustment initiation control frame to the service processing unit, and send the channel adjustment response according to the received channel from the service processing unit to the local end.
  • the time slot channel mapping configuration information of the direction is modified; the HDLC configuration management unit on the responding end side is configured to modify, according to the received channel adjustment initiation control frame from the service processing unit, the bidirectional channel channel mapping configuration information of the local end transceiver to be modified, to the service The processing unit sends a channel adjustment response.
  • the HDLC configuration management unit is further configured to configure an HDLC channel, and a mapping relationship between the HDLC channel and the physical layer time slot or the sub-time slot, and provide corresponding channel configuration information and time slot channel mapping configuration information to the HDLC processing unit.
  • the service processing unit is configured to write the received control frame from the HDLC configuration management unit to the shared memory, and send the received control frame from the shared memory to the HDLC configuration management unit.
  • the control frame includes a channel adjustment initiation control frame and a channel adjustment response.
  • the service processing unit distinguishes the data frame from the control frame, and can distinguish the control frame and the data frame by using the control word included in the frame, and the service processing unit sends the identified control frame to the HDLC configuration management unit.
  • the service processing unit is further configured to write the data frame to be sent into the shared memory, and read the received data frame buffered in the shared memory; further, the service processing unit may be configured to provide the received unit to other units in the telecommunication network element. Data frames to be processed by other units.
  • the HDLC processing unit on the initiating end side is configured to receive the HDLC data frame according to the slot channel mapping configuration information in the modified receiving direction, send the channel adjustment initiation control frame in the shared memory, and receive the channel adjustment response according to the modified sending direction.
  • the time slot channel mapping configuration information is sent to the HDLC data frame; the HDLC processing unit on the response end side is configured to write the received channel adjustment initiation control frame into the shared memory, and receive and transmit the HDLC according to the modified transmission and reception bidirectional time slot channel mapping configuration information.
  • Data frame sends the channel adjustment response in shared memory.
  • the HDLC configuration management unit on the initiating end is further configured to send a channel adjustment completion control frame to the service processing unit; the HDLC configuration management unit on the response end side is further configured to receive the service from the service The channel adjustment of the processing unit completes the control frame.
  • the HDLC processing unit on the initiating end is further configured to send a channel adjustment completion control frame in the shared memory; and the HDLC processing unit on the response end side is further configured to write the received channel adjustment completion control frame into the shared memory.
  • the apparatus further includes: a physical layer interface unit for forwarding the bit stream between the E1/T1 port and the HDLC processing unit.
  • FIG. 9 is a schematic structural diagram of an apparatus for dynamically adjusting bandwidth of an HDLC channel according to Embodiment 6 of the present invention.
  • the shared memory is divided into a data sending area and a data receiving area, and is no longer directed to data frames and
  • the control frame is divided into different storage areas, and only the data frame and the control frame to be sent are uniformly buffered in the data transmission area, and the received data frame and the control frame are uniformly buffered in the data receiving area.
  • the HDLC configuration management unit on the initiating end side is configured to modify the slot channel mapping configuration information in the receiving direction, and send a channel adjustment initiation control frame to the service processing unit, and adjust the response to the local sending direction according to the received channel from the service processing unit.
  • the time slot channel mapping configuration information is modified; the HDLC configuration management unit on the response end side is configured to modify the bidirectional channel channel mapping configuration information of the local end transceiver according to the received channel adjustment initiation control frame from the service processing unit, to the service processing unit.
  • the send channel adjusts the response.
  • the service processing unit is configured to write the received control frame from the HDLC configuration management unit to the data transmission area of the shared memory, read the control frame of the data receiving area of the shared memory, and send the control frame to the HDLC configuration management unit.
  • the HDLC processing unit includes a memory, a FIFO buffer control unit, a FIFO buffer, an HDLC protocol processing unit, and a slot channel mapping processing unit.
  • the FIFO buffer is divided into two areas: a transmission area for buffering a frame to be transmitted, and a reception area for buffering the received frame.
  • the FIFO buffer control unit is configured to receive, in the sending direction, the transmit area of the FIFO buffer according to the HDLC channel configuration table stored in the memory, to receive the frame to be sent from the shared memory data transmission area, and determine the data buffered in the transmit area of the FIFO buffer.
  • the HDLC protocol processing unit When the stream has been able to form a complete frame, the HDLC protocol processing unit is provided with the data stream constituting the complete frame; when the data stream buffered in the receiving area of the FIFO buffer is determined to be able to form a complete frame in the receiving direction, according to the memory storage
  • the HDLC channel configuration table controls the receive area of the FIFO buffer to output frames to the data receive area of the shared memory.
  • the frame may include a data frame, or a control frame, or data Frame and control frames.
  • the FIFO buffer control unit does not distinguish between the data frame and the control frame, but the service processing unit distinguishes the data frame and the control frame, and the service processing unit sends the identified control frame to the HDLC configuration management unit.
  • the data streams transmitted on the HDLC channels need to be separately processed. Therefore, when the FIFO buffer control unit controls the input and output of the FIFO buffer, it needs to be based on the HDLC channel. Configure the table to proceed.
  • the functions of the memory, the HDLC protocol processing unit, and the slot channel mapping processing unit are substantially the same as those described in FIG. 5, and details are not described herein again.
  • FIG. 10 is a flowchart of the dynamic adjustment of the bandwidth of the HDLC channel according to the seventh embodiment of the present invention. As shown in FIG. 10, in the embodiment, the process of dynamically adjusting the bandwidth of the HDLC channel includes the following steps:
  • Step A01 When the HDLC configuration management unit of the initiating end determines that the bandwidth adjustment of the HDLC channel needs to be performed, the receiving direction slot channel mapping configuration table of the local end is modified, and the channel adjustment initiation control frame is sent to the service processing unit, and the service processing unit receives the The channel adjustment initiates a control frame write to the data transmission area of the shared memory.
  • Step A02 The HDLC processing unit on the initiating end receives the HDLC frame according to the modified receiving direction slot channel mapping configuration table, and sends the HDLC frame according to the original sending direction slot channel mapping configuration table, and reads from the data sending area of the shared memory.
  • the channel adjustment initiates a control frame, and the channel control adjustment frame is processed by the HDLC protocol, and then the channel adjustment initiation control frame processed by the HDLC protocol is sent to the HDLC processing unit on the responding side.
  • Step A03 The HDLC processing unit on the responding end performs HDLC protocol processing on the received channel adjustment initiation control frame, and determines that the received data stream can form a complete frame, that is, the channel adjustment initiation control frame, and the channel adjustment initiation control frame is written. Enter the data receiving area of the shared memory.
  • the HDLC processing unit on the initiating end side and the HDLC processing unit on the responding end side read the data frame to be sent from the data transmission area of the shared memory, and the data frame to be sent is processed by the HDLC protocol, and is sent out; and the received data is received.
  • the frame performs HDLC protocol processing, and when it is determined that the received data stream can form a complete data frame, the data frame is written into the data receiving area of the shared memory.
  • Step A04 The service processing unit reads the channel adjustment initiation control frame from the data receiving area of the shared memory, determines that the read frame is a control frame, and sends a channel adjustment initiation control frame to the HDLC configuration management unit on the response end side, and the response end side
  • the HDLC configuration management unit modifies the bidirectional channel channel mapping configuration table of the local end transceiver according to the received channel adjustment initiation control frame, and then sends a channel adjustment response to the service processing unit, and the service processing unit writes the received channel adjustment response to the shared memory. Data transmission area.
  • Step A05 The HDLC processing unit on the response end receives and transmits the HDLC frame according to the modified bidirectional time slot channel mapping configuration table, and reads the channel adjustment response from the data transmission area of the shared memory, and performs HDLC protocol on the channel adjustment response. After processing, the channel adjustment response processed by the HDLC protocol is sent to the HDLC processing unit on the originating side.
  • Step A06 The HDLC processing unit on the initiating end performs HDLC protocol processing on the received channel adjustment response, and determines that the received data stream can form a complete frame, that is, the channel adjustment response, and the channel adjustment response is written into the shared memory. Area.
  • Step A07 The service processing unit reads the channel adjustment response from the data receiving area of the shared memory, determines that the read frame is a control frame, and sends a channel adjustment response to the HDLC configuration management unit at the originating end, and the HDLC configuration management of the initiating end side
  • the unit modifies the time slot channel mapping configuration table of the local receiving direction according to the received channel adjustment response, and then sends a channel adjustment completion control frame to the service processing unit, and the service processing unit writes the received channel adjustment completion control frame into the control frame of the shared memory. Sending area.
  • Step A08 The HDLC processing unit at the originating end receives and transmits the HDLC frame according to the modified bidirectional time slot channel mapping configuration table, and reads the channel adjustment completion control frame from the data sending area of the shared memory, and completes the control of the channel adjustment.
  • the frame is processed by the HDLC protocol, and then the channel adjustment completion control frame processed by the HDLC protocol is transmitted to the HDLC processing unit on the responding side.
  • Step A09 The HDLC processing unit on the responding end performs HDLC protocol processing on the received channel adjustment completion control frame, and determines that the received data stream can form a complete frame, that is, when the channel adjustment completes the control frame, and the channel adjustment completes the control frame write. Enter the data receiving area of the shared memory.
  • Step A10 The service processing unit reads the channel adjustment completion control from the data receiving area of the shared memory.
  • the frame is determined to be a control frame, and the channel adjustment completion control frame is sent to the HDLC configuration management unit on the response end side, and the HDLC configuration management unit on the response end side receives the channel adjustment completion control frame.
  • the initiator end and the response The end collaboration completes the dynamic adjustment of the bandwidth of the HDLC channel.
  • the two ends of the communication support not only the basic HDLC protocol, but also a variety of protocols derived from the HDLC protocol, for example, the Link Access Protocol (D channel), LAPD on the D channel.
  • D channel Link Access Protocol
  • LAPD on the D channel.
  • FR Frame Relay
  • MTP2 Message Transfer Part Level 2 of SS7
  • PPP Point-to-Point Protocol
  • LAPD When LAPD is supported at both ends of the communication, the frame format and processing of LAPD are basically the same as those of the basic HDLC protocol.
  • LAPD can be regarded as a special HDLC protocol.
  • the main difference between LAPD and basic HDLC protocol is: LAPD sets the length of the address information field in its frame format to 16 bits, and the address in the basic HDLC protocol frame format.
  • the information field is 8 bits in length, and the LAPD specifies the use of each bit in the address information field in its frame format.
  • LAPD as a special HDLC protocol, these subtle differences between the basic HDLC protocol and the basic HDLC protocol do not affect the implementation of the methods and apparatus provided in the embodiments of the present invention when applied to LAPD.
  • the frame format and processing of the FR protocol are basically the same as those of the basic HDLC protocol.
  • the FR protocol can be regarded as a special HDLC protocol.
  • the main difference between the FR protocol and the basic HDLC protocol is that the FR protocol uses a 16-bit field to describe address information and control information in its frame format.
  • the address information and control information in the HDLC protocol frame format are respectively described by a field of length 8 bits, and the FR protocol specifically specifies the use of each bit in the address and control information fields in its frame format.
  • the FR protocol as a special HDLC protocol, these subtle differences between the basic HDLC protocol and the basic HDLC protocol do not affect the implementation of the methods and apparatus provided in the embodiments of the present invention when applied to the FR protocol.
  • PPP When PPP is supported at both ends of the communication, the frame format and processing of PPP are basically the same as those of the basic HDLC protocol.
  • PPP can be regarded as a special HDLC protocol, PPP and basic HDLC protocol.
  • the main difference is that the address information field in the PPP frame format is fixedly filled with the hexadecimal number "FF," and the control information field is fixedly filled with the hexadecimal number "03”, and a PPP frame format is also specified.
  • the protocol information field is used to indicate the upper protocol type carried by the frame, and the protocol information field is not available in the basic HDLC protocol.
  • PPP is used as a special HDLC protocol and the basic HDLC protocol.
  • the solution provided in the embodiments of the present invention is applicable not only to the basic HDLC protocol but also to various other protocols derived from the HDLC protocol.
  • the HDLC processing unit on the initiating end receives the HDLC frame according to the modified slot direction channel mapping configuration information, and sends a channel adjustment notification;
  • the HDLC configuration management unit on the response end side obtains the The channel adjustment notification modifies the two-way time slot channel mapping configuration information of the local end transceiver, and the HDLC processing unit on the response end receives and transmits the HDLC frame according to the modified time slot channel mapping configuration information of the sending and receiving direction, and sends a channel adjustment response;
  • the HDLC configuration management unit of the end side modifies the slot channel mapping configuration information of the local end transmission direction according to the obtained channel adjustment response, and the HDLC processing unit of the originating end sends the HDLC frame according to the modified slot direction channel mapping configuration information in the sending direction.
  • the bandwidth of the HDLC channel When the bandwidth of the HDLC channel needs to be adjusted, it is initiated by one end, and the negotiation of the bandwidth adjustment of the HDLC channel is completed by the control frame interaction. It is not necessary to set a dedicated control link that occupies the time slot or sub-slot resources. Gap or sub-slot resources can be applied to In the transmission of the data stream, the utilization of the time slot or sub-slot resource is improved; and since the processing of the bandwidth adjustment of the HDLC channel is completed through negotiation between the two ends, the transmission of the data stream does not occur or is interrupted. In this case, the normal processing of the business is guaranteed to be unaffected.

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Abstract

L'invention porte sur une méthode et un dispositif d'ajustement dynamique de la largeur de bande d'un canal HDLC (à procédure de commande à haut niveau). L'unité de traitement du HDLC du côté initial reçoit une trame HDLC selon une information de collocation de mappage du créneau de temps dans les sens de la réception et envoie une notification d'ajustement du canal. L'unité de gestion de la collocation du HDLC du côté final répondant modifie l'information de collocation de mappage du créneau de temps bidirectionnelle de l'extrémité selon la notification d'ajustement du canal obtenue. L'unité de traitement HDLC du côté final répondant reçoitet transmet la trame HDLC selon l'information de collocation de mappage du créneau de temps dans les sens de la réception et de la transmission et envoie une réponse d'ajustement du canal. L'unité de gestion de la collocation du HDLC du côté initial d'introduction modifie l'information de collocation de mappage du créneau de temps dans le sens de la transmission vers l'extrémité selon la réponse de réglage du canal obtenue. L'unité de traitement HDLC du côté initial transmet la trame HDLC en fonction d'une information de collocation de mappage du créneau de temps dans les sens de la transmission et termine la négociation de l'ajustement de la largeur de bande du canal HDLC aux deux extrémités par interaction avec la trame de commande.
PCT/CN2008/000579 2007-04-12 2008-03-24 Méthode et dispositif d'ajustement dynamique de la largeur de bande d'un canal hdlc WO2008124998A1 (fr)

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