WO2008124760A3 - Mémoire non volatile et procédé et procédé de programmation prédictif - Google Patents

Mémoire non volatile et procédé et procédé de programmation prédictif Download PDF

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Publication number
WO2008124760A3
WO2008124760A3 PCT/US2008/059740 US2008059740W WO2008124760A3 WO 2008124760 A3 WO2008124760 A3 WO 2008124760A3 US 2008059740 W US2008059740 W US 2008059740W WO 2008124760 A3 WO2008124760 A3 WO 2008124760A3
Authority
WO
WIPO (PCT)
Prior art keywords
programming
threshold voltage
voltage level
memory cell
predetermined function
Prior art date
Application number
PCT/US2008/059740
Other languages
English (en)
Other versions
WO2008124760A2 (fr
Inventor
Raul-Adrian Cernea
Original Assignee
Sandisk Corp
Raul-Adrian Cernea
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/733,694 external-priority patent/US7643348B2/en
Priority claimed from US11/733,706 external-priority patent/US7551483B2/en
Application filed by Sandisk Corp, Raul-Adrian Cernea filed Critical Sandisk Corp
Priority to CN2008800195746A priority Critical patent/CN101711414B/zh
Priority to EP08745369A priority patent/EP2135252A2/fr
Priority to JP2010503176A priority patent/JP2010524147A/ja
Publication of WO2008124760A2 publication Critical patent/WO2008124760A2/fr
Publication of WO2008124760A3 publication Critical patent/WO2008124760A3/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

L'invention concerne une mémoire non volatile ayant un ensemble de cellules de mémoire, les cellules de mémoire étant programmables individuellement sur un niveau d'une plage de niveaux de tension de seuil. Cette mémoire non volatile comprend un mode de programmation prédictif dans lequel une fonction prédéterminée prédit quel niveau de tension de programmation doit être appliqué afin de programmer une cellule de mémoire donnée à un niveau de tension de seuil cible donné. De cette façon, aucune opération de vérification n'a besoin d'être effectuée, améliorant ainsi considérablement la performance de l'opération de programmation. Dans un mode de réalisation préféré, la fonction prédéterminée est linéaire et est étalonnée pour chaque cellule de mémoire lors de la programmation par un ou plusieurs points de contrôle. Le point de contrôle est une tension de programmation réelle qui programme la cellule de mémoire en question à un niveau de tension de seuil désigné vérifié.
PCT/US2008/059740 2007-04-10 2008-04-09 Mémoire non volatile et procédé et procédé de programmation prédictif WO2008124760A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2008800195746A CN101711414B (zh) 2007-04-10 2008-04-09 非易失性存储器和用于预测编程的方法
EP08745369A EP2135252A2 (fr) 2007-04-10 2008-04-09 Mémoire non volatile et procédé et procédé de programmation prédictif
JP2010503176A JP2010524147A (ja) 2007-04-10 2008-04-09 不揮発性メモリと予測プログラミングの方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/733,694 US7643348B2 (en) 2007-04-10 2007-04-10 Predictive programming in non-volatile memory
US11/733,706 2007-04-10
US11/733,694 2007-04-10
US11/733,706 US7551483B2 (en) 2007-04-10 2007-04-10 Non-volatile memory with predictive programming

Publications (2)

Publication Number Publication Date
WO2008124760A2 WO2008124760A2 (fr) 2008-10-16
WO2008124760A3 true WO2008124760A3 (fr) 2008-11-27

Family

ID=39712596

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/059740 WO2008124760A2 (fr) 2007-04-10 2008-04-09 Mémoire non volatile et procédé et procédé de programmation prédictif

Country Status (6)

Country Link
EP (1) EP2135252A2 (fr)
JP (1) JP2010524147A (fr)
KR (1) KR20100028019A (fr)
CN (1) CN101711414B (fr)
TW (1) TWI371041B (fr)
WO (1) WO2008124760A2 (fr)

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Also Published As

Publication number Publication date
CN101711414B (zh) 2013-06-26
TWI371041B (en) 2012-08-21
CN101711414A (zh) 2010-05-19
WO2008124760A2 (fr) 2008-10-16
EP2135252A2 (fr) 2009-12-23
KR20100028019A (ko) 2010-03-11
TW200907975A (en) 2009-02-16
JP2010524147A (ja) 2010-07-15

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