WO2008114397A1 - 半導体集積回路の設計方法およびその設計装置 - Google Patents

半導体集積回路の設計方法およびその設計装置 Download PDF

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Publication number
WO2008114397A1
WO2008114397A1 PCT/JP2007/055566 JP2007055566W WO2008114397A1 WO 2008114397 A1 WO2008114397 A1 WO 2008114397A1 JP 2007055566 W JP2007055566 W JP 2007055566W WO 2008114397 A1 WO2008114397 A1 WO 2008114397A1
Authority
WO
WIPO (PCT)
Prior art keywords
capacitance
resistance
wiring
worst
design
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/055566
Other languages
English (en)
French (fr)
Inventor
Kenichi Ushiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Priority to JP2009504997A priority Critical patent/JP4717944B2/ja
Priority to PCT/JP2007/055566 priority patent/WO2008114397A1/ja
Publication of WO2008114397A1 publication Critical patent/WO2008114397A1/ja
Priority to US12/461,585 priority patent/US20090313593A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

　チップサイズやコストの増加などを防ぐことができる。 　複数の配線層に対して配線した（Ｓ１１～Ｓ１６）配線レイアウトに応じた容量および抵抗が容量抵抗ファイルとして抽出され（Ｓ１７）、容量抵抗ファイルと、複数の配線層ごとの容量および抵抗に関するばらつきのベストおよびワースト条件の係数が格納されたベストワースト係数ファイルとを参照して、配線に対する配線層ごとのばらつきを考慮した容量および抵抗を定義するベストワースト容量抵抗ファイルが生成され（Ｓ１８）、ベストワースト容量抵抗ファイルに基づいて、配線のタイミング検証が行われる（Ｓ１９）。
PCT/JP2007/055566 2007-03-19 2007-03-19 半導体集積回路の設計方法およびその設計装置 Ceased WO2008114397A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009504997A JP4717944B2 (ja) 2007-03-19 2007-03-19 半導体集積回路の設計方法およびその設計装置
PCT/JP2007/055566 WO2008114397A1 (ja) 2007-03-19 2007-03-19 半導体集積回路の設計方法およびその設計装置
US12/461,585 US20090313593A1 (en) 2007-03-19 2009-08-17 Semiconductor integrated circuit design method and semiconductor integrated circuit design apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/055566 WO2008114397A1 (ja) 2007-03-19 2007-03-19 半導体集積回路の設計方法およびその設計装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/461,585 Continuation US20090313593A1 (en) 2007-03-19 2009-08-17 Semiconductor integrated circuit design method and semiconductor integrated circuit design apparatus

Publications (1)

Publication Number Publication Date
WO2008114397A1 true WO2008114397A1 (ja) 2008-09-25

Family

ID=39765519

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/055566 Ceased WO2008114397A1 (ja) 2007-03-19 2007-03-19 半導体集積回路の設計方法およびその設計装置

Country Status (3)

Country Link
US (1) US20090313593A1 (ja)
JP (1) JP4717944B2 (ja)
WO (1) WO2008114397A1 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10372869B2 (en) 2015-03-27 2019-08-06 Samsung Electronics Co., Ltd. System and method of analyzing integrated circuit in consideration of a process variation
US11256846B2 (en) 2015-03-27 2022-02-22 Samsung Electronics Co., Ltd. System and method of analyzing integrated circuit in consideration of a process variation and a shift

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004253655A (ja) * 2003-02-20 2004-09-09 Fujitsu Ltd タイミング検証方法及びタイミング検証プログラム
JP2004362202A (ja) * 2003-06-04 2004-12-24 Matsushita Electric Ind Co Ltd タイミング検証方法
JP2006338253A (ja) * 2005-06-01 2006-12-14 Matsushita Electric Ind Co Ltd タイミング検証方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3615191B2 (ja) * 2002-03-04 2005-01-26 株式会社東芝 半導体集積回路装置の設計方法、設計装置、及び設計プログラム
US7526743B2 (en) * 2004-07-23 2009-04-28 International Business Machines Corporation Method for routing data paths in a semiconductor chip with a plurality of layers

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004253655A (ja) * 2003-02-20 2004-09-09 Fujitsu Ltd タイミング検証方法及びタイミング検証プログラム
JP2004362202A (ja) * 2003-06-04 2004-12-24 Matsushita Electric Ind Co Ltd タイミング検証方法
JP2006338253A (ja) * 2005-06-01 2006-12-14 Matsushita Electric Ind Co Ltd タイミング検証方法

Also Published As

Publication number Publication date
JPWO2008114397A1 (ja) 2010-07-01
JP4717944B2 (ja) 2011-07-06
US20090313593A1 (en) 2009-12-17

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