WO2008103699A1 - Dispositif à semi-conducteurs ayant un contact de composite et procédé de fabrication de celui-ci - Google Patents

Dispositif à semi-conducteurs ayant un contact de composite et procédé de fabrication de celui-ci Download PDF

Info

Publication number
WO2008103699A1
WO2008103699A1 PCT/US2008/054368 US2008054368W WO2008103699A1 WO 2008103699 A1 WO2008103699 A1 WO 2008103699A1 US 2008054368 W US2008054368 W US 2008054368W WO 2008103699 A1 WO2008103699 A1 WO 2008103699A1
Authority
WO
WIPO (PCT)
Prior art keywords
contact
electrode
forming
conducting
semiconductor
Prior art date
Application number
PCT/US2008/054368
Other languages
English (en)
Inventor
Grigory Simin
Michael Shur
Remigijus Gaska
Original Assignee
Sensor Electronic Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/781,302 external-priority patent/US8461631B2/en
Application filed by Sensor Electronic Technology, Inc. filed Critical Sensor Electronic Technology, Inc.
Publication of WO2008103699A1 publication Critical patent/WO2008103699A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H01L27/0811—MIS diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42304—Base electrodes for bipolar transistors

Definitions

  • aspects of the disclosure relate generally to contacts for semiconductor devices, and more particularly, to semiconductor devices/structures that include a composite contact and methods of fabricating such devices/structures.
  • FIGS. 1A-B show a structure 2 and equivalent circuit 6, respectively, of a typical annealed metal (e.g., Ohmic) contact 4 according to the prior art.
  • contact 4 comprises a contact to a heterostructure with a two-dimensional (2D) electron gas at the heterointerface.
  • the equivalent circuit 6 consists of resistive components. Therefore, the resistance of contact 4 is frequency independent.
  • the resistance of contact 4 is a dominant factor in limiting the performance of the device.
  • a low contact resistance can be obtained by using high-temperature annealing in the contact formation.
  • Such annealing remains a challenging technology, especially for wide bandgap semiconductor materials.
  • the material bandgap increases, the required contact annealing temperature increases, yet the contact resistance also increases.
  • contact formation becomes even more challenging with novel emerging wide bandgap material systems and devices, such as material systems/devices based on aluminum nitride (AIN), diamond, and others.
  • Au/Ge/Ni/Au contacts to gallium arsenide (GaAs) or indium GaAs (InGaAs) require an annealing temperature in the range of 350-425 degrees Celsius and produce unit-width contact resistances as low as 0.1 ⁇ -mm or even lower.
  • gallium nitride (GaN) contact formation using Ti/AI contacts requires an annealing temperature in the range of 800-850 degrees Celsius with typical unit-width contact resistances in the range of 0.5-1.0 ⁇ -mm. While advanced annealing techniques have been shown to yield lower unit-width contact resistances, the general trend in which high annealing temperatures lead to significant morphology degradation, defect generation, and contact edge roughness remains.
  • FIGS. 2A-B show another structure 3 and equivalent circuit 7, respectively, of an alternative metal contact 5 according to the prior art.
  • metal contact 5 comprises a conventional, under annealed contact, in which there is a capacitive coupling between the metal and the underlying two-dimensional electron gas.
  • the capacitive coupling has been shown to reduce the access resistance to the two-dimensional electron gas at high frequencies (e.g., radio frequencies).
  • the composite contact includes a direct current (DC) conducting electrode that is attached to a semiconductor layer in the device, and a capacitive electrode that is partially over the DC conducting electrode and extends beyond the DC conducting electrode.
  • the composite contact provides a combined resistive-capacitive coupling to the semiconductor layer. As a result, a contact impedance is reduced when the corresponding semiconductor device is operated at high frequencies.
  • a first aspect of the invention provides a semiconductor structure comprising: a semiconductor layer; and a composite contact to the semiconductor layer, the composite contact including: a DC conducting electrode attached to the semiconductor layer; and a capacitive electrode, the capacitive electrode partially over the DC conducting electrode and extending beyond the DC conducting electrode.
  • a second aspect of the invention provides a semiconductor device comprising: a semiconductor layer; a device conducting channel; and a composite contact to the semiconductor layer, the composite contact including: a DC conducting electrode attached to the semiconductor layer; and a capacitive electrode, the capacitive electrode partially over the DC conducting electrode and extending beyond the DC conducting electrode.
  • a third aspect of the invention provides a semiconductor device comprising: a semiconductor layer; a barrier layer over the semiconductor layer; an insulating layer over the barrier layer; and a composite contact to the semiconductor layer, the composite contact including: a DC conducting electrode attached to the semiconductor layer; and a capacitive electrode, the capacitive electrode partially over the DC conducting electrode and extending beyond the DC conducting electrode.
  • a fourth aspect of the invention provides a circuit comprising: at least one semiconductor device, the at least one semiconductor device including: a semiconductor layer; a barrier layer over the semiconductor layer; an insulating layer over the barrier layer; and a composite contact to the semiconductor layer, the composite contact including: a DC conducting electrode attached to the semiconductor layer; and a capacitive electrode, the capacitive electrode partially over the DC conducting electrode and extending beyond the DC conducting electrode.
  • Additional aspects of the invention provide a method of fabricating a semiconductor device with a composite contact.
  • the fabrication includes forming the composite contact to a semiconductor layer in a semiconductor structure.
  • the composite contact is formed by forming a direct current (DC) conducting electrode attached to a semiconductor layer in a semiconductor structure and forming a capacitive electrode that is partially over the DC conducting electrode and extends beyond the DC conducting electrode.
  • the composite contact provides a combined resistive-capacitive coupling to the semiconductor layer. As a result, a contact impedance is reduced when the corresponding semiconductor device is operated at high frequencies.
  • a fifth aspect of the invention provides a method of fabricating a semiconductor device, the method comprising: obtaining a semiconductor structure comprising a semiconductor layer; forming a contact to the semiconductor layer, the contact forming including: forming a DC conducting electrode attached to the semiconductor layer; and forming a capacitive electrode, the capacitive electrode partially over the DC conducting electrode and extending beyond the DC conducting electrode.
  • a sixth aspect of the invention provides a method of fabricating a semiconductor device, the method comprising: obtaining a semiconductor structure comprising a semiconductor layer; forming a first contact to the semiconductor layer, the first contact forming including: forming a DC conducting electrode attached to the semiconductor layer; and forming a capacitive electrode, the capacitive electrode partially over the DC conducting electrode and extending beyond the DC conducting electrode; and forming a second contact, wherein the second contact forming and capacitive electrode forming are performed simultaneously.
  • a seventh aspect of the invention provides a method of fabricating a field effect transistor, the method comprising: obtaining a group Ill-Nitride based heterostructure comprising a device conducting channel; forming a drain contact to the device conducting channel, the drain contact forming including: forming a DC conducting electrode attached to the device conducting channel; and forming a capacitive electrode, the capacitive electrode partially over the DC conducting electrode and extending beyond the DC conducting electrode.
  • An eighth aspect of the invention provides a method of fabricating a circuit, the method comprising: fabricating a semiconductor device, the semiconductor device fabricating including: obtaining a semiconductor structure comprising a semiconductor layer; forming a contact to the semiconductor layer, the contact forming including: forming a DC conducting electrode attached to the semiconductor layer; and forming a capacitive electrode, the capacitive electrode partially over the DC conducting electrode and extending beyond the DC conducting electrode; and incorporating the semiconductor device in the circuit.
  • FIGS. 1A-B show a structure and equivalent circuit, respectively, of a typical annealed metal contact according to the prior art.
  • FIGS. 2A-B show another structure and equivalent circuit, respectively, of an alternative metal contact according to the prior art.
  • FIGS. 3A-B show an illustrative semiconductor structure and equivalent circuit, respectively, according to an embodiment.
  • FIG. 4 shows an illustrative semiconductor structure that comprises a heterostructure according to an embodiment.
  • FIG. 5 shows an illustrative semiconductor structure in which a dielectric layer is included between a semiconductor and a capacitive electrode according to an embodiment.
  • FIG. 6 shows an illustrative semiconductor structure in which a dielectric layer is included under all of a capacitive electrode according to an embodiment.
  • FIG. 7 shows an illustrative diode according to an embodiment.
  • FIG. 8 shows an illustrative field effect transistor according to an embodiment.
  • FIG. 9 shows another illustrative field effect transistor according to an embodiment.
  • FIG. 10 shows an illustrative bipolar junction transistor according to an embodiment.
  • FIG. 11 shows a simulated frequency dependence of a composite contact formed on an AIGaN/GaN heterostructure according to an embodiment.
  • FIG. 12 shows a simulated maximum oscillation frequency for a composite contact and a regular ohmic contact, each of which was formed on an AIGaN/GaN heterostructure field effect transistor according to an embodiment.
  • FIGS. 13A-D show illustrative steps of forming a composite contact according to embodiments.
  • FIGS. 14A-B show the formation of multiple contacts on a semiconductor structure according to an embodiment.
  • FIGS. 15A-B show illustrative steps of fabricating a field effect transistor according to embodiments.
  • aspects of the invention provide a composite contact for a semiconductor device.
  • the composite contact includes a DC conducting electrode that is attached to a semiconductor layer in the device, and a capacitive electrode that is partially over the DC conducting electrode and extends beyond the DC conducting electrode.
  • the composite contact provides a combined resistive-capacitive coupling to the semiconductor layer. As a result, a contact impedance is reduced when the corresponding semiconductor device is operated at high frequencies.
  • the term “set” means one or more (i.e., at least one) and the phrase "any solution” means any now known or later developed solution.
  • FIGS. 3A-B show an illustrative semiconductor structure 10 and equivalent circuit 20, respectively, according to an embodiment.
  • Structure 10 includes a semiconductor 12, which includes at least one semiconductor layer, and a metal to semiconductor composite contact 14 to a semiconductor layer in semiconductor 12.
  • Contact 14 comprises a composite contact that includes separate conductive and capacitive coupling regions.
  • contact 14 includes a DC conducting electrode 14A and a capacitive electrode 14B.
  • DC conducting electrode 14A can be attached to the semiconductor layer.
  • DC conducting electrode 14A can comprise an Ohmic or Schottky contact, which is melted into semiconductor 12 above the semiconductor layer, and may or may not be physically contacting the semiconductor layer.
  • Capacitive electrode 14B is formed such that it is partially over DC conducting electrode 14A and extends beyond DC conducting electrode 14A above a surface of semiconductor 12 in a direction that is substantially parallel to the semiconductor layer.
  • capacitive electrode 14B includes a first section that is over all or substantially all of DC conducting electrode 14A and a second section that extends beyond the area of DC conducting electrode 14A. In this manner, capacitive electrode 14B forms an additional capacitively coupled contact with the semiconductor layer.
  • Each electrode 14A, 14B can comprise any material, such as for example, titanium, aluminum, nickel, gold, and/or the like. While capacitive electrode 14B is shown only extending beyond DC conducting electrode 14A in a single direction, it is understood that capacitive electrode 14B can extend beyond DC conducting electrode 14A in any number of directions.
  • contact 14 provides both resistive and capacitive coupling between contact 14 and the semiconductor layer.
  • semiconductor 12 can include a barrier layer between capacitive electrode 14B and the semiconductor layer.
  • DC conducting electrode 14A provides resistive coupling 22A to the semiconductor layer
  • capacitive electrode 14B provides capacitive coupling 22B to the semiconductor layer with capacitive electrode 14B and the semiconductor layer each serving as a plate of the capacitive contact and the barrier layer separating the two plates.
  • contact 14 reduces contact impedance at high frequencies, e.g., contact 14 comprises a radio-frequency enhanced (RFE) contact.
  • the capacitive plate length can vary along a width of contact 14.
  • the semiconductor layer can comprise any type of semiconductor layer, such as a device conducting channel.
  • the device conducting channel can comprise any type of device conducting channel such as a two-dimensional gas (e.g., electron or hole), a doped (n- type or p-type) semiconductor material, an inversion layer (n-type or p-type), and/or the like.
  • a two-dimensional gas e.g., electron or hole
  • a doped (n- type or p-type) semiconductor material e.g., silicon dioxide
  • an inversion layer n-type or p-type
  • FIG. 4 shows an illustrative semiconductor structure 30 that comprises a heterostructure according to an embodiment.
  • Structure 30 can comprise, for example, a group Ill-Nitride based heterostructure such as an aluminum gallium nitride/gallium nitride (AIGaN/GaN) heterostructure.
  • Structure 30 includes a buffer layer 32, a device conducting channel 34 (e.g., a two-dimensional (2D) electron gas), and a barrier layer 36. It is understood that structure 30 could include one or more additional layers, which are not shown for clarity.
  • Contact 14 includes a DC conducting electrode 14A, which is attached to device conducting channel 34, and a capacitive electrode 14B, which extends beyond DC conducting electrode 14A by a length, L ⁇ xt .
  • Barrier layer 36 separates capacitive electrode 14B from device conducting channel 34.
  • Barrier layer 36 can comprise a semiconductor, dielectric or some combination thereof (e.g., a composite dielectric-semiconductor layer).
  • barrier layer 36 comprises a semiconductor.
  • barrier layer 36 can comprise a semiconductor having an energy gap that is wider than an energy gap of device conducting channel 34.
  • barrier layer 36 can comprise a wide bandgap material (e.g., highly resistive AIGaN) layer.
  • a semiconductor barrier layer 36 can include a depletion region formed by a Schottky contact, such as DC conducting electrode 14A, between capacitive electrode 14B and the semiconductor layer (e.g., device conducting channel 34).
  • a semiconductor barrier layer 36 can incorporate a p-n junction structure that forms a depletion region.
  • structure 30 can be implemented as part of a high frequency semiconductor device.
  • a radio frequency (RF) signal can inject from capacitive electrode 14B into the active region (e.g., device conducting channel 34) via a strong capacitive coupling that effectively shunts barrier layer 36.
  • the vertical current component is capacitive and the lateral current component passes through a low- resistive device conducting channel 34 (e.g., 2D electron gas channel), which results in a low overall contact impedance.
  • Capacitive electrode 14B and device conducting channel 34 form an RC transmission line as illustrated in FIG. 3B.
  • barrier layer 36 comprises a highly resistive AIGaN layer and device conducting channel 34 comprises a 2D electron gas channel, a propagation constant, ⁇ , and the characteristic impedance, Z 0 , of the RC
  • R SH is the sheet resistance of 2D electron gas channel 34
  • C ⁇ is the metal-channel capacitance per unit area
  • W is the electrode width
  • i the imaginary unit.
  • the expressions for the metal-semiconductor unit-area capacitance, C 1 , and the layer sheet resistance, R SH must be chosen according to the semiconductor layer structure and the interface properties of capacitive electrode 14B and device conducting channel 34.
  • an equivalent impedance of contact 14, Z 1n can be found as an input impedance of the
  • capacitive electrode 14B can be formed directly on DC conducting electrode 14A and semiconductor 12 (e.g., barrier layer 36). However, it is understood that one or more layers may be included between capacitive electrode 14B and DC conducting electrode 14A and/or semiconductor 12. For example, an insulating barrier (e.g., dielectric) layer can be included under some or all of capacitive electrode 14B. Inclusion of the insulating barrier layer can improve a quality of contact 14, enable additional functionality, and/or the like.
  • insulating barrier e.g., dielectric
  • FIG. 5 shows an illustrative semiconductor structure 40 in which a dielectric layer 42 is included between semiconductor 12 and capacitive electrode 14B according to an embodiment.
  • Dielectric layer 42 can be used to adjust an amount of the capacitive coupling provided by capacitive electrode 14B using any solution.
  • a thickness, type of material, and/or the like of dielectric layer 42 can be selected based on semiconductor 12 and the interface properties of capacitive electrode 14B and a device conducting channel in semiconductor 12 using any solution.
  • dielectric layer 42 can comprise any type of insulating material, such as for example, silicon dioxide, silicon nitride, aluminum oxide, and/or the like.
  • FIG. 6 shows an illustrative semiconductor structure 44 in which a dielectric layer 46 is included under all of capacitive electrode 14B according to an embodiment.
  • dielectric layer 46 can be included between both DC conducting electrode 14A and capacitive electrode 14B and between semiconductor 12 and capacitive electrode 14B.
  • Dielectric layer 46 can comprise any type of a thin insulating layer, such as for example, silicon dioxide, silicon nitride, aluminum oxide, and/or the like.
  • dielectric layer 46 insulates capacitive electrode 14B from DC conducting electrode 14A and semiconductor 12.
  • an additional DC or RF voltage can be applied to capacitive electrode 14B to modulate the conductivity of the semiconductor layer (e.g., device conducting channel) in semiconductor 12.
  • FIG. 7 shows an illustrative diode 50 (e.g., a Schottky diode, lateral p-n junction diode, light emitting diode, and/or the like) according to an embodiment.
  • Diode 50 includes two contacts 52A-B, each of which comprises an embodiment of the composite contact described herein. However, it is understood that only one contact for diode 50 may be implemented using a composite contact.
  • the overhanging portions of contacts 52A-B can extend in a direction of the current flow, e.g., toward the other contact 52A-B. In alternative embodiments, the overhanging portions can extend away from the other contact and/or both away from and towards the other contact.
  • FIGS. 8 and 9 show illustrative field effect transistors 54, 60, respectively, according to embodiments.
  • Each field effect transistor 54, 60 includes a source contact 56A, 62A and a drain contact 56B, 62B, respectively, which are each implemented using an embodiment of the composite contact described herein.
  • source contact 56A, 62A or drain contact 56B, 62B can be implemented using a composite contact.
  • the overhanging portion of a contact 56A-B, 62A-B can extend in a direction that the current may flow, e.g., toward a gate 58, 64 of the corresponding field effect transistor 54, 60.
  • field effect transistor 54 can include a separation distance between the capacitive electrode for drain contact 56B and gate 58 (e.g., field- controlling gap) that ensures a trapezoidal field distribution in a gate-to-drain region of field effect transistor 54.
  • field effect transistor 60 includes a set of field plates 66A-B over gate 64. Each field plate 66A-B is shown extending in a direction toward drain contact 62B.
  • field effect transistor 60 can include a separation distance between the capacitive electrode for drain contact 62B and the field plate closest to drain contact 62B, field plate 66B, (e.g., field-controlling gap) that ensures a trapezoidal field distribution in a spacing between field plates 66A-B and drain contact 62B.
  • the separation distance can be estimated as a drain-source bias divided by a characteristic field ranging between 0.1 MV/cm and 10 MV/cm.
  • the characteristic field can be determined based on the material properties and device structure of field effect transistor 60 using any solution.
  • FIG. 10 shows an illustrative bipolar junction transistor 70 according to an embodiment.
  • Bipolar junction transistor 70 is shown including an emitter 72A, a base 72B, and a collector 72C, each of which is implemented using an embodiment of the composite contact described herein. As illustrated, the overhanging portion of collector 72C extends in a direction toward base 72B.
  • emitter 72A and base 72B each include overhanging portions on both sides of the DC conducting electrode.
  • Base 72B can include the overhanging portions on both sides of the DC conducting electrode since current can flow in both directions.
  • any of the composite contacts may include one or more additional layers (e.g., a dielectric layer there between).
  • the structures described herein can be incorporated as part of various additional types of semiconductor devices, including a laser, a photodetector, and/or the like. Additionally, devices made using a structure described herein can be incorporated in various types of circuits and applications, including a radio frequency circuit, a microwave amplifier, an oscillator, a switcher, an optoelectronic circuit, and/or the like.
  • a device can undergo additional processing, such as the formation of one or more additional layers.
  • additional processing such as the formation of one or more additional layers.
  • operation of a high-power semiconductor device may be limited by premature breakdown, which can be caused by a high voltage jumping through the air or another medium adjacent to the contact regions and the spacing between the contacts (e.g., surface flashover).
  • the device can include additional layer(s) to prevent or reduce the likelihood of premature breakdown.
  • FIG. 8 shows an encapsulating layer 80 on field effect transistor 54.
  • Encapsulating layer 80 can comprise a high dielectric strength insulating material that increases a breakdown voltage of transistor 54, thereby helping to prevent a premature breakdown of transistor 54.
  • the material can have a high breakdown field that well exceeds that of air and is close to that of the material constituting transistor 54.
  • Illustrative examples of materials for encapsulating layer 80 include silicon dioxide, silicon nitride, bisbenzocyclobutene, and/or the like. While encapsulating layer 80 is shown in conjunction with field effect transistor 54, it is understood that encapsulating layer 80 can be included on any type of semiconductor device.
  • the composite contact described herein provides a combined resistive- capacitive coupling to a semiconductor layer. As a result, a contact impedance is reduced when a corresponding high frequency semiconductor device is operated at high frequencies. To this extent, FIG.
  • 1 1 shows a simulated frequency dependence of a composite contact formed on an AIGaN/GaN heterostructure according to an embodiment.
  • a contact resistance of the ohmic part, pc, of 1 ⁇ -mm and a two degree electron gas sheet resistance of 300 ⁇ were used.
  • a barrier layer thickness was approximately 200 Angstroms with a dielectric permittivity ⁇ ⁇ 9.
  • much lower contact impedances can be achieved at microwave frequencies as compared to the DC due to the additional capacitive coupling of the composite contact.
  • FIG. 12 shows a simulated maximum oscillation frequency for a composite contact and a regular ohmic contact, each of which was formed on an AIGaN/GaN heterostructure field effect transistor according to an embodiment.
  • the capacitive electrode of the composite contact extended beyond the DC conducting electrode by 0.2 ⁇ m (L ⁇ xt ), while the other parameters used in the simulations were the same as described above with respect to FIG. 1 1.
  • the simulated maximum oscillation frequencies for the respective contacts are shown as a function of DC contact resistance.
  • a significant performance improvement can be obtained for a microwave device with the composite contact as compared to a microwave device with a regular ohmic contact.
  • the additional capacitive coupling can make the maximum oscillation frequency, f MA x, largely insensitive to the DC contact resistance, Rc, while the ohmic contact has significant degradation of the maximum oscillation frequency due to the DC contact resistance.
  • a composite contact can be formed by depositing and annealing a metal (e.g., Ohmic) contact to a semiconductor layer. During formation of the metal contact, a high annealing temperature may not be required since achieving a low DC contact resistance may not be essential. Alternatively, the metal contact may be formed without annealing, thereby forming a Schottky contact. Subsequently, a capacitive electrode having a portion over the DC conducting electrode and a portion extending beyond the DC conducting electrode can be formed (e.g., deposited). Formation of the capacitive electrode can be combined with additional processing, such as the formation of a gate or another electrode for the structure/device, thereby allowing for an alignment-free formation process and/or tight spacing.
  • a metal e.g., Ohmic
  • additional aspects of the invention provide a method of fabricating a semiconductor device with a composite contact.
  • the fabrication includes forming the composite contact to a semiconductor layer in a semiconductor structure.
  • the composite contact is formed by forming a direct current (DC) conducting electrode attached to a semiconductor layer in a semiconductor structure and forming a capacitive electrode that is partially over the DC conducting electrode and extends beyond the DC conducting electrode.
  • the composite contact provides a combined resistive-capacitive coupling to the semiconductor layer. As a result, a contact impedance is reduced when the corresponding semiconductor device is operated at high frequencies.
  • FIGS. 13A-D show illustrative steps of forming a composite contact according to embodiments.
  • a semiconductor structure 12 is obtained.
  • Semiconductor structure 12 can comprise any type of semiconductor structure.
  • semiconductor structure 12 can be fabricated from silicon (Si), group IN-V compounds, group M-Vl compounds, silicon carbide (SiC), group III nitride compounds, ternary and/or quaternary alloys of these compounds, and/or the like.
  • Semiconductor structure 12 can be obtained as a pre-fabricated structure and/or can be partially or entirely fabricated using any solution.
  • a compound contact 14 is formed to a semiconductor layer in semiconductor structure 12.
  • the semiconductor layer can comprise any type of semiconductor layer, such as a device conducting channel.
  • the device conducting channel can comprise any type of device conducting channel such as a two- dimensional gas (e.g., electron or hole), a doped (n-type or p-type) semiconductor material, an inversion layer (n-type or p-type), and/or the like.
  • a DC conducting electrode (contact) 14A attached to a semiconductor layer in semiconductor structure 12 is formed using any solution.
  • DC conducting electrode 14A can be an Ohmic contact, which is formed by depositing a metal and annealing.
  • DC conducting electrode 14A is deposited above the semiconductor layer, and may or may not be physically contacting the semiconductor layer. During formation of the Ohmic contact, a high annealing temperature may not be required since achieving a low DC contact resistance may not be essential.
  • DC conducting electrode 14A can comprise a Schottky contact, which can be formed by depositing a metal, but without requiring annealing.
  • DC conducting electrode 14A can comprise any material, which can be selected based on its properties when interacting with semiconductor structure 12. For example, when semiconductor structure 12 comprises a GaAs or InGaAs-based material, DC conducting electrode 14A can comprise Au/Ge/Ni/Au. However, when semiconductor structure 12 comprises GaN-based material, DC conducting electrode 14A can comprise Ti/AI.
  • a capacitive electrode (contact) 14B is formed such that a first portion of capacitive electrode 14B is directly on DC conducting electrode 14A and a second portion of capacitive electrode 14B extends beyond DC conducting electrode 14A and is directly on semiconductor structure 12. In this manner, capacitive electrode 14B forms an additional capacitively coupled contact with the semiconductor layer.
  • Each electrode 14A, 14B can comprise any material, such as for example, titanium, aluminum, nickel, gold, and/or the like.
  • contact impedance is reduced, e.g., contact 14 comprises a radio- frequency enhanced (RFE) contact.
  • RFE radio- frequency enhanced
  • capacitive electrode 14B may not be formed directly on DC conducting electrode 14A and/or semiconductor structure 12.
  • a barrier layer 42 e.g., dielectric
  • FIG. 13C a barrier layer 42 (e.g., dielectric) is formed on semiconductor structure 12, adjacent to DC conducting electrode 14A.
  • capacitive electrode 14B is formed directly on DC conducting electrode 14A and barrier layer 42 (e.g., dielectric). In this manner, barrier layer 42 further separates the overhanging portion of capacitive electrode 14B from the semiconductor layer in semiconductor structure 12.
  • a barrier layer 46 (e.g., dielectric) is formed on DC conducting electrode 14A and semiconductor structure 12.
  • capacitive electrode 14B is formed directly on barrier layer 46 (e.g., dielectric), such that a first portion of capacitive electrode 14B is on a portion of barrier layer 46 that is over DC conducting electrode 14A and a second portion of capacitive electrode 14B is on a portion of barrier layer 46 that extends beyond DC conducting electrode 14A.
  • barrier layer 46 insulates capacitive electrode 14B from both DC conducting electrode 14A and the semiconductor layer in semiconductor structure 12.
  • barrier layer 42 (FIG. 13C) or barrier layer 46 (FIG. 13D) can comprise any type of insulating material, such as a dielectric, a passivation layer, a metal-insulator structure, a wide band gap semiconductor layer, and/or a combination thereof (e.g., a composite dielectric layer).
  • barrier layers 42, 46 can comprise any material having an energy bandgap that is larger than an energy bandgap of the underlying semiconductor structure 12, and a conductivity that is smaller than a conductivity of the underlying semiconductor structure 12.
  • barrier layer 42, 46 can comprise silicon dioxide (SiU 2 ), silicon nitride (SiN, Si 3 N 4 ), silicon oxynithde (SiON), aluminum nitride (AIN), aluminum gallium nitride (AIGaN), aluminum indium gallium nitride (AIInGaN), gallium nitride (GaN), aluminum oxide (AI 2 O3), hafnium oxide (HfO), strontium titanate (SrTiO 3 ), lanthunum titanate (LaTiO3), gallium oxide (GaO), zinc oxide (ZnO), diamond, and/or the like.
  • Barrier layers 42, 46 can improve a quality of the contact and/or enable additional functionality.
  • a material and/or thickness of barrier layer 42, 46 can be selected based on a desired operating characteristic of the device. For example, an amount of capacitive coupling provided by capacitive electrode 14B can be adjusted using barrier layers 42, 46.
  • formation of capacitive electrode 14B and/or barrier layer 42, 46 can include determining an amount of capacitive coupling desired for operating a device fabricated with semiconductor structure 12, and selecting a material and/or thickness of barrier layer 42, 46 that will enable the desired amount of capacitive coupling between capacitive electrode 14B and the semiconductor layer in semiconductor structure 12.
  • the required capacitance, C, of capacitive electrode 14B per unit area can be calculated by the formula
  • d B and ⁇ B are the thickness and dielectric permittivity of barrier layers 42, 46, and d s and ⁇ s are the thickness and dielectric permittivity of the depletion region of the semiconductor layer in semiconductor structure 12.
  • barrier layer 46 also isolates capacitive electrode 14B from DC conducting electrode 14A.
  • an additional DC or RF voltage can be applied to capacitive electrode 14B to modulate the conductivity of the semiconductor layer (e.g., device conducting channel) in semiconductor structure 12.
  • the semiconductor layer e.g., device conducting channel
  • barrier layer 46 also isolates capacitive electrode 14B from DC conducting electrode 14A.
  • an additional DC or RF voltage can be applied to capacitive electrode 14B to modulate the conductivity of the semiconductor layer (e.g., device conducting channel) in semiconductor structure 12.
  • a DC voltage to a capacitive electrode 14B that is used as a source and/or drain contact of a field effect transistor, an additional reduction in the access resistance for the field effect transistor can be achieved without requiring more complicated techniques such as selective doping.
  • capacitive electrode 14B and/or barrier layer 46 can include determining a desired amount of modulation for the conductivity of the semiconductor layer, and selecting a material and/or thickness of barrier layer 46 that will enable the desired amount of modulation of the conductivity of the semiconductor layer. For example, in a typical field effect transistor device with a threshold voltage of -4 Volts, application of a positive voltage exceeding +4 Volts at capacitive electrode 14B would not only remove the depletion of the semiconductor layer caused by the surface potential, but may nearly double the concentration in the source-gate spacing and thus decrease the access resistance by a factor of nearly two.
  • the illustrative semiconductor structures and compound contacts described herein can be implemented as part of any type of multi- terminal semiconductor device.
  • the composite contact provides a combined resistive-capacitive coupling to a semiconductor layer, which reduces a contact impedance when a corresponding high frequency semiconductor device is operated at high frequencies and can make a maximum oscillation frequency largely insensitive to DC contact resistance.
  • capacitive electrode 14B can be formed along with one or more contacts for the multi-terminal semiconductor device in an alignment-free manner.
  • the simultaneous formation of multiple contacts enables close spacing between the contacts.
  • FIGS. 14A-B show the formation of multiple contacts on a semiconductor structure according to an embodiment.
  • a semiconductor structure 12 including two DC conducting electrodes 14A is shown.
  • a barrier layer 20 e.g., a dielectric
  • two capacitive electrodes 14B are formed over DC conducting electrodes 14A simultaneously with two additional contacts 22, 24.
  • one capacitive electrode 14B is formed directly on DC conducting electrode 14A, while the other is formed on dielectric layer 20.
  • contact 22 is also formed on barrier layer 20, while contact 24 is formed directly on semiconductor structure 12.
  • any number of contacts and/or combinations of types of contacts can be formed using any solution.
  • a field effect transistor includes compound contacts for the source and drain contacts.
  • FIGS. 15A-B show illustrative steps of fabricating a heterostructure field effect transistor according to embodiments.
  • a heterostructure 30 is obtained, which includes a buffer layer 32, a device conducting channel, e.g., two degree electron gas 34, and a barrier layer 36.
  • Heterostructure 30 can comprise, for example, a group Ill-Nitride based heterostructure such as an aluminum gallium nitride/gallium nitride (AIGaN/GaN) heterostructure. It is understood that heterostructure 30 could include one or more additional layers, which are not shown for clarity.
  • two DC conducting electrodes 14A, for a source and drain contact are shown formed on heterostructure 30 and attached to two degree electron gas 34.
  • FIG. 15B two capacitive electrodes 14B are formed along with a gate 38 in an alignment-free manner. Each capacitive electrode 14B extends beyond the respective DC conducting electrode 14A in a direction towards gate 38. Each capacitive electrode 14B and DC conducting electrode 14A pair create a source contact 39A and drain contact 39B, respectively. It is understood that one or both contacts 39A-B could include additional layer(s), such as a barrier layer between capacitive electrode 14B and DC conducting electrode 14A. These have not been shown for clarity.
  • Each capacitive electrode 14B overhangs the corresponding DC conducting electrode 14A by a distance, L ⁇ xt , as indicated in FIG. 15B.
  • the distance for the overhang can be selected to provide a desired capacitance between capacitive electrode 14A and the semiconductor layer (e.g., two degree electron gas 34) using any solution.
  • a desired separation distance e.g., field- controlling gap
  • a separation distance that ensures a trapezoidal field distribution in a gate-to- drain spacing of the field effect transistor can be determined.
  • the formation of gate 38 and/or capacitive electrode 14B for drain contact 39B can include ensuring that the gate-to-drain spacing comprises the separation distance.
  • fabrication of the device is further shown including forming a set of field plates 66A-B on gate 64 (which corresponds to gate 38 in FIG. 15B) using any solution.
  • the desired separation distance e.g., field-controlling gap
  • the desired separation distance can be determined for the field plate 66B that is closest to drain contact 62B and capacitive electrode 14B for the drain contact 62B.
  • the formation of field plate 66B and/or capacitive electrode 14B for drain contact 62B can ensure that the spacing between the field plate 66B and capacitive electrode 14B for drain contact 62B comprises the determined separation distance.
  • additional processing may be performed in fabricating a device/structure with the composite contacts described herein.
  • additional processing such as etching, chemical or thermal treatment, the deposit of one or more layers, and/or the like can be implemented to achieve and/or improve certain aspects of the device functionality using any solution.
  • the processing can be selected based on one or more desired aspects of the device operation, the device type, the materials, and/or the like, using any solution.
  • FIG. 8 shows an encapsulating layer 80 being formed over a field effect transistor.
  • Encapsulating layer 80 can comprise any insulating material having a high breakdown field, such as a dielectric, to increase the breakdown voltage of the field effect transistor, which can help prevent a premature breakdown due to a surface flashover through the air or another medium adjacent to the device contact region and the spacing between the contacts during operation of the device.
  • Encapsulating layer 80 can comprise a high dielectric strength insulating material that increases a breakdown voltage of the field effect transistor, thereby helping to prevent the premature breakdown of the field effect transistor.
  • the material can have a high breakdown field that well exceeds that of air and is close to that of the material constituting the field effect transistor.
  • Illustrative examples of materials for encapsulating layer 80 include silicon dioxide, silicon nitride, bisbenzocyclobutene, and/or the like. While encapsulating layer 80 is shown in conjunction with a field effect transistor, it is understood that encapsulating layer 80 can be included on any type of semiconductor device.
  • the formation of the composite contacts can be implemented as part of a fabrication process for various types of semiconductor devices, including a field effect transistor, a diode (light-emitting, photodetector, and/or the like), a bipolar junction transistor, a laser, a photodetector, and/or the like.
  • a device fabricated using a structure described herein can be incorporated in various types of circuits and applications, including a radio frequency circuit, a microwave amplifier, an oscillator, a switcher, an optoelectronic circuit, and/or the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

La présente invention concerne un contact de composite destiné à un dispositif à semi-conducteurs qui comporte une électrode conductrice en CC qui est reliée à une couche semi-conductrice dans le dispositif, et une électrode capacitive qui se trouve partiellement sur l'électrode conductrice en CC et s'étend au-delà de l'électrode conductrice en CC. Un procédé de fabrication d'un dispositif à semi-conducteurs doté d'un contact de composite comporte l'étape consistant à former le contact de composite sur une couche semi-conductrice dans une structure semi-conductrice. Le contact de composite est formé en formant une électrode conductrice en CC reliée à une couche semi-conductrice dans une structure semi-conductrice et en formant une électrode capacitive qui se trouve partiellement sur l'électrode conductrice en CC et qui s'étend au-delà de l'électrode conductrice en CC. Le contact de composite fournit un couplage résistant capacitif combiné à la couche semi-conductrice. Par conséquent, une impédance de contact est réduite lorsque le dispositif à semi-conducteurs correspondant est actionné à de hautes fréquences.
PCT/US2008/054368 2007-02-23 2008-02-20 Dispositif à semi-conducteurs ayant un contact de composite et procédé de fabrication de celui-ci WO2008103699A1 (fr)

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
US90310907P 2007-02-23 2007-02-23
US90310407P 2007-02-23 2007-02-23
US60/903,109 2007-02-23
US60/903,104 2007-02-23
US90572507P 2007-03-08 2007-03-08
US90563407P 2007-03-08 2007-03-08
US60/905,725 2007-03-08
US60/905,634 2007-03-08
US11/781,302 US8461631B2 (en) 2007-02-23 2007-07-23 Composite contact for semiconductor device
US11/781,308 US7674666B2 (en) 2007-02-23 2007-07-23 Fabrication of semiconductor device having composite contact
US11/781,302 2007-07-23
US11/781,308 2007-07-23

Publications (1)

Publication Number Publication Date
WO2008103699A1 true WO2008103699A1 (fr) 2008-08-28

Family

ID=39710464

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/054368 WO2008103699A1 (fr) 2007-02-23 2008-02-20 Dispositif à semi-conducteurs ayant un contact de composite et procédé de fabrication de celui-ci

Country Status (1)

Country Link
WO (1) WO2008103699A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5126284A (en) * 1991-10-25 1992-06-30 Curran Patrick A Method of inductively contacting semiconductor regions
US5196907A (en) * 1990-08-20 1993-03-23 Siemens Aktiengesellschaft Metal insulator semiconductor field effect transistor
US6207584B1 (en) * 2000-01-05 2001-03-27 International Business Machines Corp. High dielectric constant material deposition to achieve high capacitance
US6589822B1 (en) * 1995-12-09 2003-07-08 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method for top-gate type and bottom-gate type thin film transistors

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5196907A (en) * 1990-08-20 1993-03-23 Siemens Aktiengesellschaft Metal insulator semiconductor field effect transistor
US5126284A (en) * 1991-10-25 1992-06-30 Curran Patrick A Method of inductively contacting semiconductor regions
US6589822B1 (en) * 1995-12-09 2003-07-08 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method for top-gate type and bottom-gate type thin film transistors
US6207584B1 (en) * 2000-01-05 2001-03-27 International Business Machines Corp. High dielectric constant material deposition to achieve high capacitance

Similar Documents

Publication Publication Date Title
US7674666B2 (en) Fabrication of semiconductor device having composite contact
US10446542B1 (en) GaN structures
US6867078B1 (en) Method for forming a microwave field effect transistor with high operating voltage
JP5519930B2 (ja) ゲート−ソースフィールドプレートを含むワイドバンドギャップトランジスタ
US7229903B2 (en) Recessed semiconductor device
US20160293747A1 (en) Semiconductor devices with field plates
US20070228401A1 (en) Semiconductor device
US10256332B1 (en) High hole mobility transistor
US9252253B2 (en) High electron mobility transistor
JP2011071307A (ja) 電界効果トランジスタ及びその製造方法
US20220376104A1 (en) Transistors including semiconductor surface modification and related fabrication methods
US11594625B2 (en) III-N transistor structures with stepped cap layers
US11961888B2 (en) Extrinsic field termination structures for improving reliability of high-voltage, high-power active devices
US9673285B2 (en) Semiconductor device with low-conducting buried and/or surface layers
US20180301528A1 (en) High electron mobility transistor
CN116344586A (zh) 折叠沟道氮化镓基场效应晶体管及其制备方法
US11929428B2 (en) Circuits and group III-nitride high-electron mobility transistors with buried p-type layers improving overload recovery and process for implementing the same
US20220367695A1 (en) Circuits and group iii-nitride transistors with buried p-layers and controlled gate voltages and methods thereof
US20220367697A1 (en) Group iii-nitride transistors with back barrier structures and buried p-type layers and methods thereof
US20220013423A1 (en) Electronic device and manufacturing method thereof
WO2008103699A1 (fr) Dispositif à semi-conducteurs ayant un contact de composite et procédé de fabrication de celui-ci
US20220376070A1 (en) Semiconductor device and fabrication method thereof
US20240063219A1 (en) Integrated depletion and enhancement mode gallium nitride high-electron mobility transistors
US20220052163A1 (en) Gate control for hemt devices using dielectric between gate edges and gate field plates
KR102268169B1 (ko) 질화갈륨계 반도체소자 및 그 제조방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08730215

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08730215

Country of ref document: EP

Kind code of ref document: A1