WO2008096447A1 - データ転送回路、情報処理装置および情報処理装置の試験方法 - Google Patents

データ転送回路、情報処理装置および情報処理装置の試験方法 Download PDF

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Publication number
WO2008096447A1
WO2008096447A1 PCT/JP2007/052397 JP2007052397W WO2008096447A1 WO 2008096447 A1 WO2008096447 A1 WO 2008096447A1 JP 2007052397 W JP2007052397 W JP 2007052397W WO 2008096447 A1 WO2008096447 A1 WO 2008096447A1
Authority
WO
WIPO (PCT)
Prior art keywords
information processing
processing device
packet
crossbar
data transfer
Prior art date
Application number
PCT/JP2007/052397
Other languages
English (en)
French (fr)
Inventor
Yasuhiro Kuroda
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/052397 priority Critical patent/WO2008096447A1/ja
Publication of WO2008096447A1 publication Critical patent/WO2008096447A1/ja

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/101—Packet switching elements characterised by the switching fabric construction using crossbar or matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/55—Prevention, detection or correction of errors
    • H04L49/555—Error detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1302—Relay switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1304—Coordinate switches, crossbar, 4/2 with relays, coupling field
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13106—Microprocessor, CPU
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13322—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

　クロスバ制御回路（１００Ａ）は、テストモード時において、行き先判定ゲート（１０２ａ～１０２ｄ）が、自クロスバ制御回路（１００Ａ）宛てのパケットを、他のクロスバ制御回路へブロードキャストする。行き先判定ゲート（１０２ｅ～１０２ｇ）には、パケットの送り元のクロスバ識別番号が設定されており、その設定とパケットの送り元システムボード番号とが矛盾する場合に、このパケットを破棄する。また、行き先判定ゲート（１０２ｅ～１０２ｇ）には、自クロスバ識別番号が設定されており、その設定とパケットの宛て先システムボード番号が矛盾する場合には、このパケットを破棄する。
PCT/JP2007/052397 2007-02-09 2007-02-09 データ転送回路、情報処理装置および情報処理装置の試験方法 WO2008096447A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/052397 WO2008096447A1 (ja) 2007-02-09 2007-02-09 データ転送回路、情報処理装置および情報処理装置の試験方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/052397 WO2008096447A1 (ja) 2007-02-09 2007-02-09 データ転送回路、情報処理装置および情報処理装置の試験方法

Publications (1)

Publication Number Publication Date
WO2008096447A1 true WO2008096447A1 (ja) 2008-08-14

Family

ID=39681366

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/052397 WO2008096447A1 (ja) 2007-02-09 2007-02-09 データ転送回路、情報処理装置および情報処理装置の試験方法

Country Status (1)

Country Link
WO (1) WO2008096447A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013054444A (ja) * 2011-09-01 2013-03-21 Lapis Semiconductor Co Ltd 半導体集積回路

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000134283A (ja) * 1998-10-28 2000-05-12 Nec Eng Ltd 回線切換装置及びそれに用いるルートチェック方法並びにその制御プログラムを記録した記録媒体
JP2001024650A (ja) * 1999-07-02 2001-01-26 Fujitsu Ltd Ａｔｍ交換機及びそれにおける回線装置の試験方法
JP2002016664A (ja) * 2000-06-27 2002-01-18 Hitachi Ltd ループバックテスト方法および装置
JP2005073043A (ja) * 2003-08-26 2005-03-17 Nippon Steel Corp テスト支援方法及びテスト支援装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000134283A (ja) * 1998-10-28 2000-05-12 Nec Eng Ltd 回線切換装置及びそれに用いるルートチェック方法並びにその制御プログラムを記録した記録媒体
JP2001024650A (ja) * 1999-07-02 2001-01-26 Fujitsu Ltd Ａｔｍ交換機及びそれにおける回線装置の試験方法
JP2002016664A (ja) * 2000-06-27 2002-01-18 Hitachi Ltd ループバックテスト方法および装置
JP2005073043A (ja) * 2003-08-26 2005-03-17 Nippon Steel Corp テスト支援方法及びテスト支援装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013054444A (ja) * 2011-09-01 2013-03-21 Lapis Semiconductor Co Ltd 半導体集積回路

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