WO2008090816A1 - Mask pattern designing method and semiconductor device fabrication method - Google Patents

Mask pattern designing method and semiconductor device fabrication method Download PDF

Info

Publication number
WO2008090816A1
WO2008090816A1 PCT/JP2008/050598 JP2008050598W WO2008090816A1 WO 2008090816 A1 WO2008090816 A1 WO 2008090816A1 JP 2008050598 W JP2008050598 W JP 2008050598W WO 2008090816 A1 WO2008090816 A1 WO 2008090816A1
Authority
WO
WIPO (PCT)
Prior art keywords
opc
mask pattern
cell
ope
canceller
Prior art date
Application number
PCT/JP2008/050598
Other languages
French (fr)
Japanese (ja)
Inventor
Hirokazu Nosato
Tetsuaki Matsunawa
Hidenori Sakanashi
Tetsuya Higuchi
Original Assignee
National Institute Of Advanced Industrial Science And Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Institute Of Advanced Industrial Science And Technology filed Critical National Institute Of Advanced Industrial Science And Technology
Priority to JP2008555036A priority Critical patent/JP4883591B2/en
Publication of WO2008090816A1 publication Critical patent/WO2008090816A1/en

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Abstract

To realize shorting of OPC (Optical Proximity Correction) processing time, in a mask pattern design method using an OPC -processed cell library. When designing a mask pattern using an OPC-processed cell library, an OPC canceller for suppressing the occurrence of an OPE (Optical Proximity Effect) caused by a pattern formed in a cell is formed in a part of the cell. The OPE canceller comprises an aggregation of tiny patterns that are formed on a photo mask together with the pattern in the cell but are not transferred onto a wafer. The layout, number, shape, light transmittance, etc. of the tiny patterns constituting the OPE canceller are appropriately adjusted using an optimization method, a random search method, or other method.
PCT/JP2008/050598 2007-01-26 2008-01-18 Mask pattern designing method and semiconductor device fabrication method WO2008090816A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008555036A JP4883591B2 (en) 2007-01-26 2008-01-18 Mask pattern design method and semiconductor device manufacturing method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007015761 2007-01-26
JP2007-015761 2007-01-26

Publications (1)

Publication Number Publication Date
WO2008090816A1 true WO2008090816A1 (en) 2008-07-31

Family

ID=39644392

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/050598 WO2008090816A1 (en) 2007-01-26 2008-01-18 Mask pattern designing method and semiconductor device fabrication method

Country Status (2)

Country Link
JP (1) JP4883591B2 (en)
WO (1) WO2008090816A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015034973A (en) * 2013-07-10 2015-02-19 キヤノン株式会社 Creation method of pattern, program, and information processor
US20220180503A1 (en) * 2020-12-07 2022-06-09 Samsung Electronics Co., Ltd. Method of verifying error of optical proximity correction model
CN118131581A (en) * 2024-05-06 2024-06-04 全芯智造技术有限公司 Optical proximity correction method, electronic device, and storage medium

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104423142B (en) * 2013-08-22 2020-05-05 中芯国际集成电路制造(上海)有限公司 Calibration data collection method and system for optical proximity correction model
US12293279B2 (en) * 2019-08-29 2025-05-06 Synopsys, Inc. Neural network based mask synthesis for integrated circuits

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0915833A (en) * 1995-06-30 1997-01-17 Sony Corp Scanning data forming device and scanning data forming method in exposing mask manufacturing device
JPH1032253A (en) * 1996-07-15 1998-02-03 Toshiba Corp Semiconductor device and its manufacturing method, basic cell library and its forming method, mask
JP2004288685A (en) * 2003-03-19 2004-10-14 Nec Micro Systems Ltd Method and program for designing layout of semiconductor integrated circuit
JP2005084101A (en) * 2003-09-04 2005-03-31 Toshiba Corp Method for manufacturing mask pattern, method for manufacturing semiconductor device, manufacturing system of mask pattern, cell library, and method for manufacturing photomask
JP2006139165A (en) * 2004-11-15 2006-06-01 Seiko Epson Corp Recording medium on which cell is recorded and semiconductor integrated circuit
JP2006276079A (en) * 2005-03-28 2006-10-12 National Institute Of Advanced Industrial & Technology Mask pattern design method and design apparatus in optical proximity correction of optical lithography, and semiconductor device manufacturing method using the same
JP2007080965A (en) * 2005-09-12 2007-03-29 Matsushita Electric Ind Co Ltd Semiconductor device manufacturing method, library used therefor, recording medium, and semiconductor manufacturing apparatus

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0915833A (en) * 1995-06-30 1997-01-17 Sony Corp Scanning data forming device and scanning data forming method in exposing mask manufacturing device
JPH1032253A (en) * 1996-07-15 1998-02-03 Toshiba Corp Semiconductor device and its manufacturing method, basic cell library and its forming method, mask
JP2004288685A (en) * 2003-03-19 2004-10-14 Nec Micro Systems Ltd Method and program for designing layout of semiconductor integrated circuit
JP2005084101A (en) * 2003-09-04 2005-03-31 Toshiba Corp Method for manufacturing mask pattern, method for manufacturing semiconductor device, manufacturing system of mask pattern, cell library, and method for manufacturing photomask
JP2006139165A (en) * 2004-11-15 2006-06-01 Seiko Epson Corp Recording medium on which cell is recorded and semiconductor integrated circuit
JP2006276079A (en) * 2005-03-28 2006-10-12 National Institute Of Advanced Industrial & Technology Mask pattern design method and design apparatus in optical proximity correction of optical lithography, and semiconductor device manufacturing method using the same
JP2007080965A (en) * 2005-09-12 2007-03-29 Matsushita Electric Ind Co Ltd Semiconductor device manufacturing method, library used therefor, recording medium, and semiconductor manufacturing apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015034973A (en) * 2013-07-10 2015-02-19 キヤノン株式会社 Creation method of pattern, program, and information processor
US20220180503A1 (en) * 2020-12-07 2022-06-09 Samsung Electronics Co., Ltd. Method of verifying error of optical proximity correction model
US11699227B2 (en) * 2020-12-07 2023-07-11 Samsung Electronics Co., Ltd. Method of verifying error of optical proximity correction model
CN118131581A (en) * 2024-05-06 2024-06-04 全芯智造技术有限公司 Optical proximity correction method, electronic device, and storage medium

Also Published As

Publication number Publication date
JP4883591B2 (en) 2012-02-22
JPWO2008090816A1 (en) 2010-05-20

Similar Documents

Publication Publication Date Title
WO2008090816A1 (en) Mask pattern designing method and semiconductor device fabrication method
TW200625407A (en) Method for foring a finely patterned resist
CN103941550B (en) A kind of intelligent selection target size method of adjustment
CN105093808B (en) Optical proximity correction method for hole layer for avoiding large length-width ratio pattern
TW200721260A (en) Substrate processing method, photomask manufacturing method, photomask and device manufacturing method
WO2011143013A3 (en) Method for integrated circuit design and manufacture using diagonal minimum-width patterns
TWI266373B (en) Pattern forming method and method of manufacturing semiconductor device
JP2013174728A5 (en)
US8434034B2 (en) Method of making optical proximity correction to original gate photomask pattern based on different substrate areas
CN110989288B (en) Mask, mask system and preparation and photoetching methods
TW200603253A (en) A semiconductor manufacturing method and an exposure mask
US8383299B2 (en) Double patterning mask set and method of forming thereof
KR102504179B1 (en) Photomask including shading layer and method forming patterns using the same
CN103309148A (en) Optical proximity effect correction method
KR20150120265A (en) Method of designing integrated circuit, system of carrying out the method and system of verifying integrated circuit
US9760027B2 (en) Scanner routing method for particle removal
US8661372B1 (en) Optical proximity correction method
US7727683B2 (en) High-transmission attenuating PSM
KR100801738B1 (en) Photomask and Forming Method
CN104280999A (en) Optical proximity correction for connecting via between layers of a device
US9274416B2 (en) Method for forming photo-mask and OPC method
JP2011209638A (en) Photomask and method for manufacturing semiconductor device
KR100989706B1 (en) How to make a mask
US8765495B1 (en) Method of forming pattern of doped region
US20130045607A1 (en) Pattern generating apparatus, pattern generating program, and method for fabricating semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08703448

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2008555036

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08703448

Country of ref document: EP

Kind code of ref document: A1