KR20150120265A - Method of designing integrated circuit, system of carrying out the method and system of verifying integrated circuit - Google Patents

Abstract

The present invention provides a method for designing an integrated circuit capable of scaling-down an integrated circuit by using a partial circuit layout which improves scaling of the integrated circuit. The method for designing an integrated circuit receives a data file having a scaling reinforced circuit layout and designs a first standard cell layout by using a design rule and the data file. The scaling reinforced circuit layout includes a design rule violation layer. Designing the first standard cell layout designs the first standard cell layout by using the data file and designs a second area of the first standard cell layout by using the design rule.

Description

TECHNICAL FIELD The present invention relates to an integrated circuit design method, a system and an integrated circuit verification system for implementing the integrated circuit design method, a method of designing integrated circuit,

The present invention relates to an integrated circuit design method, a system for implementing the method, and an integrated circuit verification system.

An integrated circuit, or IC, is made by patterning devices and their interconnections on a substrate, such as a semiconductor wafer. The manufacturing process of the integrated circuit begins by designing the integrated circuit using electronic design automation (EDA), which allows the designer to position and connect the various components of the circuit interactively. That is, using electronic design automation, an integrated circuit layout is created. The circuit layout includes circuit components, connection wiring, and the physical location and size of the various layers.

By transferring the integrated circuit layout onto a semiconductor substrate, an integrated circuit is fabricated. However, before manufacturing an integrated circuit using such an integrated circuit layout, the integrated circuit layout is subjected to a verification process.

The verification process of the layout is done through whether the integrated circuit layout conforms to the design rules. However, creating an integrated circuit layout that fully complies with such a design rule has limitations in reducing the scaling of the integrated circuit.

It is an object of the present invention to provide an integrated circuit design method capable of achieving scaling-down of an integrated circuit by using a partial circuit layout capable of improving the scaling of the integrated circuit.

Another object to be solved by the present invention is to provide an integrated circuit design system capable of achieving scaling-down of the integrated circuit.

It is yet another object of the present invention to provide an integrated circuit verification system that can verify an integrated circuit layout.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

An aspect of the integrated circuit design method of the present invention to solve the above problems is to receive a data file including a scaling enhancement circuit layout and to design a first standard cell layout using a design rule and the data file Wherein the scaling enhancement circuit layout comprises a design rule violation layer and wherein designing the first standard cell layout uses the data file to define a first standard cell layout, And designing a second region of the first standard cell layout using the design rules.

In some embodiments of the present invention, the method further comprises inspecting the design rules of the first standard cell layout using a design rule checker, wherein examining the design rules of the first standard cell layout comprises: Lt; RTI ID = 0.0 > 1 < / RTI > standard cell layout.

In some embodiments of the invention, the scaling enhancement circuit layout comprises a marker layer.

In some embodiments of the present invention, designing a first region of the first standard cell layout places the scaling enhancement circuit layout in a first region of the first standard cell layout.

In some embodiments of the invention, the method further comprises designing a second standard cell layout that is different from the first standard cell layout.

In some embodiments of the present invention, designing the second standard cell layout may include designing a first area of the second standard cell layout using the data file, and using the design rules, And designing a second area of the cell layout.

In some embodiments of the invention, the first area of the first standard cell layout and the first area of the second standard cell layout comprise the same layout.

In some embodiments of the invention, the method further comprises designing a logic block layout comprising the first standard cell layout, the first standard cell layout including the scaling enhancement circuit layout, the scaling enhancement circuit layout comprising: And being disposed in a portion of the logic block layout.

In some embodiments of the present invention, a design rule violation layer is defined in a portion of a standard cell, and a fabrication process is optimized for the violation requirement region, thereby designing the design rule violation layer, And designating the scaled enhancement circuit layout as a golden scaled enhancement layout.

In some embodiments of the present invention, the method further includes using the Golden Scaling enhancement layout to check whether the scaling enhancement circuit layout included in the logic block layout has been modified in the course of designing the first standard cell layout do.

In some embodiments of the invention, the scaling enhancement circuit layout is part of a standard cell layout that performs a specific function.

In some embodiments of the present invention, the data file is in the form of a graphic database system (GDS) file, a GDS instance file, or a hard macro file.

Another aspect of the integrated circuit design method of the present invention to solve the above problems is to design a standard cell layout including a first scaling enhancement circuit layout, design a logic block layout including the standard cell layout, And replacing the first scaling enhancement circuit layout in the layout with a second scaling enhancement circuit layout to update the logic block layout.

In some embodiments of the present invention, the standard cell layout includes a first area and a second area located in the periphery of the first area, the designing of the standard cell layout comprises a first area of the standard cell layout , Placing the first scaled enhancement circuit layout and designing the second area of the standard cell layout using design rules.

In some embodiments of the present invention, updating the logic block layout includes removing the first scaled enhancement circuit layout included in the logic block layout, and then removing the second scaled enhancement circuit layout from the first scaled enhancement circuit layout, And placing the enhanced circuit layout.

In some embodiments of the present invention, the first scaling enhancement circuit layout includes a marker layer, and updating the logic block layout may include identifying the location of the first scaled enhancement circuit layout using the marker layer .

Another aspect of the integrated circuit design method of the present invention to solve the above problems is to receive a first data file including a first scaling enhancement circuit layout and a second data file including a second scaling enhancement circuit layout, Designing a first standard cell layout using the rule and the first data file, designing a second standard cell layout using the design rule and the second data file, Wherein the first scaling enhancement circuit layout comprises a first design rule violation layer and the second scaling enhancement circuit layout comprises a second design rule violation layer, Wherein designing the first standard cell layout comprises designating the first standard cell layout using the first data file, Out and designing a second area of the first standard cell layout using the design rules, wherein designing the second standard cell layout comprises designing a second area of the first standard cell layout using the second data file Designing a first region of the second standard cell layout and designing a second region of the second standard cell layout using the design rules.

In some embodiments of the present invention, the first standard cell layout and the second standard cell layout are layouts of standard cells performing different functions.

In some embodiments of the present invention, the first scaled enhancement circuit layout and the second scaled enhancement circuit layout are the same layout.

According to another aspect of the present invention, there is provided an integrated circuit design system including a storage module storing a logic block layout including a first scaling enhancement circuit layout, a second scaling enhancement module updating the first scaling enhancement circuit layout, An update module that removes the first scaling enhancement circuit layout from the logic block layout and places the second scaling enhancement circuit layout at a location where the first scaling enhancement circuit layout is removed, .

Other specific details of the invention are included in the detailed description and drawings.

1 is a flowchart illustrating an integrated circuit design method according to an embodiment of the present invention.
FIGS. 2 to 5 are flowcharts and figures for explaining S100 of FIG.
6 is a view for explaining S110 in Fig.
7 is a view for explaining S120 in Fig.
8 is a view for explaining S130 in Fig.
9 is a block diagram illustrating an integrated circuit verification system that implements S130 of FIG.
10 is a flowchart illustrating a method of designing an integrated circuit according to another embodiment of the present invention.
11 is a view for explaining S220 of FIG.
12 is a block diagram for explaining an integrated circuit design system for executing S22 of Fig.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout the specification.

One element is referred to as being "connected to " or" coupled to "another element, either directly connected or coupled to another element, One case. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

1 to 9, a method of designing an integrated circuit according to an embodiment of the present invention will be described.

1 is a flowchart illustrating an integrated circuit design method according to an embodiment of the present invention. FIGS. 2 to 5 are flowcharts and figures for explaining S100 of FIG. 6 is a view for explaining S110 in Fig. 7 is a view for explaining S120 in Fig. 8 is a view for explaining S130 in Fig. 9 is a block diagram illustrating an integrated circuit verification system that implements S130 of FIG.

1 to 5, a first data file 120f including a first scaling enhancement circuit layout 120 is received (S100). It also receives a second data file 130f that includes a first scaling enhancement circuit layout 120 and a second scaling enhancement circuit layout 130 that is different from the first scaling enhancement circuit layout 120. [

Receiving the first data file 120f and the second data file 130f, it is possible to receive a design rule manual including a design rule necessary for designing an integrated circuit.

Design rules are several variables provided by integrated circuit manufacturers. Through such design rules, the integrated circuit designer can verify the accuracy of the photomask set to be made through the integrated circuit layout.

A design rule may include, for example, a ground rule and a special structure. Here, a special structure means a structure that applies margins more strictly than a ground rule. That is, a special structure is also a kind of design rule.

The design rules may include, for example, a width rule, a minimum area rule, a space rule, an enclosure rule, a symmetry rule, an alignment rule (alignment rule) rule, and the like.

The design rules can be provided in the form of a document to the integrated circuit designer.

Unlike the confines rule, the first scaling enhancement circuit layout 120 and the second scaling enhancement circuit layout 130 may be provided to the integrated circuit designer in the form of a graphic file.

The first data file 120f and the second data file 130f may be, for example, a graphic database system (GDS) file, a graphic database system instance (GDS instance) file, or a hard macro file , But is not limited thereto. That is, the first data file 120f and the second data file 130f may be graphics file formats capable of representing the layout of the circuit.

In other words, the first scaling enhancement circuit layout 120 and the second scaling enhancement circuit layout 130 may be provided to an integrated circuit designer in the form of, for example, a graphic database system, a graphic database system instance, or a hard macro .

2 to 5, a first data file 120f and a second data file 130f, each including a first scaling enhancement circuit layout 120 and a second scaling enhancement circuit layout 130, Will be described.

Referring to FIG. 2 and FIG. 3, a part of the target standard cell 100 is defined as a design rule violation requiring area 105 (S11).

The target standard cell 100 may be a basic cell required to configure a logic circuit. That is, the target standard cell 100 may be a circuit component performing a specific function. For example, the target standard cell 100 may be a standard cell representing a NAND circuit, a NOR circuit, an inverter circuit, a flip flop circuit, and the like, but is not limited thereto.

Since the design rule violation need area 105 is a part of the target standard cell 100, the confusion rule violation area 105 does not perform a specific function. That is, the design rule violation requiring area 105 may be a part of a standard cell performing a specific function.

The design rule violation requiring area 105 may be a part of one standard cell or a part of standard cells of various kinds. That is, it is needless to say that a common part included in various types of standard cells can be defined as a design rule violation requiring area 105.

The design rule violation need area 105 defines, for example, a portion of the target standard cell 100 that requires scaling enhancement and manufacturing process enhancement. That is, the design rule violation need area 105 can define a part where a process challenge is high in the manufacturing process.

For example, when implementing a cross-couple in the area of a given standard cell, a diagonal contact plug that takes into account the process margin must be designed in the standard cell. Such a complex structure is difficult to describe as a design rule. Or, even if a complex structure is described as a design rule, it is very difficult to create a layout with the same structure as that of a design rule developer.

Therefore, a portion that is difficult to describe in the design rule or difficult to describe the same layout even if it is described is defined as a region 105 that requires violation of the design rule.

The design rule violation need area 105 shown in FIG. 3 is for convenience of explanation, but is not limited thereto.

Referring to FIG. 2, in order to achieve the advantage of scaling down, a portion defined by the design rule violation required area 105 is optimized in terms of the manufacturing process (S12). That is, from the viewpoint of the manufacturing process, the layout of the area 105 requiring the violation of the design rule is optimized.

It is not necessary to optimize the layout of all the layers included in the design rule violation requiring area 105. [ That is, for at least some of the layers included in the design rule violation requiring area 105, the layout may be optimized in terms of the manufacturing process.

Thus, the fabrication process for at least some of the design rule violation need areas 105 is optimized to design the design rule violation layer.

Referring to FIGS. 2, 4, and 5, a first scaling enhancement circuit layout 120 including a design rule violation layer designed through optimization of a manufacturing process is designed (S13). The first scaling enhancement circuit layout 120 is a layout in which the design rule violation need area 105 is optimized from a manufacturing process viewpoint.

The first scaling enhancement circuit layout 120 designed based on the design rule violation need area 105 is part of the target standard cell layout because the design rule violation need area 105 is part of the target standard cell 100. [ Therefore, the portion produced based on the first scaling enhancement circuit layout 120 can not perform a specific function.

For the sake of convenience of explanation, the design rule violation layer is described as an optimization of the required area 105 that is out of the design rule shown in Fig. 3 in view of the manufacturing process. That is, the design rule violation layer and the first scaling enhancement circuit layout 120 are described as being the same.

However, the present invention is not limited thereto, and it is needless to say that it is possible to design a multi-character rule violation layer by optimizing only a part of a plurality of layers included in the violation area 105 for design rule violation.

Then, the first scaling enhancement circuit layout 120 is designated as the golden scaling enhancement layout 110 (S14). In addition, the designated golden scaling enhancement layout 110 may be registered.

The first scaling enhancement circuit layout 120 and the golden scaling enhancement layout 110 are substantially the same layout.

The golden scaling enhancement layout 110 may include only a circuit layout as shown in FIG. 4A or may be a golden scaling enhancement layout including a marker layer 115 as shown in FIG. 4B 110m).

Then, a first data file 120f including the first scaled enhancement circuit layout 120 is generated. And provides the generated first data file 120f to the integrated circuit designer.

The first scaling enhancement circuit layout 120 included in the first data file 120f may include, but is not limited to, the marker layer 115 as shown in FIG. 4 (b).

An integrated circuit designer may be advantageous from the standpoint of implementing an integrated circuit, although the design of the integrated circuit in accordance with the rules of multiplicity may be disadvantageous from a scaling point of view.

If an integrated circuit designer designs an integrated circuit layout deviating from a multi-person rule, it is unknown whether the layout contrary to the design rules can be implemented as an actual integrated circuit. That is, it is fortunate that an integrated circuit maker can optimize the manufacturing process to implement a layout that is contrary to the design rule as an integrated circuit, otherwise the integrated circuit design may have to be re-designed.

On the other hand, an integrated circuit manufacturer can implement the layout of an integrated circuit contrary to the design rule as an actual integrated circuit by optimizing the manufacturing process. The reason why an integrated circuit maker can implement the layout of an integrated circuit contrary to a design rule is because an integrated circuit maker can implement a complicated pattern that deviates from a design rule by controlling manufacturing process conditions and the like.

Further, when a photomask is manufactured using an integrated circuit layout, an integrated circuit maker can use, for example, an optical proximity correction (OPC) method or the like. That is, the integrated circuit maker can implement a complicated pattern that deviates from the design rule by adjusting the condition of the step of manufacturing the photomask.

Integrated circuit designers design an integrated circuit layout based on design rules, but integrated circuit manufacturers implement integrated circuits through optimization of the actual manufacturing process. Thus, an integrated circuit designer can optimize a highly complicated structure that deviates from a design rule or is expressed by a design rule from a manufacturing process perspective, and can make it into a scaling-enhanced circuit layout.

Thus, the design of a standard cell layout using a scaled enhancement circuit layout can improve the scaling down of a standard cell over the design of a standard cell layout according to a design rule.

Although FIGS. 3 and 4 illustrate the design of one golden scaling enhancement layout 110, it is not so limited. That is, in the target standard cell 100, an area having a structure different from the design rule violation required area 105 may be defined as an area that violates the additional design rule, and the scaling enhanced circuit layout may be designed.

Alternatively, in a target standard cell different from the target standard cell 100 of FIG. 3, a region having a structure different from the design rule violation requiring region 105 of FIG. 3 is defined as an area requiring additional design rule violation, It is of course possible to design a circuit layout.

In Fig. 5, the second scaling enhancement circuit layout 130 included in the second data file 130f may be a layout designed by optimizing the fabrication process for the above-mentioned additional design rule violation required area.

Referring to FIGS. 1 and 6, the first to fourth standard cell layouts 300, 310, 320, and 330 are defined using the design rule and the first data file 120f and the second data file 130f. (S110).

Referring to FIG. 6A, designing the first standard cell layout 300 using the design rule and the first data file 120f will be described as an example.

The first standard cell layout 300 may include a first area 300a, a second area 300b, and a third area 300c. The second area 300b of the first standard cell layout may be a region adjacent to the first area 300a of the first standard cell layout and the third area 300c of the first standard cell layout. The second area 300b of the first standard cell layout may be located around the first area 300a of the first standard cell layout and the third area 300c of the first standard cell layout.

The first area 300a of the first standard cell layout and the third area 300c of the first standard cell layout may be different areas of the first standard cell layout 300. [

The first area 300a of the first standard cell layout is designed using the first data file 120f. Designing the first area 300a of the first standard cell layout may be to place the first scaling enhancement circuit layout 120 in the first area 300a of the first standard cell layout.

In other words, since the integrated circuit designer receives the first scaling enhancement circuit layout 120 in graphical data format, the first scaling enhancement circuit layout 120 may include a first region 300a of the first standard cell layout As shown in FIG.

When designing the first area 300a of the first standard cell layout, the third area 300c of the first standard cell layout can also be designed. That is, the first scaling enhancement circuit layout 120 may be disposed in the third region 300c of the first standard cell layout.

Then, the second area 300b of the first standard cell layout is designed using design rules. More specifically, designing the second area 300b of the first standard cell layout may be performed using a design rule to define a first area 300a of the first standard cell layout in which the first scaling enhancement circuit layout 120 is disposed, And the third area 300c of the first standard cell layout.

When designing the second area 300b of the first standard cell layout, the first scaling enhancement circuit layout 120 disposed in the first area 300a and the third area 300c of the first standard cell layout, 1 < / RTI > standard cell layout 300 may be considered.

Next, a second standard cell layout 310 performing a function different from the first standard cell layout 300 and a second standard cell layout 310 performing a function different from that of the first standard cell layout 300 will be described with respect to designing the third standard cell layout 320 and the fourth standard cell layout 330 Explain.

The first through fourth standard cell layouts 300, 310, 320, and 330 may be standard cell layouts that perform different functions.

6 illustrates four standard cell layouts 300, 310, 320, and 330, it is for convenience of description only, and is not limited thereto. In addition, although FIG. 6 illustrates designing a standard cell layout using different first and second scaling enhancement circuit layouts 120 and 130, it is only for convenience of explanation, but is not limited thereto.

In FIG. 6B, the second standard cell layout 310 may include a first area 310a and a second area 300b. The second area 300b of the first standard cell layout may be located around the first area 300a of the first standard cell layout.

The second standard cell layout 310 may include one first scaling enhancement circuit layout 120, unlike the first standard cell layout 300. [

6A and 6B, the first standard cell layout 300 and the second standard cell layout 310, which perform different functions, may include the same first scaling enhancement circuit layout 120 have.

The design of the third standard cell layout 320 using the design rule, the first data file 120f and the second data file 130f will be described with reference to Fig. 6 (c).

The third standard cell layout 320 may include a first area 320a, a second area 320b, and a third area 320c. The second area 320b of the third standard cell layout may be a region adjacent to the first area 320a of the third standard cell layout and the third area 320c of the third standard cell layout. The second area 320b of the third standard cell layout may be located around the third area 320c of the third standard cell layout and the third area 320c of the third standard cell layout.

The first area 320a of the third standard cell layout is designed using the first data file 120f. Designing the first area 320a of the third standard cell layout may be to place the first scaling enhancement circuit layout 120 in the first area 320a of the third standard cell layout.

The third area 320c of the third standard cell layout is designed using the second data file 130f. Designing the third region 320c of the third standard cell layout may be to place the second scaled enhancement circuit layout 130 in the third region 320c of the third standard cell layout.

Then, the second area 320b of the third standard cell layout is designed using design rules. More specifically, designing the second region 320b of the third standard cell layout may include designing the first region 320a of the third standard cell layout in which the first scaling enhancement circuit layout 120 is located using design rules, And the third region 320c of the third standard cell layout in which the second scaling enhancement circuit layout 130 is disposed.

When designing the second region 320b of the third standard cell layout, the first scaling enhancement circuit layout 120, the second scaling enhancement circuit layout 130, and the surrounding patterns of the third standard cell layout 320 Etc. can be considered.

In Figure 6 (d), the fourth standard cell layout 330 does not include a scaling enhancement circuit layout, but can be designed entirely using design rules.

In this way, the designed first through fourth standard cell layouts 300, 310, 320 and 330 can be made into a graphic data format. The first through fourth standard cell layouts 300, 310, 320, and 330 of the created graphic data format may be provided to a designer designing a logic block layout.

Although not shown in FIG. 1, the design rule checker (DRC) can be used to check the complexity rules for each of the first through fourth standard cell layouts 300, 310, 320, 330.

When examining the design rules of each of the first through fourth standard cell layouts 300, 310, 320, 330, the first scaling enhancement circuit layout 120 and / or the second scaling enhancement circuit layout 130 are arranged Some of the standard cell layouts may not be inspected through the design rule checker.

The first scaling enhancement circuit layout 120 and / or the second scaling enhancement circuit layout 130 may be provided through the marker layers included in the first scaling enhancement circuit layout 120 and / or the second scaling enhancement circuit layout 130. [ It is possible to confirm the position in which it is disposed.

Or the second scaling enhancement circuit layout 120 and / or the second scaling enhancement circuit layout 130 when examining the design rules of each of the first through fourth standard cell layouts 300, 310, 320, Some of the standard cell layouts arranged may be processed to satisfy the design rule.

When examining the design rules for each of the first through fourth standard cell layouts 300, 310, 320, and 330, the design rule checking of the logic block layout may be omitted after designing the logic block layout described hereinafter have.

1, 6, and 7, a logic block layout 400 including first through fourth standard cell layouts 300, 310, 320, and 330 is designed.

The logic block designer places the first through fourth standard cell layouts 300, 310, 320, and 330 in the logic block layout 400 so as to create the logic integrated circuit to be implemented through the logic block layout 400 .

At least one of the standard cell layouts of the first through fourth standard cell layouts 300, 310, 320, 330 includes a first scaling enhancement circuit layout 120 and / or a second scaling enhancement circuit layout 130.

Thus, the logic block layout 400 includes a first scaling enhancement circuit layout 120 and / or a second scaling enhancement circuit layout 130. [ The first scaling enhancement circuit layout 120 and / or the second scaling enhancement circuit layout 130 are disposed in some areas of the logic block layout 400.

The logic block layout 400 thus designed can be made into a graphic data format. The logic block layout 400 of the created graphics data format may be provided to an integrated circuit manufacturer to manufacture integrated circuits.

Although not shown in FIG. 1, a design rule checker may be used to examine the complexity rules for the logic block layout 400.

When inspecting the design rule of the logic block layout 400, the portion of the logic block layout 400 where the first scaling enhancement circuit layout 120 and / or the second scaling enhancement circuit layout 130 are arranged is a design rule It may not be checked by a checker.

Alternatively, when inspecting the design rule of the logic block layout 400, the portion where the first scaling enhancement circuit layout 120 and / or the second scaling enhancement circuit layout 130 are disposed is determined to satisfy the design rule It is possible.

Referring to Figures 1, 8 and 9, a first scaling enhancement circuit layout 120 included in the logic block layout 400 may be used to design the standard cell layout 300, 310, 320, 330, It is checked whether the layout 400 has been changed in the course of designing (S130).

The original of the first scaling enhancement circuit layout 120 included in the logic block layout 400 may be the golden scaling enhancement layout 110 described with reference to FIG. That is, using the golden scaling enhancement layout 110, it can be determined whether the first scaling enhancement circuit layout 120 included in the logic block layout 400 has been changed in the standard cell layout or logic block layout design process.

The design process of the first standard cell layout 300 shown in FIG. 6 (a) will be exemplarily described with reference to the designing process. The second region 300b of the first standard cell layout is designed after the first scaling enhancement circuit layout 120 is disposed in the first region 300a of the first standard cell layout.

That is, in the process of designing the second area 300b of the first standard cell layout using the design rule, the first scaling enhancement (not shown) placed in the first area 300a of the first standard cell layout The circuit layout 120 can be changed.

The first scaled enhancement circuit layout 120 is optimized for layout from a manufacturing process perspective. When the first scaling enhancement circuit layout 120 is changed during the design process and the photomask is fabricated using the modified first scaling enhancement circuit layout, the logic integrated circuit fabricated through such a photomask is operated as intended by the designer . Since the photomask is fabricated using the changed first scaling enhancement circuit layout, there is a possibility that the logic integrated circuit fabricated using the first scaling enhancement circuit layout has also been changed.

By verifying the first scaling enhancement circuit layout 120 included in the logic block layout 400 using the golden scaling enhancement layout 110, the stability of the fabrication process and the performance of the logic integrated circuit fabricated through the logic block layout Can also be guaranteed.

4, 8 and 9, an integrated circuit verification system 500 for verifying a designed logic block layout 400 includes a first input module 510, a first storage 530, (520), and a display unit (540).

The first input module 510 may receive a logic block layout 400 that includes a first scaling enhancement circuit layout 120. The first input module 510 can be input in a graphic data format.

The first storage unit 530 may be a portion in which the original scaling enhancement layout 110 is stored, but is not limited thereto. In other words, it is needless to say that there may be a separate input module receiving the input of the scaling enhancement layout 110, which is the original of the first scaling enhancement circuit layout 120.

The verification module 520 compares the first scaling enhancement circuit layout 120 in the logic block layout 400 received by the first input module 510 with the golden scaling enhancement layout 110 of the first storage 530 To determine whether the first scaled enhancement circuit layout 120 has been deformed in the design process.

The verification module 520 can determine which location in the logic block layout 400 the first scaling enhancement circuit layout 120 is located by identifying the marker layers included in the first scaling enhancement circuit layout 120 have.

The display unit 540 may indicate whether the first scaling enhancement circuit layout 120 that has been verified through the verification module 520 is deformed.

A method of designing an integrated circuit according to another embodiment of the present invention will be described with reference to FIGS. 1 to 12. FIG.

10 is a flowchart illustrating a method of designing an integrated circuit according to another embodiment of the present invention. 11 is a view for explaining S220 of FIG. 12 is a block diagram for explaining an integrated circuit design system for executing S22 of Fig.

Referring to FIGS. 1 to 9, the standard cell layouts 300, 310, 320, and 330 are designed using the first scaling enhancement circuit layout 120 and the design rule (S200). At least one of the standard cell layouts 300, 310, 320, and 330 includes a first scaling enhancement circuit layout 120.

The first scaled enhancement circuit layout 120 may include a marker layer (115 in FIG. 4).

Designing the standard cell layouts 300, 310, 320, and 330 is substantially the same as that described with reference to FIGS. 1 and 6, and will be omitted hereafter.

The logic block layout 400 including the standard cell layouts 300, 310, 320, and 330 is then designed (S210).

10 and 11, the first scaling enhancement circuit layout 120 in the logic block layout 400 is replaced with the updated first scaling enhancement circuit layout 121. [ Thereby, the logic block layout 400 is updated (S220).

First, similar to that described with reference to FIGS. 2-4, the first scaling enhancement circuit layout 120 is updated to design the updated first scaling enhancement circuit layout 121. The first scaling enhancement circuit layout 120 is updated to reflect the changed manufacturing process or the like when the manufacturing process used to optimize the first scaling enhancement circuit layout 120 and the like have changed.

Thus, the updated first scaling enhancement circuit layout 121 represents the same design rule violation required area 105 as the first scaling enhancement circuit layout 120. [

The updated first scaling enhancement circuit layout 121 may be used to update the golden scaling enhancement layout 110.

11 (a) and (b), the first scaling enhancement circuit layout 120 included in the logic block layout 400 is removed. Of the logic block layout 400, the portion where the first scaled enhancement circuit layout 120 is removed may be blank.

In the logic block layout 400, where the first scaling enhancement circuit layout 120 is located can be identified using the marker layer included in the first scaling enhancement circuit layout 120.

11 (b) and (c), the first scaling enhancement circuit layout 120 is removed and the updated first scaling enhancement circuit layout 121 is placed in a blank area.

This allows the updated logic block layout 401 to be designed.

The logic block layout can be redesigned through a simple process of updating the scaled enhancement circuit layout and exchanging the updated scaled enhancement circuit layout with the existing scaled enhancement circuit layout, as the manufacturing process changes.

If you do not use the scaling enhancement layout of the graphical data format, it will take a very long time to update the logic block layout. That is, the design rule manual is updated, and the process design kit (PDK) is updated. Then, using the updated process design kit or the like, the standard cell layouts are updated and the logic block layout is updated using the updated standard cell layout.

Although the logic block layout is updated through this series of complicated procedures, by using the integrated circuit design method of the present invention, by simply replacing the scaling enhancement layout, the logic block layout can be updated.

11 and 12, the integrated circuit design system 600 for updating the logic block layout 400 includes a second input module 610, a second storage unit 620, an update module 630, etc. . ≪ / RTI >

The second input module 610 may receive the updated first scaling enhancement circuit layout 121 generated by updating the first scaling enhancement circuit layout 120. The second input module 610 may be input in a graphic data format.

The second storage unit 620 may be a portion in which the logic block layout 400 including the first scaling enhancement circuit layout 120 is stored, but is not limited thereto. In other words, it is needless to say that a separate input module may be additionally provided for receiving the logic block layout 400 including the first scaling enhancement circuit layout 120.

The update module 630 finds and removes the first scaling enhancement circuit layout 120 in the logic block layout 400 and updates the first scaled enhancement circuit layout 120 in a location where the first scaling enhancement circuit layout 120 is removed 121 can be disposed.

The update module 630 can identify which location in the logic block layout 400 the first scaling enhancement circuit layout 120 is located by identifying the marker layers included in the first scaling enhancement circuit layout 120 have.

The update module 630 may also send the updated logic block layout 401 to the second storage unit 620 so that the updated logic block layout 401 is stored in the second storage unit 620, It is not. That is, the update module 630 may send the updated logic block layout 401 to a separate storage module or output, or may store the updated logic block layout 401 itself.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

100: target standard cell 105: design rule violation required area
110: Golden Scaling Enhancement Layout 120f, 130f: Data File
120, 130: scaling enhanced circuit layout
300, 310, 320, 330: Standard cell layout
400: Logic block layout 500: Integrated circuit verification system
600: Integrated Circuit Design System

Claims (20)

Receiving a data file including a scaling enhanced circuit layout,
Designing a first standard cell layout using a design rule and the data file,
Wherein the scaling enhancement circuit layout comprises a design rule violation layer,
Designing the first standard cell layout
Designing a first area of the first standard cell layout using the data file,
And designing a second region of the first standard cell layout using the design rules. The method according to claim 1,
Further comprising checking a design rule of the first standard cell layout using a design rule checker,
Wherein inspecting the design rules of the first standard cell layout comprises un-checking a first region of the first standard cell layout. The method according to claim 1,
Wherein the scaling enhancement circuit layout comprises a marker layer. The method according to claim 1,
Wherein designing the first region of the first standard cell layout places the scaling enhanced circuit layout in a first region of the first standard cell layout. The method according to claim 1,
Further comprising designing a second standard cell layout different from the first standard cell layout. 6. The method of claim 5,
Designing the second standard cell layout
Designing a first area of the second standard cell layout using the data file,
And designing a second region of the second standard cell layout using the design rule. The method according to claim 6,
Wherein the first region of the first standard cell layout and the first region of the second standard cell layout comprise the same layout. The method according to claim 1,
Further comprising designing a logic block layout comprising the first standard cell layout,
Wherein the first standard cell layout comprises the scaling enhancement circuit layout,
Wherein the scaling enhancement circuit layout is disposed in a portion of the logic block layout. 9. The method of claim 8,
Define a region that violates the design rule in a part of the standard cell,
Optimizing the manufacturing process for the areas where the design rule violation is required, designing the design rule violating layer,
Designing the scaled enhancement circuit layout including the confined rule violation layer,
Further comprising designating the scaling enhancement circuit layout as a golden scaling enhancement layout. 10. The method of claim 9,
Further comprising using the Golden Scaling Enhancement Layout to check whether the scaled enhancement circuit layout included in the logic block layout has been modified in the process of designing the first standard cell layout. The method according to claim 1,
Wherein the scaling enhancement circuit layout is part of a standard cell layout performing a specific function. The method according to claim 1,
Wherein the data file is in the form of a graphic database system (GDS) file, a GDS instance file, or a hard macro file. Designing a standard cell layout that includes a first scaled enhancement circuit layout,
Design a logic block layout including the standard cell layout,
And replacing the first scaling enhancement circuit layout in the logic block layout with a second scaling enhancement circuit layout to update the logic block layout. 14. The method of claim 13,
Wherein the standard cell layout includes a first area and a second area located around the first area,
Designing the standard cell layout
Arranging the first scaling enhancement circuit layout in a first region of the standard cell layout,
And designing the second area of the standard cell layout using a design rule. 14. The method of claim 13,
Updating the logic block layout
And removing the first scaling enhancement circuit layout included in the logic block layout and then placing the second scaling enhancement circuit layout at a location where the first scaling enhancement circuit layout is removed. 14. The method of claim 13,
Wherein the first scaling enhancement circuit layout comprises a marker layer,
Wherein updating the logic block layout includes identifying the location of the first scaled enhancement circuit layout using the marker layer. Receiving a first data file including a first scaling enhancement circuit layout and a second data file including a second scaling enhancement circuit layout,
Designing a first standard cell layout using the design rule and the first data file,
Designing a second standard cell layout using the design rule and the second data file,
Designing a logic block layout including the first standard cell layout and the second standard cell layout,
Wherein the first scaling enhancement circuit layout comprises a first design rule violation layer and the second scaling enhancement circuit layout comprises a second design rule violation layer,
Designing the first standard cell layout comprises designing a first region of the first standard cell layout using the first data file and designing a second region of the first standard cell layout using the design rules , ≪ / RTI >
Designing the second standard cell layout may include designing a first region of the second standard cell layout using the second data file and designing a second region of the second standard cell layout using the design rule The integrated circuit design method. 18. The method of claim 17,
Wherein the first standard cell layout and the second standard cell layout are standard cell layouts that perform different functions. 19. The method of claim 18,
Wherein the first scaling enhancement circuit layout and the second scaling enhancement circuit layout are the same layout. A storage module in which a logic block layout including a first scaled enhancement circuit layout is stored;
An input module receiving a second scaling enhancement circuit layout updated with the first scaling enhancement circuit layout; And
And an update module that removes the first scaling enhancement circuit layout from the logic block layout and places the second scaling enhancement circuit layout at a location where the first scaling enhancement circuit layout is removed.

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