JP2000148821A - Method for designing layout of semiconductor circuit and storage medium recorded with the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the layout area of a building block type semiconductor integrated circuit by reducing the areas of functional blocks and wiring channels at the time of designing the layout of the circuit. SOLUTION: When three kinds of contact cells respectively having square, rectangular, and crisscross contact margins are used around a contact hole in a method for designing layout of semiconductor integrated circuit, larger costs are successively added in the order of the contact cells having the horizontal rectangular shape, crisscross shape, square shape, and vertical rectangular shape, namely, in the order of the heights of the cells in step 4000. In the next step 4001, the contact cell having the horizontal rectangular shape and the lowest cost is selected and whether or not the selected contact cell meets a design rule is checked. When it is discriminated that the selected cell does not meet the design rule in step 4003, the process returns to the step 4001 to select another contact cell having the next lowest cost. After the selection, the process proceeds to the step 4003. In such a way, the steps 4001 and 4003 are repeatedly performed until a suitable contact cell is selected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a building block layout design method for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Generally, the manufacturing cost of a chip of a semiconductor integrated circuit is determined by keeping the manufacturing cost per unit area constant.
The larger the chip area, the higher the chip area. Also, as the chip area increases, the yield decreases and the manufacturing cost increases.
Therefore, in order to reduce the manufacturing cost of the semiconductor integrated circuit chip, it is necessary to minimize the chip area.

In a conventional layout design method for a semiconductor integrated circuit, attention is paid to reducing the area of a functional block in order to minimize the chip area. The area of the functional block has been minimized by setting the smallest possible interval in accordance with the spacing rules of the cells and wiring or the wiring grid.

[0004]

In order to minimize the layout area of a semiconductor integrated circuit, it is necessary not only to minimize the area of each functional block but also to minimize the area of a wiring channel. .

However, even if the distance between the terminals of the functional block is made as small as possible in accordance with the contact and wiring spacing rules as in the prior art, the area of the wiring channel can always be minimized. Not necessarily. This will be described with a specific example.

[0006] Today, with the progress of the semiconductor manufacturing process, various types of contact cells for connecting two wiring layers are employed, for example, a contact cell having a square, rectangular or cross-shaped contact margin. Exists. Now, if a horizontally long rectangular contact cell with the lowest height is used, the height of the wiring channel will be the lowest, but the distance between the terminals of the functional block will be long, and a square or vertically long rectangular contact cell will be used. Larger than when a cell is adopted. Therefore, when the number of terminals of the functional block is large, the layout area of the functional block itself may be increased. On the other hand, when a vertically long rectangular contact cell is used, the space between the terminals of the functional block is minimized. Therefore, even when the number of terminals of the functional block is large, the layout area of the functional block itself can be minimized. The area of the channel increases.

As described above, the distance between the terminals of the functional block is made as small as possible in accordance with the spacing rule of the contact cell and the wiring to minimize the area of the functional block as well as the wiring channel. If the area of the semiconductor integrated circuit (chip) is not minimized, the layout area of the semiconductor integrated circuit (chip) cannot be minimized.

Further, the conventional channel router which performs wiring between functional blocks in a building block system has no function of selectively using a plurality of types of contact cells for the purpose of reducing the wiring channel area. When used for wiring, a design rule error may occur or the wiring channel area may be increased as compared with the case where one type of contact cell is used.

Further, from the viewpoint of minimizing the layout area of the semiconductor integrated circuit by reducing the area of the wiring channel,
Looking at the state of the conventional wiring channel, wide power supply wiring and ground wiring are arranged in the wiring channel in order to stabilize the operation of a functional block such as a memory, so that the area of the wiring channel becomes large. In the layout design of the building block method, it is possible to recognize the layer, width, position, etc. of the power supply terminal of the functional block when wiring in the wiring channel, but it is not possible to recognize the power supply structure inside the functional block. In general, the power supply wiring and the ground wiring of the wiring channel are often arranged in parallel with the power supply wiring and the ground wiring inside the functional block, and the area occupied by the power supply wiring and the ground wiring as a whole increases. Furthermore, if the routing structure of the power supply wiring and the ground wiring in the wiring channel becomes complicated, the area of the wiring channel is increased, which causes an increase in the layout area of the entire semiconductor integrated circuit.

In view of the foregoing, an object of the present invention is to provide a layout design method for a semiconductor integrated circuit of a building block type, in which the area of a functional block and the area of a wiring channel are reduced, and It is to reduce the layout area as a whole.

[0011]

In order to solve the above-mentioned problems, in the present invention, a plurality of types of contact cells are appropriately formed according to the distance between terminals of a functional block or the shape of a contact margin. By properly using them, the area of the entire semiconductor integrated circuit is reduced. Further, the power supply wiring and the ground wiring inside the functional block and the power supply wiring and the ground wiring arranged in the wiring channel are arranged without waste, and the area of the whole semiconductor integrated circuit is reduced.

According to a first aspect of the present invention, there is provided a layout design method for a semiconductor integrated circuit, comprising arranging a plurality of functional blocks, and connecting the functional blocks to a wiring channel between the functional blocks. A layout design method of a building block type semiconductor integrated circuit in which wiring to be connected is provided, wherein a type of a contact cell connecting two wiring layers is determined according to a pitch of wiring connection terminals provided in each of the functional blocks. It is characterized by selecting.

According to a second aspect of the present invention, in the layout design method of the semiconductor integrated circuit according to the first aspect, the type of the contact cell includes a square, rectangular, and cross contact margin around the contact hole. It is characterized in that two or more of the three types of contact cells are provided.

According to a third aspect of the present invention, in the layout design method of the semiconductor integrated circuit according to the first or second aspect, a contact cell having a smaller height is selected as the terminal pitch of the functional block is longer. I do.

According to a fourth aspect of the present invention, there is provided a recording medium storing a layout design program for a semiconductor integrated circuit, wherein a plurality of functional blocks are arranged by a computer, and each of the functional blocks is arranged in a wiring channel between these functional blocks. A recording medium on which a layout design program for a building block type semiconductor integrated circuit for arranging wiring to be connected is recorded, wherein the design program comprises two or more wiring connection terminals provided in each of the functional blocks.
It is characterized in that a type of a contact cell connecting two wiring layers is selected.

According to a fifth aspect of the present invention, in the recording medium storing the semiconductor integrated circuit layout design program according to the fourth aspect, the design program is arranged such that the longer the terminal pitch of the functional block is, the higher the wiring channel height is. Is characterized by selecting a contact cell having a shape that can reduce the contact cell.

According to a sixth aspect of the present invention, there is provided a layout design method for a semiconductor integrated circuit, wherein a plurality of functional blocks are arranged,
A layout design method of a building block type semiconductor integrated circuit in which wiring connecting each of the functional blocks is wired to a wiring channel between these functional blocks,
When a contact cell that connects two wiring layers is located at the end of the wiring channel, one of a plurality of types of contact cells that are provided in advance is selected as the contact cell according to the width and height of the wiring channel. It is characterized by:

According to a seventh aspect of the present invention, there is provided a recording medium storing a semiconductor integrated circuit layout design program, wherein a plurality of functional blocks are arranged by a computer, and each of the functional blocks is arranged in a wiring channel between these functional blocks. A recording medium recording a layout design program of a building block type semiconductor integrated circuit for laying out wiring to be connected, wherein the design program is arranged such that a contact cell connecting two wiring layers is located at an end of the wiring channel. According to another aspect of the present invention, one of a plurality of types of contact cells provided in advance is selected as the contact cell according to the width and height of the wiring channel.

In a layout design method for a semiconductor integrated circuit according to the present invention, a plurality of functional blocks are arranged.
This is a layout design method of a building block type semiconductor integrated circuit in which wiring connecting each of the functional blocks is wired to a wiring channel between these functional blocks, wherein a plurality of types of connecting two wiring layers in the wiring channel are provided. The contact cell is costed according to the magnitude of the influence on the height of the wiring channel by the shape of the contact cell, and the contact cell existing in the wiring channel is initially replaced with a contact cell having the minimum cost. It is checked whether or not the cell satisfies the design rule, and if the design rule error has occurred, it is repeated to replace the contact cell with the next lowest cost and check whether or not the design rule is satisfied. It is characterized by.

According to a ninth aspect of the present invention, in the layout design method of a semiconductor integrated circuit according to the eighth aspect, the plurality of types of contact cells have square, rectangular, and cross-shaped contacts around the contact hole. It includes three types of contact cells having a margin.

According to a tenth aspect of the present invention, in the layout design method of the semiconductor integrated circuit according to the ninth aspect, among the three types of contact cells, the cost of a contact cell having a horizontally long rectangular contact margin is the smallest. The feature is that the cost of a contact cell having a vertically long rectangular contact margin is the largest.

In a recording medium storing a semiconductor integrated circuit layout design program according to the present invention, a plurality of functional blocks are arranged by a computer, and each of the functional blocks is arranged in a wiring channel between these functional blocks. A recording medium recording a layout design program of a building block type semiconductor integrated circuit for arranging wiring to be connected, wherein the design program comprises a plurality of types of contact cells that connect two wiring layers in the wiring channel. Depending on the magnitude of the influence on the height of the wiring channel due to its shape, the cost is set according to the magnitude of the influence on the height of the wiring channel, and the contact cell existing in the wiring channel is initially replaced with the contact cell with the minimum cost, and the design is performed with the replaced contact cell. Check if the rules are satisfied and If occurs Ruera, next to let me replaced with a small contact cell cost, it is characterized in that to repeat to check whether they meet the design rule.

According to a twelfth aspect of the present invention, there is provided the eleventh aspect.
3. The recording medium according to claim 1, wherein the design program has a square, rectangular, and cross-shaped contact margin around a contact hole among the plurality of types of contact cells. Among the types of contact cells, the cost of a contact cell having a horizontally long rectangular contact margin is minimized, and the cost of a contact cell having a vertically elongated rectangular contact margin is maximized.

According to a thirteenth aspect of the present invention, there is provided a layout design method for a semiconductor integrated circuit, wherein a plurality of functional blocks are arranged, and a wiring block for connecting the functional blocks to a wiring channel between these functional blocks is provided. A method for designing a layout of a semiconductor integrated circuit according to a method, wherein power supply wiring and ground wiring arranged in the wiring channel are moved into each of the functional blocks and added to each of the functional blocks.

The invention according to claim 14 is the invention according to claim 13.
In the layout design method for a semiconductor integrated circuit described above,
In each functional block, the horizontal or vertical position of the power supply wiring and the ground wiring added inside is set to the same position between the functional blocks.

According to a fifteenth aspect of the present invention, there is provided a recording medium on which a layout design program for a semiconductor integrated circuit is recorded, wherein a plurality of functional blocks are arranged by a computer, and each of the functional blocks is arranged in a wiring channel between these functional blocks. A recording medium recording a layout design program of a building block type semiconductor integrated circuit for laying out wiring to be connected, wherein the design program includes a power supply wiring and a ground wiring arranged in the wiring channel in each of the functional blocks. It is characterized by being moved and added within each functional block.

The invention according to claim 16 is the invention according to claim 15.
In a recording medium on which a layout design program for a semiconductor integrated circuit according to the above is recorded, the design program determines the horizontal or vertical position of a power supply wiring and a ground wiring added inside each functional block between the functional blocks. Are set at the same position.

The invention according to claim 17 is the invention according to claim 13.
Or the layout design method of a semiconductor integrated circuit according to 14, wherein a plurality of functional blocks are arranged, and a wiring for connecting each of the functional blocks is wired to a wiring channel between these functional blocks. In a layout design method, a power supply wiring and a ground wiring are arranged only on a wiring layer different from the wiring layer of the functional block.

The invention according to claim 18 is the invention according to claim 15.
Alternatively, in a recording medium recording a layout design program for a semiconductor integrated circuit according to 16, a computer arranges a plurality of functional blocks and wires wiring connecting the functional blocks to a wiring channel between these functional blocks. A recording medium recording a layout design program of a building block type semiconductor integrated circuit, wherein the design program arranges a power supply wiring and a ground wiring only in a wiring layer different from a wiring layer of the functional block. And

With the above configuration, in the inventions according to the first to fifth aspects, a contact cell having a smaller height is selected as the distance between the terminals of the functional block (terminal pitch) is longer. Therefore, even if the width of the selected contact cell is wide, as long as the contact cell is within the pitch of the terminals, the height of the wiring channel in which the contact cell is arranged is reduced, and the area of the wiring channel is reduced.

According to the present invention, when the contact cell is located at the end of the wiring channel, the contact cell having a low height is provided when the width of the wiring channel is wide and the height is low. On the other hand, if the width of the wiring channel is small and the height is high, a contact cell having a small width is selected, so that the enlargement of the area of the wiring channel is limited.

Furthermore, in the inventions according to the eighth to twelfth aspects, the contact cells are sequentially arranged starting from the contact cells having a small height and a small value, so that the area of the wiring channel can be effectively reduced. The layout is completed.

In addition, in the inventions according to the thirteenth to sixteenth aspects, since the power supply wiring and the ground wiring arranged in the wiring channel extend into the functional block, the number of power supply wirings and the like and the number of contact cells are reduced. The arrangement structure of the power supply wiring and the like is simplified, and the area of the wiring channel is reduced.

In the invention according to the seventeenth and eighteenth aspects, the power supply wiring and the ground wiring are arranged in a wiring layer different from the function block, and these power supply wiring and the ground wiring can pass over the function block. So,
Only the main line of the signal line connecting the functional blocks is arranged in the wiring channel, and the area of the wiring channel is reduced.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A layout design method of a semiconductor integrated circuit according to a first embodiment of the present invention will be described below. The design method according to the present embodiment is a computer layout method for functional blocks of the standard cell system, and a case where a plurality of contact cells exist will be described with reference to the drawings.

First, the contact cell will be described. The contact cell is used to connect two different wiring layers, and the contact cell connecting the wiring of the first wiring layer and the wiring of the second wiring layer is the first contact cell.
It comprises a rectangle of the wiring layer, a rectangle of the second wiring layer, and a contact hole connecting the first wiring layer and the second wiring layer. The rectangle of the first wiring layer and the rectangle of the second wiring layer are margins of the contact cells of the first and second wiring layers, respectively. This is necessary to ensure that the wiring of the layer and the wiring of the second wiring layer are connected.

In FIG. 1, reference numeral 11 denotes a square-shaped contact margin of the first wiring layer, 12 denotes a square-shaped contact margin of the second wiring layer, and 13 denotes a contact hole connecting the first and second wiring layers. , 14 indicate a rectangular contact margin of the first wiring layer, and 15 indicates a rectangular contact margin of the second wiring layer.

For the sake of simplicity, the size of each layout pattern shows the case where the minimum line width of the wiring is 2. Further, the minimum distance between the wirings in the first wiring layer and the second wiring layer is also set to 2.

The size of the layout pattern is such that the minimum line width of the wiring in the first wiring layer is W1, the width of the square contact margin of the first wiring layer is W11, and the height is H11 (W
11 = H11), the width of the rectangular contact margin of the first wiring layer is W12, and the height is H12 (W12> H1).
2) If the width of the contact hole connecting the first wiring layer and the second wiring layer is W31 and the height is H31, W31 ≦
W1 <W11 <W12, H31 ≦ W1 ≦ H12 <H11
Shall be satisfied.

Similarly, the minimum line width of the wiring in the second wiring layer is W2, the width of the square contact margin of the second wiring layer is W21, the height is H21 (W21 = H21), and the height of the second wiring layer is W21. The width of the rectangular contact margin is W22,
If the height is H22 (W22> H22), the width of the contact hole connecting the first wiring layer and the second wiring layer is W31, and the height is H31, W31 ≦ W2 <W21 <W22, H
It is assumed that the condition of 31 ≦ W2 ≦ H22 <H21 is satisfied.

In each of the plurality of functional blocks, a terminal is set as a signal line outlet at a boundary where the signal line is drawn from the functional block in order to connect a signal line with another functional block. I do.

The size of the functional block may be larger than a desired size depending on the number of terminals, the distance between terminals, the direction in which signal lines are led out, the contact cells used for leading out signal lines, and the like. For this reason, to minimize the area of the functional block, the number of terminals, the direction in which the signal lines are drawn,
In consideration of the minimum spacing rule between the contact cell used for leading out the signal line and the wiring, the distance between the terminals needs to be set to an optimum distance.

Further, if a contact cell corresponding to the distance between terminals is used, the area of a region required for connecting the wiring of the first wiring layer and the wiring of the second wiring layer can be minimized, and the semiconductor integrated circuit can be reduced. The entire layout area can be reduced.

Hereinafter, when determining the interval between the terminals of the functional block, the layout area of the functional block and the semiconductor integrated circuit (chip) is minimized in consideration of the shape of the contact cell used for leading the signal line. A method for performing the above will be described.

FIG. 15 is a flowchart of a layout design method for a functional block of a semiconductor integrated circuit according to the first embodiment of the present invention. This flowchart is realized by a layout design program, and is provided by being recorded on a recording medium.

In FIG. 15, the data input step 10
In 00, a netlist that is logical connection information in a functional block, standard cell data that is physical circuit information, a wiring layer, a minimum wiring width, a minimum spacing between wirings,
Technology data of the design process such as contact cells,
The number of cell stages of the functional block, the designation of the upper, lower, left, and right sides of the functional block on which the input / output terminals are to be placed, and the layout and wiring parameters for controlling the wiring are input.

Next, in step 1001, standard cells are arranged according to the number of cell stages specified by parameters, and input / output terminals are arranged on the specified sides.
Further, the minimum value of the width and height of the functional block is determined according to the cell arrangement.

Subsequently, in a schematic wiring step 1002,
Specify the wiring route according to the netlist. At the time when the schematic wiring is completed, the width and height of the functional block are substantially determined.

Further, in step 1003, when there are a plurality of types of contact cells, it is determined which type of contact the terminal interval (terminal pitch) of the functional block should be. Hereinafter, a method of calculating the optimum pitch of the terminals of the functional block will be described.

Assuming that the number of terminals arranged on each side of the functional block is Np, the length of the side of the functional block is Wb, and no terminals are set at the four corners of the functional block, The minimum interval Sp up to is represented by Sp = Wb / (Np + 1).

In step 1001, the number Np of terminals arranged on each side is determined. In step 1002, the width and height of the functional block are substantially determined, and the length Wb of the side is also a constant. The value of the interval Sp is determined.

FIG. 2 shows the contact margin of the wiring layer,
The contact cells 21 to 23 each having a square shape, a cross shape, and a horizontally long rectangular shape in combination with a contact hole connecting two wiring layers are shown. The square contact cell 21 has a square margin of the first wiring layer,
It is composed of a square margin of the second wiring layer and a square contact hole connecting the first wiring layer and the second wiring layer. The cross-shaped contact cell 22
Is composed of a horizontally long rectangular margin of the first wiring layer, a vertically long rectangular margin of the second wiring layer, and a square contact hole connecting the first wiring layer and the second wiring layer. Furthermore, the horizontally long rectangular contact cell 23
Is composed of a horizontally-long rectangular margin of the first wiring layer, a horizontally-long rectangular margin of the second wiring layer, and a square contact hole connecting the first and second wiring layers.

FIG. 3 shows a spacing rule of the square contact cell 21 shown in FIG.
Indicates that the minimum distance between the centers of one comrade is 5. FIG. 4 shows a square contact cell 21 of FIG.
Indicates that the minimum distance from the center of the first wiring layer to the center of the minimum width wiring of the first wiring layer (or the minimum width wiring of the second wiring layer) is 4.5. FIG. 5 shows the spacing rule of the cross-shaped contact cells 22 of FIG. 2, and shows that the minimum distance between the centers of the contact cells 22 is eight. FIG. 6 shows the cross-shaped contact cell 22 of FIG.
From the center of the first wiring layer to the center of the minimum width wiring of the first wiring layer (or the minimum width wiring of the second wiring layer). FIG. 7 shows the spacing rule of the horizontally long rectangular contact cells 23 in FIG. 2, and shows that the minimum distance between the centers of the contact cells 23 is eight. FIG. 8 shows that the minimum distance from the center of the horizontally long rectangular contact cell 23 in FIG. 2 to the center of the minimum width wiring of the first wiring layer (or the minimum width wiring of the second wiring layer) is six. Indicates that there is. FIG. 9 shows a case where the horizontally long rectangular contact cell 23 shown in FIG. 2 is 90 ° (or 270 °).
When rotated, the minimum distance between the centers of the vertically long rectangular contact cells 23 is 4.

As can be seen from FIGS. 3 to 9, the minimum distance between terminals can be selected from five types of 4, 4.5, 5, 6, and 8.

Since a contact cell is used when connecting a terminal of the first wiring layer to a wiring of the second wiring layer, an area S required for connecting the wiring of the first wiring layer and the wiring of the second wiring layer is used. Is the distance from the terminal to the contact cell, Dv
Assuming that p and the length of the side of the functional block are Wb, S = Dvp × Wb Since Wb is a constant after the general wiring, S = c × Dvp (c: constant). , The distance Dvp from the terminal to the contact cell must be minimized.

If Sp ≧ 8, the minimum terminal interval is set to 8. When the minimum distance between the terminals is 8, to connect the terminals of the first wiring layer to the wiring of the second wiring layer, as shown in FIG. The distance Dvp to the contact cell is minimized.

In the case of 6 ≦ Sp <8, if the minimum distance between the terminals is set to 6, in order to connect the terminals of the first wiring layer to the wiring of the second wiring layer, it is necessary to use the square contact cell 21 or the horizontally long contact cell 21. Although it is possible to use the rectangular contact cell 23, as can be seen from FIGS. 11 and 12, when the square contact cell 21 is used, the distance Dvp from the terminal to the contact cell is minimized. In this case, even if the minimum distance between terminals is 5, the same holds true.
If Sp <8, the minimum terminal interval is set to 5.

In the case of 4.5 ≦ Sp <5, when the minimum distance between the terminals is set to 4.5, the terminals of the first wiring layer are connected to the second terminals.
In order to connect to the wiring of the wiring layer, it is possible to use a square contact cell 21 or a vertically long rectangular contact cell 23. As can be seen from FIG. 13 and FIG. The use of the cell 23 minimizes the distance Dvp from the terminal to the contact cell. In this case, the same is true even when the minimum terminal interval is set to 4. Therefore, if 4 ≦ Sp <5, the minimum terminal interval is set to 4.

Once the minimum terminal distance Sp is determined, FIG.
In the detailed wiring step 1004, detailed wiring is performed to complete the layout of the functional blocks. Then, in the data output step 1005, the completed layout result is output.

Since the sizes of the wiring layers, contact cells, and layout patterns depend on the process of manufacturing the semiconductor integrated circuit, the names and numbers of the wiring layers and contacts described in the present embodiment are simply described. This is not intended to limit the names and numbers of wiring layers and contacts in an actual semiconductor process and the size of a layout pattern.

The effect of the present embodiment is similarly exerted when applied to a contact cell connecting an arbitrary n-th wiring layer and an (n + 1) -th wiring layer.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
A layout design method of a semiconductor integrated circuit according to the embodiment using a computer will be described with reference to the drawings. In the present embodiment, an object is to reduce the area of each wiring channel by properly using a plurality of types of contact cells in each wiring channel.

In this embodiment, the conditions for contacts and wiring are exactly the same as those in the first embodiment.

FIG. 16 shows a simplified layout of a one-chip semiconductor integrated circuit. In FIG.
BL3 to PAD3 are functional blocks, PAD1 to PAD4 are input / output circuit blocks of the semiconductor integrated circuit, and Ch1 to Ch6 are wiring channels, which are areas through which signal lines, power supply wirings, and ground wirings pass to connect the function blocks. is there.

FIG. 17 is a flowchart showing a layout design method for a semiconductor integrated circuit according to the second embodiment of the present invention. This flowchart is realized by a layout design program, and is provided by being recorded on a recording medium.

In FIG. 17, a data input step 20
In 00, a netlist, which is logical connection information between functional blocks in one chip, the shape of functional blocks, physical information such as wiring layers, wiring layers, minimum wiring width, minimum spacing between wirings, and contacts Enter the technology data for the cell and other design processes.

In the next function block arrangement step 2001, a plurality of function blocks are arranged.

Subsequently, a wiring channel setting step 200
In step 2, a wiring channel is set, and in the general wiring step 2003, it is determined which wiring channel all wirings pass through. Next, detailed wiring step 2004
Then, the signal lines are wired for each wiring channel according to the technology rule of the physical process.

Thereafter, a wiring channel adjustment step 200
In 5, the area of the wiring channel is changed by adjusting the positions of the floating terminals at the left and right ends of the wiring channel. Here, the floating terminal is a terminal provided on a wiring passing through the left and right ends of the wiring channel, and is a virtual substance having no substance.

FIG. 18 is an enlarged view of the right end of the wiring channel after the detailed wiring. The height and width of the wiring channel are clarified using this figure. As shown in the figure, the wiring channels are fixed terminals P300 and P30 whose arrangement positions do not change.
1 and a floating side where floating terminals FP300 to FP302 whose placement positions are not determined exist. In this two-dimensional plane, the fixed side is expressed as a width, and the floating side is expressed as a height. In terms of the x and y planes, the x axis is set on the fixed side and the y axis is set on the floating side. In FIG.
VIA 300 to VIA 302 are the smallest virtual contact cells both vertically and horizontally, and it is necessary to always replace them with any of the three types of contact cells 21 to 23 shown in FIG.

The floating terminal F located at the right end of the wiring channel
P300 is a horizontal wiring LH300 of the first wiring layer.
And the contact cell VIA300. Similarly, the floating terminal FP301 is connected to the horizontal wiring LH301 of the first wiring layer and the contact cell VIA301.
Connected by The floating terminal FP302 is
The wiring LH302 of the first wiring layer in the horizontal method is connected to the contact cell VIA302.

To minimize the wiring channel height,
As shown in FIG. 19, contact cells VIA300 to VIA300V
The IA 302 is replaced with a horizontally long rectangular contact cell 23 having the minimum height shown in FIG. The replaced contact cells VIA 310 to VIA 312 are
The design rule of the minimum spacing between the wiring LV300 of the wiring layer and the wiring LV300 is not observed.

Therefore, as shown in FIG. 20, contact cells VIA 310 to VIA 312 and floating terminal FP 3
00 to FP302 are moved in the left-right direction to a position that satisfies the design rule with the minimum distance from the wiring LV300. In this case, the width of the wiring channel increases by four.

Next, referring to FIGS. 21 to 23, the horizontally long rectangular contact cell 23 is connected to the left and right ends of the horizontal wiring channel or the floating terminals at the upper and lower ends of the vertical wiring channel. The following describes how much area reduction effect is obtained by using the method.

The horizontal width of the wiring channel is Wch, the minimum distance between the first wiring layers is WS, the height of the square contact cell 21 is WV1, and the horizontally long rectangular contact cell 23 is formed.
Height of WV3, vertically long rectangular contact cell 2
Assuming that the height of No. 3 is WV4, as shown in FIG. 21, the area Sch1 of the wiring channel when the vertically long rectangular contact cell 23 is used is expressed by the following equation.

Sch1 = (2 × WS + WV4) × Wch Since WS = 2 and WV4 = 6, the area Sch1 of the wiring channel becomes Sch1 = 10 × Wch.

As shown in FIG. 22, when a square contact cell 21 is used, the width of the wiring channel increases by 1, and the area Sch2 of the wiring channel is expressed by the following equation.

Here, Sch2 = (2 × WS + WV1)
× (Wch + 1) Since WS = 2 and WV1 = 3, the area Sch2 of the wiring channel becomes Sch2 = 7 × (Wch + 1).

As shown in FIG. 23, when a horizontally long rectangular contact cell 23 is used, the width of the wiring channel increases by 4 and the area of the wiring channel Sch3
Is represented by the following equation.

Sch3 = (2 × WS + WV3) × (Wch + 4) Here, since WS = 2 and WV3 = 2, the area Sch3 of the wiring channel becomes Sch3 = 6 × (Wch + 4).

For Sch1> Sch3, 10 × Wch> 6 × (Wch + 4) 4 × Wch> 24 Wch> 6 For Sch2> Sch3, 7 × (Wch + 1)> 6 × (Wch + 4) Wch> 24 Under the condition of Wch> 24, the wiring channel area Sch3
Is the smallest.

When the width of the wiring channel is 24, the condition that the minimum wiring width is 2 and the minimum spacing is 2 is that there is only an interval of up to eight vertical wires in the vertical direction. In the design, as shown in FIG. 23, when a horizontally long rectangular contact cell 23 is used, the area of the wiring channel is minimized.

The extent to which the area is reduced will be described below. When the width Wch of the wiring channel is sufficiently large, Sch1: Sch2: Sch3 = 10: 7: 6 = 1.67: 1.17: 1, which is compared with the case where the square-shaped contact cell 21 is used. Can also be 17% smaller.

Next, in FIG. 17, after the wiring channel width adjusting step 1005, the contact cell is optimized in a contact cell optimizing step 2006.

The contact cell optimizing step 200
FIG. 24 shows the details of the process 6. In the figure, in a contact cell costing step 4000, costing is performed according to the height of the contact cell. The details of this costing will be described below.

When the priority direction of the wiring in the first wiring layer is the horizontal direction and the priority direction of the wiring in the second wiring layer is the vertical direction, usually, the height of the wiring channel is mainly determined in the horizontal direction. This is the wiring of the first layer. However, the wiring in the horizontal direction is not 100% of the wiring in the first wiring layer, and the ratio is very small. However, the wiring in the horizontal direction is not connected to the wiring in the second wiring layer because the contact resistance is minimized to reduce the contact resistance. Wiring may be used. Therefore, it is necessary to consider the influence of the wiring of the second wiring layer.

The square contact cell 2 shown in FIG.
The height of 1 is 3 for both the first wiring layer and the second wiring layer. The cost of the square contact cell 21 is set to 3.3.

The cross-shaped contact cell 22 shown in FIG.
Is the first height when there is only the wiring of the first wiring layer above and below.
The height is 2 which is the height of the wiring layer, but becomes 6 which is the height of the second wiring layer when there are wires and contact cells of the second wiring layer above and below. Therefore, the cross-shaped contact cell 22
Is 2.6.

Since the height of the horizontally long rectangular contact cell 23 shown in FIG. 2 is 2 for both the first wiring layer and the second wiring layer, the cost of this horizontally long rectangular contact cell 23 is 2. Let it be 2.

Since the height of the vertically long rectangular contact cell is 6 for both the first wiring layer and the second wiring layer, the cost of this vertically long rectangular contact cell is 6.6.

Next, in FIG. 24, in a contact cell replacement step 4001, the contact cells are replaced in ascending order of cost. So at first,
Replace with a horizontally long contact cell 23. This replacement of the contact cell is performed for the virtual contact cell used in the detailed wiring, which is the smallest in both the vertical and horizontal directions, and the contact cell causing the spacing error.

FIG. 25 shows the result of the detailed wiring of the wiring channel. In the figure, LH400 to LH403 are the first
LV400 to LV402 are vertical wirings of the second wiring layer, LV403 to LV405 are vertical wirings of the first wiring layer, and P400 to P402 are terminals of the second wiring layer of the functional block BL1. , P403-P4
05 is a terminal of the first wiring layer of the functional block BL2, VIA
400 to VIA 405 are the smallest virtual contact cells both vertically and horizontally, and must be replaced with the three types of contact cells 21 to 23 shown in FIG.

In order to minimize the height of the wiring channel shown in FIG. 25, virtual contact cells VIA400 to VIA400-V
As shown in FIG. 26, the IA 405 is replaced with a horizontally long rectangular contact cell 23 having the minimum cost, and is referred to as contact cells VIA 410 to VIA 415.

In a design rule check step 4002 in FIG. 24, it is checked whether or not a contact cell has caused a spacing error in the horizontal direction, and a list is made so that the contact cell having a spacing error can be recognized. .

More specifically, contact cell VI in FIG.
It is checked whether A410 to VIA415 have caused a design rule error in the horizontal direction, and the following design rule error can be confirmed.

That is, the minimum distance between the contact cell VIA 410 and the wiring LV 401 is 0, and the minimum distance 2
Is not satisfied, it is determined that a spacing error has occurred. Similarly, contact cell VIA41
Since the minimum interval between 1 and the wiring LV400 is 0 and does not satisfy the minimum interval 2, it is determined that a spacing error has occurred. Further, the contact cell VI
The minimum distance between A412 and the wiring LV402 is 0,
Since the minimum interval 2 is not satisfied, it is determined that a spacing error has occurred. In addition, since the minimum interval between the two contact cells VIA 413 and VIA 414 is 0 and does not satisfy the minimum interval 2, it is determined that a spacing error has occurred. Also,
Since the minimum interval between the two contact cells VIA 414 and VIA 415 is 0 and does not satisfy the minimum interval 2, it is determined that a spacing error has occurred. Therefore, all contact cells VIA shown in FIG.
Each of 410 to VIA 415 is listed as a contact cell having a spacing error.

Since there is a contact cell causing a spacing error, the contact cell V listed as the contact cell causing the spacing error is determined in step 4003 of FIG.
A contact cell replacement step 4001 is executed for the IAs 410 to VIA 415.

As shown in FIG. 27, contact cells VIA410 to VIA4 having a spacing error have occurred.
15 is replaced by the next-highest cross-shaped contact cells VIA420 to VIA425.

Again, design rule check step 4
002, the cross-shaped contact cells VIA420 to VIA42 obtained by replacing the contact cells.
5 checks whether a design rule error has occurred in the horizontal direction. That is, the contact cell VIA42
The margin of the second wiring layer of 0 and the wiring LV401 satisfy the minimum distance 2. The margin of the second wiring layer of the contact cell VIA421 is the wiring LV400 and the wiring LV.
402 and the minimum interval 2 is satisfied. Margin of second wiring layer of contact cell VIA422 and wiring LV
401 satisfies the minimum interval 2. Since the contact cells VIA420, VIA421, and VIA422 satisfy the design rule, the replacement of the contact cells is not performed thereafter.

The two contact cells VIA423, VIA
Since the minimum interval between A424 is 0 and does not satisfy the minimum interval 2 of the second wiring layer, it is determined that a spacing error has occurred. Similarly, the minimum interval between the two contact cells VIA 424 and VIA 425 is 0, which does not satisfy the minimum interval 2 of the second wiring layer, so that it is determined that a spacing error has occurred. FIG.
Contact cells VIA423, VIA424, V
Each of the IAs 425 is listed as a contact cell having a spacing error.

Since there is a contact cell in which a spacing error has occurred, a contact cell replacement step 4001 is performed for the contact cells VIA 423, VIA 424, and VIA 425 in which the spacing error has occurred, as determined in step 4003 of FIG. Execute That is, as shown in FIG. 28, the contact cells VIA 423 and V
IA 424, VIA 425, followed by square contact cells VIA 433, VIA 434,
Replace with VIA435.

Thereafter, in a design rule check step 4002, as shown in FIG. 28, the square-shaped contact cells VIA433, VIA433
It is checked whether the IA 434 and the VIA 435 have not caused a design rule error in the horizontal direction. Where 2
Since the minimum interval between the contact cells VIA433 and VIA434 is 0, which does not satisfy the minimum interval 2 of the second wiring layer, a spacing error occurs. Also, two contact cells VIA434 and VIA435
Since the minimum interval between them is 0 and does not satisfy the minimum interval 2 of the second wiring layer, a spacing error occurs. These contact cells VIA433, VIA43
4. The VIA 435 is each listed as a contact cell having a spacing error.

Since there is a contact cell in which a spacing error has occurred, the contact cell VIA in the list is determined by the determination in step 4003 of FIG.
A contact cell replacement step 4001 is executed for the 433, the VIA 434, and the VIA 435. That is, as shown in FIG. 29, the contact cells VIA433, VIA434, V
The IA 435 is replaced by the next most expensive vertically long rectangular contact cells VIA 443, VIA 444, and VIA 4.
Replace with 45.

Design rule check step 4002
In FIG. 29, as shown in FIG. 29, a vertically long rectangular contact cell VIA in which the contact cell is replaced
433, VIA 434, and VIA 435 are checked to see if a design rule error has occurred in the horizontal direction.
Here, the margin of the second wiring layer of the contact cell VIA433 and the margin of the second wiring layer of the contact cell VIA434 satisfy the minimum interval 2. The margin of the second wiring layer of the contact cell VIA 434 and the margin of the second wiring layer of the contact cell VIA 435 satisfy the minimum distance 2. Therefore, all the contact cells shown in FIG. 29 satisfy the design rule error in the horizontal direction, and the contact cell optimizing step 2006 in FIG. 17 ends according to the determination in step 4003 in FIG.

Next, in the wiring channel minimization step 2007 of FIG. 17, the compaction of the wiring channel is performed to satisfy the vertical design rule of the wiring channel and to minimize the area of the wiring channel. The contact cells VIA433, VIA434, VIA43 shown in FIG.
In No. 5, although a design rule error has occurred in the vertical direction, the design rule in the vertical direction of the wiring channel is satisfied as shown in FIG. Is completed.

If it is confirmed in step 2008 of FIG. 17 that the wiring of all the wiring channels has been completed, in a data output step 2009, the layout result is output, and all the processing ends.

Next, the effect of reducing the area of the wiring channel by replacing the contact cell will be described with reference to FIGS.

FIG. 31 shows a contact cell 2 having a square shape.
The detailed wiring result of the conventional wiring channel using only 1 is shown. In the drawing, assuming that the wiring channel width is Wch and the wiring channel height is Hch, the area S1 of the wiring channel
S1 = Hch × Wch Here, Hch = 6 × WS + 3 × WV1 + 2 × WH WS = 2, WV1 = 3, and WH = 2, so that S1 = 25 × Wch.

FIG. 32 shows a detailed wiring result obtained by replacing the contact cells under the same conditions as in FIG. In the figure, the area S2 of the wiring channel is S2 = (6 ×
WS + 1 × WV1 + 4 × WH) × Wch = 23 × Wch
Becomes

The ratio between the area S1 and the area S2 of the wiring channel is as follows: S1: S2 = 25 × Wch: 23 × Wch = 1.09: 1.

From the above, it is understood that the area of the wiring channel can be reduced by about 10% by replacing the contact cell.

Further, as shown in FIG. 34, when the terminal pitch is 8 or more, the wiring channel area S3 is: S3 = (6 × WS + 1 × WV3 + 4 × WH) × Wch where WV3 = 2, S3 = 22 × Wch

The ratio between the area S1 and the area S3 of the wiring channel is as follows: S1: S3 = 25 × Wch: 22 × Wch = 1.14: 1. From the above, it is understood that in the best case, the area of the wiring channel can be reduced by 14%.

As described above, in each wiring channel,
By selectively using contact cells having different margins, the area of each wiring channel can be reduced, and the layout area of the semiconductor integrated circuit can be reduced.

Since the sizes of the wiring layers, contacts, and layout patterns depend on the process of manufacturing the semiconductor integrated circuit, the names and numbers of the wiring layers and contacts described in the present embodiment will simplify the description. The present invention does not limit the names and numbers of wiring layers and contacts in an actual semiconductor process and the size of a layout pattern.

(Third Embodiment) Next, a third embodiment of the present invention will be described.
A layout design method of a semiconductor integrated circuit by a computer according to the embodiment will be described with reference to the drawings.
This embodiment relates to an improvement in arrangement of a power supply wiring and a ground wiring.

In FIG. 34, BL701 is a functional block having a ring-shaped power supply wiring and a ground wiring in the periphery, and BL702 and BL703 are functional blocks in which the power supply wiring and the ground wiring are provided in a fixed direction. .

In the layout design of the ordinary building block system, the power supply wiring and the ground wiring pass through all the wiring channels.

Power supply wiring LV70 passing through wiring channel
1 and the ground wiring LV702 and the functional block BL7
01 internal power supply line LV711 and ground line LV7
12 are very close to each other. Therefore, FIG.
As shown in FIG. 5, if the power supply line and the ground line are shared, the power supply line LV701 and the ground line LV70
2 is not required, and the area of the wiring channel may be reduced.

However, in the layout design of the ordinary building block system, the power supply wiring and the ground wiring passing through the wiring channel are connected to the power supply wiring and the ground wiring inside the functional block through terminals of the functional block. For this reason, it is impossible to share the power supply wiring and the ground wiring as shown in FIG.

In FIG. 36, BL181 to BL184
Is a functional block, ch181 to ch183 are wiring channels, and Edge1 to Edge6 are boundaries of wiring channels. Each of the two functional blocks BL181 and BL184 includes two power supply wirings VDD and two ground wirings GND wirings. These two wirings are connected to each other by a connection wiring IH181, IL181, IH18
4, connected by IL184. The internal power supply wiring and ground wiring are respectively connected to the wiring channels ch181 to c181.
The two functional blocks are connected to each other using h183.

FIG. 37 is a layout diagram in which power supply wirings and ground wirings are connected between the two functional blocks. In the figure, Ch181 to Ch183 are wiring channels, BL181 to BL184 are functional blocks, VIA181 to VIA200 are contact cells connecting the power supply wiring of the first wiring layer and the wiring of the second wiring layer, L
H182, LH185, LH187, LH188, LH
189, LH190, LV181, LV182, LV1
83 and LV184 are wirings of the first wiring layer, LH181 and LH181.
H183, LH184, LH186, LV185-LV
196 is a power supply wiring of the second wiring layer. The power wiring L
V185 to LV188 are wirings passing through the inside of the function block BL184, and are power supply wirings LV189 to LV1.
Reference numeral 92 denotes a wiring passing through the inside of the function block BL181.

Each of the wiring channels Ch181, Ch182,
If the main line of Ch183 is the first wiring layer, LH1
82, LH185, LV181, LV182, LV18
3, LV184 is the power supply wiring of the first wiring layer, and the wiring L
In order to connect H182 and wiring LV181, power supply wiring LH181 of the second wiring layer and contact cell VIA18
1. Use VIA185. Similarly, the wiring LH183 and the contact cells VIA184 and VIA186 are used for the wiring LH182 and the wiring LV183. Wiring LH1
The same applies to the case where the wiring 85 and the wirings LV183 and LV184 are connected.

In order to connect the wiring LV189 and the wiring LH182, the contact cell VIA187 and the wiring LH182 are connected.
It is necessary to use the contact cells VIA189, VIA197, VIA198, and the wirings LH189, LV193 so that V190 does not contact with the same wiring layer. When the wiring LV186 and the wiring LH185 are connected, when the wiring LV187 and the wiring LH182 are connected, the wiring L
Similarly, when connecting V192 and the wiring LH185, a plurality of contacts and wiring are required.

In the conventional power supply wiring structure shown in FIG. 37, many contacts and many wirings are required, so that the wiring structure becomes complicated, and as a result, the area of the wiring channel may increase.

In FIG. 38, Ch181 to Ch183
Is a wiring channel, BL181 to BL184 are functional blocks, LH201 and LH202 are wirings of a first wiring layer, LV
201 to LV 204 are wirings of the second wiring layer, VIA 201
VIA 204 are contacts of the first wiring layer and the second wiring layer.

In the present embodiment, as shown in FIG.
Power supply wiring LV1 of wiring channels Ch181 and Ch182
81, LV182, LV183, and LV184 are assigned to the functional block BL181 in consideration of the power consumption of the functional block.
~ BL184.

As shown in FIG. 38, power supply line LV201
37 to the power line LV shown in FIG.
189 to LV192. However, in the power supply structure of FIG. 38 of the present embodiment, the number of wires and the number of contacts are smaller than that of the conventional power supply structure of FIG. 37, and the power supply structure is simple. Therefore, it is possible to make the area of the wiring channel smaller than that of the conventional example shown in FIG.

Next, a power supply structure in the case where a plurality of power supply wirings and ground wirings are provided in a functional block will be described.

In FIG. 39, Ch221 is a wiring channel, BL221 and BL222 are functional blocks, P22
1 to P236 are terminals of the second wiring layer of the functional block, LH
Reference numerals 221 and LH222 denote wirings of the first wiring layer, and LV221 to LV221.
LV232 is a wiring of the second wiring layer, VIA221 to VIA.
228 is a contact cell of the first wiring layer and the second wiring layer.

Since the terminals P221 and P229 have their terminals aligned in the horizontal direction, they can be connected by the wiring LV221. However, the terminals P223, P225, P231, P
233, the wirings LH221 and LV22
5, LV227, LV229, LV231, and contact cells VIA221, VIA223, VIA225,
Requires VIA 227. Similarly, terminals P224, P
When connecting 226, P232, and P234, the wiring L
H222, LV226, LV228, LV230, LV
232, and contact cells VIA222, VIA22
4, VIA 226 and VIA 228 are required.

Minimum height HC of wiring channel Ch221
h221 indicates that there is no other wiring, and the wiring LH221,
The wiring width of LH222 is WH, and the minimum distance between wirings is SP.
1. Assuming that the minimum distance between the wiring and the functional block is SP2, it is expressed by the following equation.

HCh221 = 2 × WH + SP1 + 2 × SP2 FIG. 40 shows a case where the positions of two terminals connecting the functional blocks BL221 and BL222 are aligned in the horizontal direction.

Minimum height HC of wiring channel Ch222
h222 indicates that there is no other wiring and the functional block BL
Assuming that the minimum interval between the H.221 and BL222 is SP3, HCh222 = SP3.

If SP1 = SP2 = SP3 = SP, HCh221 = 2 × WH + 3 × SP HCh222 = SP HCh221−HCh222 = 2 × WH + 3 × SP−SP = 2 (WH + SP) WH> 0, SP> 0 HCh221−HCh222 = 2 (WH + SP)> 0. Therefore, it is apparent that the minimum height HCh222 of the wiring channel Ch222 is higher than that of the wiring channel Ch22.
It can be seen that the minimum height HCh221 is smaller than the minimum height HCh221.

FIG. 41 shows a layout of a conventional semiconductor integrated circuit. The semiconductor integrated circuit shown in the figure has three functional blocks BL1 to BL3 and four input / output circuit blocks PAD1.
To PAD4 and six wiring channels ch1 to ch6. Main lines of power supply wiring and ground wiring are arranged in the wiring channels ch1 to ch6 for supplying power to the functional blocks. Since these trunk lines are thicker than the signal lines, the areas of the wiring channels ch1 to ch6 are large.

FIG. 42 shows a layout of the semiconductor integrated circuit according to the present embodiment. In the figure, two functional blocks B
The positions of the power supply terminal and the ground terminal are made to coincide with each other in the horizontal direction in the figure between L1 and BL2. Therefore, as can be seen from the figure, the trunk lines ml41 to ml44 in FIG. 41 can be eliminated, and two wiring channels ch1 and
The area of ch2 can be reduced, and the area of the entire semiconductor integrated circuit can be reduced.

Further, as shown in FIG. 43, when the positions of the power supply terminals are the same in all the functional blocks BL1 to BL4, the wiring constituting the functional blocks can be wired above (or below) the functional blocks. By arranging the power supply wiring and the ground wiring in a wiring layer different from the layer, the main lines of the power supply wiring and the ground wiring are not required in all the wiring channels. Therefore, the area of all the wiring channels ch1 to ch6 can be effectively reduced, and the chip area can be effectively reduced.

Since the sizes of the wiring layers, contacts, and layout patterns depend on the semiconductor manufacturing process, the names and numbers of the wiring layers and contacts in this embodiment are for the sake of simplicity. Therefore, the present invention does not limit the wiring layers, the names and numbers of contacts, and the size of the layout pattern in the actual semiconductor process.

[0140]

As described above, according to the first to fifth aspects of the present invention, the longer the distance between the terminals of the functional block is, the lower the height of the contact cell can be selected. Can be limited to a low height, and the area of the wiring channel can be reduced.

According to the present invention, the type of the contact cell located at the end of the wiring channel is selected in accordance with the width and height of the wiring channel. Therefore, the increase in the area of the wiring channel can be suppressed to a small extent.

Further, according to the invention as set forth in claims 8 to 12, during the layout of the semiconductor integrated circuit, of the plurality of types of contact cells, the contact cells having a small value and a low height are sequentially arranged. Therefore, it is possible to complete the layout while effectively reducing the area of the wiring channel.

In addition, according to the thirteenth to sixteenth aspects of the present invention, since the power supply wiring and the ground wiring arranged in the wiring channel are extended in the functional block, the number of power supply wirings and the number of contact cells are reduced. Thus, the arrangement structure of the power supply wiring and the like can be simplified, and the area of the wiring channel can be effectively reduced.

According to the seventeenth and eighteenth aspects of the present invention, since the power supply wiring and the ground wiring are arranged in a wiring layer different from the functional block, only the trunk line of the signal line connecting the functional blocks is provided in the wiring channel. And the area of the wiring channel can be effectively reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a shape of a contact cell margin and a contact hole.

FIG. 2 is a view showing three types of contact cells in which a contact margin and a contact hole are combined.

FIG. 3 is a diagram showing a spacing rule between contact cells having a square shape.

FIG. 4 is a diagram showing a spacing rule between a square contact cell and a wiring.

FIG. 5 is a diagram showing a spacing rule between cross-shaped contact cells.

FIG. 6 is a diagram showing a spacing rule between a cross-shaped contact cell and a wiring.

FIG. 7 is a view showing a spacing rule between horizontally long rectangular contact cells.

FIG. 8 is a diagram showing a spacing rule between a horizontally long rectangular contact cell and a wiring.

FIG. 9 is a diagram showing a spacing rule between vertically long rectangular contact cells.

FIG. 10 is a schematic diagram showing a layout of functional blocks when a horizontally long rectangular contact cell is selected in accordance with the interval between terminals.

FIG. 11 is a schematic diagram showing another layout of a functional block when a horizontally long rectangular contact cell is selected according to the interval between terminals.

FIG. 12 is a schematic diagram showing a layout of functional blocks when a square-shaped contact cell is selected according to an interval between terminals.

FIG. 13 is a schematic diagram showing another layout of functional blocks when a square-shaped contact cell is selected according to an interval between terminals.

FIG. 14 is a schematic diagram showing a layout of functional blocks when a vertically long rectangular contact cell is selected in accordance with the interval between terminals.

FIG. 15 is a flowchart illustrating a layout design method according to the first embodiment of the present invention.

FIG. 16 is a diagram schematically illustrating a layout of a semiconductor integrated circuit;

FIG. 17 is a flowchart illustrating a layout design method according to the second embodiment of this invention.

FIG. 18 is an enlarged view of a right end portion of a wiring channel after detailed wiring.

FIG. 19 is a diagram in which a contact cell at the right end of a wiring channel is replaced with a horizontally long rectangular contact cell.

FIG. 20 is a diagram in which a horizontally long rectangular contact cell located at the right end of a wiring channel is moved to a position where a spacing error does not occur.

FIG. 21 is a diagram in which a contact cell at the right end of a wiring channel is replaced with a vertically long rectangular contact cell.

FIG. 22 is a diagram in which a contact cell at the right end of a wiring channel is replaced with a square-shaped contact cell.

FIG. 23 is a diagram in which the contact cell at the right end of the wiring channel is replaced with a horizontally long rectangular contact cell.

FIG. 24 is a flowchart showing a detailed process of a contact cell optimizing step.

FIG. 25 is a diagram showing a detailed wiring result of a wiring channel.

FIG. 26 is a diagram in which virtual contact cells resulting from detailed wiring of a wiring channel are replaced with horizontally long rectangular contact cells.

FIG. 27 is a diagram in which a horizontally long rectangular contact cell causing a design error in a wiring channel is replaced with a cross-shaped contact cell.

FIG. 28 is a diagram in which a cross-shaped contact cell causing a design error in a wiring channel is replaced with a square-shaped contact cell.

FIG. 29 is a diagram in which a square contact cell causing a design error in a wiring channel is replaced with a vertically long rectangular contact cell.

FIG. 30 is a diagram showing a result of channel compaction of a detailed wiring result of a wiring channel after contact cell replacement.

FIG. 31 is a diagram showing a conventional layout result when a distance between terminals of a functional block is adjusted to a spacing rule between contact cells having a square shape.

FIG. 32 is a diagram showing a layout result in a case where the spacing between the terminals of the functional block is set in accordance with the spacing rule of the cross-shaped contact cells in the second embodiment of the present invention.

FIG. 33 is a diagram showing a layout result in the case where the distance between the terminals of the functional block is adjusted to the spacing rule between the horizontally long rectangular contact cells in the second embodiment of the present invention.

FIG. 34 is a diagram showing a schematic arrangement of a power supply wiring and a ground wiring between functional blocks in the related art.

FIG. 35 is a diagram showing a layout of a semiconductor integrated circuit in a case where a power supply wiring and a ground wiring in a functional block are shared with a power supply wiring and a ground wiring of a wiring channel.

FIG. 36 is a diagram in which a power supply wiring and a ground wiring are arranged inside two functional blocks in a conventional semiconductor integrated circuit.

FIG. 37 is a diagram showing a layout of power supply wiring and ground wiring arranged in a wiring channel between two functional blocks in a conventional semiconductor integrated circuit.

FIG. 38 is a view showing a layout in which a power supply wiring and a ground wiring of a wiring channel of a semiconductor integrated circuit are extended inside two functional blocks in the third embodiment of the present invention.

FIG. 39 is a diagram showing a layout of a power supply wiring and a ground wiring of a wiring channel between two functional blocks of the semiconductor integrated circuit in the third embodiment of the present invention.

FIG. 40 shows a layout in a case where the terminal positions of two functional blocks to which the power supply wiring and the ground wiring of the wiring channel of the semiconductor integrated circuit are connected to the same position in the third embodiment of the present invention. FIG.

FIG. 41 is a diagram showing a layout of power supply wiring and ground wiring in a conventional semiconductor integrated circuit.

FIG. 42 is a diagram showing a layout of a power supply wiring and a ground wiring of the semiconductor integrated circuit in the third embodiment of the present invention.

FIG. 43 is a diagram showing a layout in which a power supply wiring and a ground wiring of a semiconductor integrated circuit are arranged in a wiring layer different from a wiring layer of a wiring channel in the third embodiment of the present invention.

[Explanation of symbols]

11 Square margin of first wiring layer in contact cell 12 Square margin of second wiring layer in contact cell 13 Square contact hole 14 Horizontal rectangular margin of first wiring layer in contact cell 15 Contact cell 21. Horizontal rectangular margin of second wiring layer 21. Square contact cell 22 Cross-shaped contact cell 23 Horizontal rectangular contact cell 1000 Data input step 1001 Step of arranging cells and terminals 1002 Schematic wiring step 1003 Step for calculating the terminal pitch of the function block and selecting the type of contact cell 1004 Detailed wiring step 1005 Data output step 2000 Data input step 2001 Function block arrangement step 2002 Wiring channel setting Step 2003 Schematic wiring step 2004 Detailed wiring step 2005 Wiring channel width adjustment step 2006 Contact cell optimization step 2007 Wiring channel minimization step 2008 Completion determination step 2009 Data input step

Claims (18)

[Claims] 1. A layout design method of a building block type semiconductor integrated circuit, comprising arranging a plurality of function blocks and wiring wirings connecting the respective function blocks to wiring channels between the function blocks, A layout design method for a semiconductor integrated circuit, wherein a type of a contact cell connecting two wiring layers is selected according to a pitch of wiring connection terminals provided in each functional block. 2. The type of the contact cell is at least two of three types of contact cells each having a square, rectangular, and cross-shaped contact margin around a contact hole. Item 2. The layout design method for a semiconductor integrated circuit according to Item 1. 3. The longer the terminal pitch of the functional block is,
3. The layout design method for a semiconductor integrated circuit according to claim 1, wherein a contact cell having a low height is selected. 4. A layout design program for a building block type semiconductor integrated circuit in which a plurality of functional blocks are arranged by a computer and wiring for connecting the functional blocks is wired to a wiring channel between the functional blocks. Wherein the design program causes a type of a contact cell connecting two wiring layers to be selected according to a pitch of wiring connection terminals provided in each of the functional blocks. A recording medium on which a circuit layout design program is recorded. 5. The layout of a semiconductor integrated circuit according to claim 4, wherein said design program selects a contact cell having a shape capable of lowering the wiring channel height as the terminal pitch of the functional block is longer. A recording medium that records a design program. 6. A layout design method for a building block type semiconductor integrated circuit, comprising arranging a plurality of function blocks, and arranging wiring for connecting the respective function blocks to wiring channels between the function blocks, When a contact cell that connects two wiring layers is located at the end of the wiring channel, one of a plurality of types of contact cells that are previously provided according to the width and height of the wiring channel.
A layout design method for a semiconductor integrated circuit, wherein a seed is selected as the contact cell. 7. A layout design program for a building block type semiconductor integrated circuit in which a plurality of functional blocks are arranged by a computer, and wiring connecting the functional blocks is wired to a wiring channel between the functional blocks. The recording program according to claim 1, wherein the design program comprises: when a contact cell connecting two wiring layers is located at an end of the wiring channel, a plurality of types of contacts previously provided according to a width and a height of the wiring channel; 1 in the cell
A recording medium storing a layout design program for a semiconductor integrated circuit, wherein a seed is selected as the contact cell. 8. A layout design method of a building block type semiconductor integrated circuit in which a plurality of functional blocks are arranged and wiring connecting the respective functional blocks is wired to a wiring channel between the functional blocks, For a plurality of types of contact cells that connect two wiring layers in a wiring channel, cost is set according to the magnitude of the influence on the height of the wiring channel due to the shape of the contact cell. ,
Replace the contact cell with the lowest cost, check whether the replaced contact cell satisfies the design rule, and if the design rule error occurs, replace the contact cell with the next lowest cost contact cell A layout design method for a semiconductor integrated circuit, which repeatedly checks whether or not a rule is satisfied. 9. The semiconductor according to claim 8, wherein the plurality of types of contact cells include three types of contact cells having a square, rectangular, and cross-shaped contact margin around a contact hole. Layout design method for integrated circuits. 10. The three types of contact cells, wherein a contact cell having a horizontally long rectangular contact margin has the lowest cost, and a contact cell having a vertically long rectangular contact margin has the highest cost. Claim 9
The layout design method of the semiconductor integrated circuit described in the above. 11. A layout design program for a building block type semiconductor integrated circuit in which a plurality of functional blocks are arranged by a computer, and wiring connecting the functional blocks is wired to a wiring channel between these functional blocks. The design program, for the plurality of types of contact cells connecting two wiring layers in the wiring channel, the cost is set according to the magnitude of the influence of the shape of the contact cells on the height of the wiring channel. Initially, a contact cell existing in the wiring channel is
Replace the contact cell with the lowest cost, check whether the replaced contact cell satisfies the design rule, and if the design rule error occurs, replace the contact cell with the next lowest cost contact cell. A storage medium storing a layout design program for a semiconductor integrated circuit, wherein the step of repeatedly checking whether or not the design rule is satisfied is repeated. 12. The design program according to claim 3, wherein, among the plurality of types of contact cells, three types of contact cells having a square, rectangular, and cross-shaped contact margin around a contact hole have a horizontally long rectangular shape. 12. The semiconductor integrated circuit layout design program according to claim 11, wherein the cost of a contact cell having a contact margin is minimized, and the cost of a contact cell having a vertically long rectangular contact margin is maximized. recoding media. 13. A layout design method for a building block type semiconductor integrated circuit, comprising arranging a plurality of function blocks, and arranging wiring for connecting the respective function blocks to a wiring channel between these function blocks, A power supply wiring and a ground wiring arranged in a wiring channel are moved into each of the functional blocks and added to each of the functional blocks. 14. The functional block according to claim 13, wherein the horizontal or vertical position of the power supply wiring and the ground wiring added inside is set to the same position between the functional blocks. A layout design method for a semiconductor integrated circuit. 15. A layout design program for a building block type semiconductor integrated circuit in which a plurality of functional blocks are arranged by a computer, and wiring connecting the functional blocks is wired to a wiring channel between the functional blocks. The recording program according to claim 1, wherein the design program moves a power supply wiring and a ground wiring arranged in the wiring channel into each of the functional blocks and adds the power and ground wirings to each of the functional blocks. A recording medium on which a layout design program is recorded. 16. The design program sets the horizontal or vertical position of a power supply wiring and a ground wiring to be added inside each functional block at the same position among the functional blocks. A recording medium recording the semiconductor integrated circuit layout design program according to claim 15. 17. A layout design method for a building block type semiconductor integrated circuit, comprising arranging a plurality of function blocks, and arranging wiring for connecting each of the function blocks to a wiring channel between these function blocks. 15. The layout design method for a semiconductor integrated circuit according to claim 13, wherein the wiring and the ground wiring are arranged only on a wiring layer different from the wiring layer of the functional block. 18. A layout design program for a building block type semiconductor integrated circuit in which a plurality of functional blocks are arranged by a computer, and wirings connecting the functional blocks are wired to wiring channels between the functional blocks. 17. The recording medium according to claim 15, wherein the design program arranges a power supply wiring and a ground wiring only in a wiring layer different from a wiring layer of the functional block. A recording medium on which a layout design program is recorded.