WO2008090621A1 - 半導体記憶装置の製造方法 - Google Patents

半導体記憶装置の製造方法 Download PDF

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Publication number
WO2008090621A1
WO2008090621A1 PCT/JP2007/051202 JP2007051202W WO2008090621A1 WO 2008090621 A1 WO2008090621 A1 WO 2008090621A1 JP 2007051202 W JP2007051202 W JP 2007051202W WO 2008090621 A1 WO2008090621 A1 WO 2008090621A1
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WO
WIPO (PCT)
Prior art keywords
ingesbte
memory device
semiconductor memory
temperature
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/051202
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English (en)
French (fr)
Inventor
Yuichi Matsui
Takahiro Morikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2008554944A priority Critical patent/JP5043044B2/ja
Priority to PCT/JP2007/051202 priority patent/WO2008090621A1/ja
Priority to US12/524,049 priority patent/US20100015755A1/en
Publication of WO2008090621A1 publication Critical patent/WO2008090621A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

　ゲルマニウム（Ｇｅ）、アンチモン（Ｓｂ）およびテルル（Ｔｅ）からなるＧｅＳｂＴｅを母材とし、インジウム（Ｉｎ）が添加されたＩｎＧｅＳｂＴｅ膜を形成する工程において、母材のＧｅＳｂＴｅのその場結晶化温度と、ＩｎＧｅＳｂＴｅのその場結晶化温度との間に半導体基板の温度を保った状態で、その半導体基板上にＩｎＧｅＳｂＴｅ膜をスパッタリングによって形成する。その結果、その後の製造工程中にＩｎＧｅＳｂＴｅ膜中に相分離が発生する不具合を抑制することができる。
PCT/JP2007/051202 2007-01-25 2007-01-25 半導体記憶装置の製造方法 Ceased WO2008090621A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008554944A JP5043044B2 (ja) 2007-01-25 2007-01-25 半導体記憶装置の製造方法
PCT/JP2007/051202 WO2008090621A1 (ja) 2007-01-25 2007-01-25 半導体記憶装置の製造方法
US12/524,049 US20100015755A1 (en) 2007-01-25 2007-01-25 Manufacturing method of semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/051202 WO2008090621A1 (ja) 2007-01-25 2007-01-25 半導体記憶装置の製造方法

Publications (1)

Publication Number Publication Date
WO2008090621A1 true WO2008090621A1 (ja) 2008-07-31

Family

ID=39644203

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/051202 Ceased WO2008090621A1 (ja) 2007-01-25 2007-01-25 半導体記憶装置の製造方法

Country Status (3)

Country Link
US (1) US20100015755A1 (ja)
JP (1) JP5043044B2 (ja)
WO (1) WO2008090621A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014022619A (ja) * 2012-07-20 2014-02-03 Hitachi Ltd 低電力で動作する半導体記憶装置
JP2022055333A (ja) * 2020-09-28 2022-04-07 インターナショナル・ビジネス・マシーンズ・コーポレーション 相変化（ｐｃｍ）デバイス及び製造方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090035911A1 (en) * 2007-07-30 2009-02-05 Willy Rachmady Method for forming a semiconductor device having abrupt ultra shallow epi-tip regions
US8174876B2 (en) * 2009-06-19 2012-05-08 Hynix Semiconductor Inc. Fusion memory device embodied with phase change memory devices having different resistance distributions and data processing system using the same
JP5779138B2 (ja) * 2012-06-07 2015-09-16 株式会社東芝 分子メモリ
US9178144B1 (en) * 2014-04-14 2015-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. RRAM cell with bottom electrode
EP3796372A4 (en) * 2018-07-10 2022-03-16 National Institute Of Advanced Industrial Science And Technology LAMINATE STRUCTURE AND METHOD OF MANUFACTURE THEREOF AND SEMICONDUCTOR DEVICE
KR102820467B1 (ko) 2020-09-15 2025-06-16 삼성전자주식회사 정보 저장 물질 패턴을 포함하는 반도체 장치
WO2024034807A1 (ko) * 2022-08-11 2024-02-15 포항공과대학교 산학협력단 비정질 텔루륨 옥사이드를 포함하는 반도체, 그를 포함하는 박막트랜지스터 및 그의 제조방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005117030A (ja) * 2003-09-17 2005-04-28 Mitsubishi Materials Corp 半導体不揮発メモリー用相変化膜およびこの相変化膜を形成するためのスパッタリングターゲット
JP2006140395A (ja) * 2004-11-15 2006-06-01 Renesas Technology Corp 半導体メモリおよびその製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5687112A (en) * 1996-04-19 1997-11-11 Energy Conversion Devices, Inc. Multibit single cell memory element having tapered contact
KR100632948B1 (ko) * 2004-08-06 2006-10-11 삼성전자주식회사 칼코겐화합물 스퍼터링 형성 방법 및 이를 이용한 상변화 기억 소자 형성 방법
US7638786B2 (en) * 2004-11-15 2009-12-29 Renesas Technology Corp. Semiconductor and semiconductor manufacturing arrangements having a chalcogenide layer formed of columnar crystal grains perpendicular to a main substrate surface
JP2006156886A (ja) * 2004-12-01 2006-06-15 Renesas Technology Corp 半導体集積回路装置およびその製造方法
KR100688532B1 (ko) * 2005-02-14 2007-03-02 삼성전자주식회사 텔루르 전구체, 이를 이용하여 제조된 Ｔｅ-함유 칼코게나이드(ｃｈａｌｃｏｇｅｎｉｄｅ) 박막, 상기 박막의 제조방법 및 상변화 메모리 소자

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005117030A (ja) * 2003-09-17 2005-04-28 Mitsubishi Materials Corp 半導体不揮発メモリー用相変化膜およびこの相変化膜を形成するためのスパッタリングターゲット
JP2006140395A (ja) * 2004-11-15 2006-06-01 Renesas Technology Corp 半導体メモリおよびその製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014022619A (ja) * 2012-07-20 2014-02-03 Hitachi Ltd 低電力で動作する半導体記憶装置
JP2022055333A (ja) * 2020-09-28 2022-04-07 インターナショナル・ビジネス・マシーンズ・コーポレーション 相変化（ｐｃｍ）デバイス及び製造方法
JP7655645B2 (ja) 2020-09-28 2025-04-02 インターナショナル・ビジネス・マシーンズ・コーポレーション 相変化（ｐｃｍ）デバイス及び製造方法

Also Published As

Publication number Publication date
US20100015755A1 (en) 2010-01-21
JP5043044B2 (ja) 2012-10-10
JPWO2008090621A1 (ja) 2010-05-13

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