WO2008089685A1 - Appareil de communication, système de communication série en synchronisation et procédé correspondant - Google Patents

Appareil de communication, système de communication série en synchronisation et procédé correspondant Download PDF

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Publication number
WO2008089685A1
WO2008089685A1 PCT/CN2008/070126 CN2008070126W WO2008089685A1 WO 2008089685 A1 WO2008089685 A1 WO 2008089685A1 CN 2008070126 W CN2008070126 W CN 2008070126W WO 2008089685 A1 WO2008089685 A1 WO 2008089685A1
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WO
WIPO (PCT)
Prior art keywords
slave device
serial communication
line
data
communication system
Prior art date
Application number
PCT/CN2008/070126
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English (en)
Chinese (zh)
Inventor
Qiang Zhang
Dongning Lin
Original Assignee
Print-Rite Technology Development Co., Ltd Of Zhuhai
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN2007100265233A external-priority patent/CN101227264B/zh
Priority claimed from CNU2007200503701U external-priority patent/CN201039212Y/zh
Application filed by Print-Rite Technology Development Co., Ltd Of Zhuhai filed Critical Print-Rite Technology Development Co., Ltd Of Zhuhai
Publication of WO2008089685A1 publication Critical patent/WO2008089685A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the field of communications, and more particularly to communication devices and peer serial communication systems and methods in the field of communications.
  • the invention is based on a Chinese invention patent application with an application date of January 21, 2007, application number 200710026523. 3 and a Chinese utility model patent application with an application date of 200720050370. The contents of the application are incorporated herein by reference. Background technique
  • Serial communication is mainly divided into two categories: heterogeneous and homogenous.
  • the RS232 serial communication port on the computer is a different mode.
  • the communication parties agree on the communication speed, and only one data line is needed to complete the communication.
  • a clock line is added to the data transmitted on the data line.
  • the clock line is controlled by the host.
  • the host processes interrupts or other abnormalities, the clock signal can be paused.
  • the communication process hangs (pauses). After the host processing is completed, the clock signal continues to be transmitted, and the communication can continue.
  • Synchronous serial communication can occur between multiple devices connected to the same data bus, including a clock line, a reset line, and a data line.
  • a master device is generally set in such a multi-device serial communication system, the clock signal and the reset signal are sent by the master device, the other devices are set as slave devices, and the slave device is received by the master device. Clock signal and reset signal.
  • Each slave device has its own fixed and different address codes. When the communication starts, the master device sends the address code corresponding to the slave device to be communicated to the data bus, and the slave device corresponding to the address code responds to the communication and obtains the master.
  • the device's communication right, BP gets the right to use the data line, while the other slaves are idle, waiting for the next address recognition.
  • FIG. 1 A more typical implementation of an existing peer-to-peer serial communication system is shown in FIG.
  • the serial communication system includes a master device M and two slave devices &, b, the master device M and two slave devices a, b are connected on the same data bus.
  • the master device M with The two slave devices a, b share the same power line.
  • the master device M and the two slave devices a, b can have their own independent power lines, and the operating voltages of the three devices can also be different. These are very well known. current technology.
  • the address code of the device a (assumed to be "01") is first sent to the data line, and the device a is used to obtain the right to use the data line.
  • Data communication with the master device M, power supply, data, reset and clock waveform diagrams when operating from the device a can be seen in FIG.
  • the slave device a is in the active state, the slave device b is in an idle state. If the master device M needs to perform data communication with the slave device b, first stop the data exchange work with the slave device a, and then send the address code of the slave device b (assumed to be "10") to the address line, the slave device. b, that is, the right to use the data line, data communication with the host device M, at this time, the slave device a is idle.
  • the multi-device serial communication system shown in FIG. 1 is composed of one master device and two slave devices.
  • such a serial serial communication system can be composed of one master device and two or more slave devices.
  • the working principle is the same as above; of course, the serial communication system can also include a master device and a single slave device. At this time, since there is only one slave device, the address code is only one, gp, and the master device only This unique slave device communicates. In short, the working principle is similar regardless of how the device changes, and will not be described here.
  • the working or idle state of the slave devices a and b is completely determined by the master device M. If a peer serial communication system includes one master device and two slave devices (as shown in FIG. 1), the user needs to Immediately during the operation of the device a, the slave device b is used instead of the slave device a to communicate with the master device M, ⁇ , and the slave device b needs to immediately replace the slave device a in the working state to perform data communication with the master device M, then The existing serial serial communication system cannot be realized;
  • an existing peer serial communication system includes a master device M and more than one slave device
  • the user needs to add a new communication device as the slave device to form a new serial communication.
  • System and in the newly formed peer serial communication system, the user needs to be able to use the newly added slave device to communicate with the master device M in the process of working in the original slave device, that is, the newly added slave
  • the device needs to be able to immediately replace the slave device and the master device M that are in the working state. For data communication, this functional extension is not possible with the prior art. Summary of the invention
  • a first object of the present invention is to provide a communication device capable of being incorporated into an existing peer serial communication system and capable of flexible data communication;
  • a second object of the present invention is to provide a peer-to-peer serial communication system capable of flexible data communication
  • a third object of the present invention is to provide a peer-to-peer serial communication method capable of implementing flexible data communication.
  • the present invention provides a communication device that is added as an external slave device to a serial communication system, the serial communication system including a master device and at least one original The slave device, the master device and the slave device are connected to the same data bus.
  • the data bus includes a clock line, a reset line and a data line.
  • the original slave device receives the clock signal and the reset signal generated by the master device through the clock line and the reset line, respectively.
  • the clock signal is exchanged with the main device through the data line.
  • the communication device of the present invention includes:
  • a device body connected to the same data bus, which receives a clock signal and a reset signal of the master device through a clock line and a reset line, and exchanges data with the master device through the data line; the clock signal generated by the master device or A level pull-down circuit that resets the amplitude of the signal, the device body can exchange data with the master device under a reduced amplitude clock signal or a reset signal.
  • the present invention provides a peer-to-peer serial communication system including: a master device, a first slave device, and a second slave device connected to the same data bus, wherein the data bus includes a clock a line, a reset line, and a data line, the first slave device and the second slave device respectively receive a clock signal and a reset signal generated by the master device through the clock line and the reset line, and perform data exchange with the master device through the data line, and at the first a level pull-down circuit that reduces the amplitude of the clock signal or the reset signal generated by the master device under the control of the device, and the first slave device can exchange data with the master device under the reduced amplitude clock signal or the reset signal.
  • the second slave device is then masked by the reduced amplitude clock signal or reset signal.
  • the present invention provides a peer-to-peer serial communication method according to the above-described peer-to-peer serial communication system, which includes the following steps: When the second slave device performs data exchange with the master device, the first slave device monitors data and determines whether the exchanged data meets a specific requirement;
  • the amplitude of the clock signal or the reset signal generated by the master device is lowered by the level pull-down circuit, and the first slave device replaces the second slave device with the master device for data exchange.
  • FIG. 1 is a schematic diagram of a conventional serial communication system
  • FIG. 2 is a working waveform diagram of the serial communication system of the same type in FIG. 1;
  • FIG. 3 is a schematic structural view of a first embodiment of a serial communication system of the present invention.
  • FIG. 4 is a schematic structural view of the main device shown in FIG. 3;
  • FIG. 5 is a schematic structural diagram of a circuit after the circuit of FIG. 4 is further refined
  • FIG. 7 is a schematic structural block diagram of a synchronous serial communication system of the present invention applied to a printing system
  • FIG. 8 is a detection unit, an execution unit, and a level of an ink cartridge chip when the same serial communication system of the present invention is applied in a printing system
  • FIG. 9 is an electrical schematic diagram of a detection unit, an execution unit, a level pull-down circuit and a reset line of the ink cartridge chip when the serial communication system of the present invention is applied in a printing system;
  • Figure 10 is a diagram showing the operation waveforms of the power supply signal, the reset signal, the controller signal, and the data signal in the circuit of Figure 9. detailed description
  • FIG. 3 is a schematic structural diagram of a first embodiment of a serial communication system according to the present invention.
  • the first embodiment of the serial communication system of the present invention comprises a main device 8, a first slave device 1, a second slave device 2, and a level pull-down circuit 4, the master device S and the first slave device 1.
  • the second slave device 2 and the level pull-down circuit 4 are all connected to the same clock line, and the clock signal of the clock line is generated by the clock pin CLK of the master device S, and the first slave device 1 and the second slave device 2 respectively pass The respective clock pins CLK1, CLK2 receive the clock signal of the master device S, which is the same as the prior art. I will not repeat them here.
  • FIG. 3 Only the schematic structure of the key including the clock line is shown.
  • a level pull-down circuit 4 is connected to the clock line, and the level pull-down circuit 4 is subjected to The control of the first slave device 1, BP, the level pull-down circuit 4 can reduce the amplitude of the clock signal generated by the master device S under the control of the first slave device 1; meanwhile, the first slave device 1 can be lowered The amplitude of the clock signal is exchanged with the master device, while the second slave device 2 is unable to perform any data exchange with the master device S under the reduced amplitude clock signal. Therefore, the serial communication system shown in FIG.
  • the main device S and the second slave device 2 exchange data
  • the first slave device 1 monitors specific data, it needs to replace the second slave device 2
  • the data is exchanged with the master device S
  • the first slave device 1 can reduce the amplitude of the clock signal sent by the master device S by the control level pull-down circuit 4, at this time, since the second slave device 2 cannot be reduced in amplitude Any data exchange with the master device S under the value of the clock signal, so that the data communication between the second slave device and the master device S is interrupted, and on the other hand, since the first slave device 1 can be at the reduced amplitude clock Data is exchanged with the master device S under the signal, so that the first slave device 1 can exchange data with the master device S instead of the second slave device 2.
  • FIG. 3 has clearly and briefly described the structure and function of the serial communication system of the present invention, in order to more specifically explain the structure of the serial communication system of the present invention, those skilled in the art can further The features of the serial communication system of the present invention are clearly understood and can be implemented without any hindrance. The following description will be made in conjunction with FIGS. 4 and 5.
  • the master device S shown in Fig. 3 can be divided into a master device body Sl, a clock driver circuit 3, a DC power source VCC, and a current limiting resistor R1. It should be emphasized that the method by which the master device S generates a clock signal is various, and FIG. 4 is merely an example of the description, and does not mean that the present invention is limited to this embodiment.
  • the main device body S1 includes an internal clock pin CLKout, which is relatively small.
  • the weak clock signal, and the power supply VCC, the current limiting resistor R1, and the clock driving circuit 3 function to amplify the internal clock signal CLKout (the specific amplification process will be described later), and then input to the clock line.
  • the clock output circuit of the main device S in FIG. It is considered to be a limitation of the present invention.
  • the structure and operation mode of the main device S in the present invention are not different from those in the prior art, those skilled in the art can fully devise the modifications.
  • FIG. 5 refines the circuit of FIG. 4, wherein the clock driving circuit 3 in FIG. 4 is implemented by a triode QS, and the level pull-down circuit 4 is realized by a Zener diode QD and a triode Q1.
  • this voltage is applied to the transistor QS through the current limiting resistor R1.
  • the main device body S1 outputs the internal clock signal CLKout
  • the transistor QS is turned on, and the clock line is turned on.
  • the voltage (close to zero) is used as the low level; during the low period of the clock signal CLKout, the transistor QS is turned off, the clock line is 5V as the high level, gp, and the clock signal on the clock line is taken as the high level with the 5V voltage.
  • the clock line output voltage is higher than 2.5 V (of course, this value can also be based on actual needs and characteristics of components).
  • the first slave device 1 and the second slave device 2 When the adjustment occurs, the first slave device 1 and the second slave device 2 will consider it to be a high level; when the clock line output voltage is between 1.5 V and 2.5 V, the second slave device 2 will consider it It is low, and the first slave device 1 still considers it to be high. When the clock line output voltage is lower than 1.5 V, the first slave device 1 also considers it to be low. That is, the first slave device 1 can operate at a lower clock signal amplitude, but the second slave device 2 cannot, once the level of the clock signal falls below 2. 5V, the second slave device 2 Will continue to receive low level, unable to continue working.
  • the level pull-down circuit 4 includes a Zener diode QD whose negative terminal is connected to the clock line (assuming that the Zener diode QD has a voltage regulation value of 1.5 V) and a transistor Q1 connected between the anode and the ground of the Zener diode QD, wherein The collector of the transistor Q1 is connected to the anode of the Zener diode QD, the emitter of the transistor Q1 is grounded, and the base of the transistor Q1 is connected to the control terminal of the first slave device 1, and the control terminal can generate direct current Press VI.
  • the transistor Q1 When the DC voltage VI is applied to the base of the transistor Q1, if the clock line outputs a high level (amplitude of 5V), then the transistor Q1 will be turned on (assuming that the voltage drop after its turn-on is 0.7 V), due to stability
  • the voltage regulator QD is regulated, the actual voltage on the clock line will be 2. 2V ( 1. 5+0. 7), the amplitude of the clock signal will be reduced, and the reduced voltage will be second.
  • the slave device 2 considers it to be a low level and is considered to be a high level by the first slave device 1.
  • the level pull-down circuit 4 can also have other implementations.
  • a switching element having a switching function such as an electronic switch or a field effect transistor can be used instead of the transistor Q1 to perform the corresponding switching function.
  • the Zener diode QD can also be replaced by other voltage divider components, such as a voltage divider resistor (of course, the Zener diode QD as a voltage divider component can make the circuit performance very good, and its effect is better than the general voltage divider resistor).
  • the core idea of the level pull-down circuit 4 is to: control the on or off of the switching element (for example, the transistor Q1) by the first slave device 1, since the level pull-down circuit 4 is connected to the clock line and the ground (of course, Not grounded but connected to a lower level, the condition is similar to the switch such as transistor Q1 can be turned on), which is essentially the control level pull-down circuit 4 and the clock line is turned on or off, when the level When the pull-down circuit 4 is turned on with the clock line, the amplitude of the clock signal can be reduced.
  • the voltage-dividing component acts as a voltage divider, which can increase the overall voltage drop of the level pull-down circuit.
  • the master device S When the master device S issues the address code of the second slave device 2, since the second slave device 2 matches the address, the master device S will issue a command code to communicate with the second slave device, during the communication, if the first When the specified sequence is detected from the device 1 (ie, the first slave device 1 needs to communicate with the second slave device 2), the first slave device immediately generates a DC voltage VI, and the control level pull-down circuit 4 will decrease the amplitude of the clock signal. After the amplitude of the clock signal is reduced (as in the above example, the amplitude is reduced to 2.
  • the second slave device 2 will not receive a high level and is therefore shielded, while the first slave device 1 will still
  • the clock signal of the reduced amplitude can be recognized as a high level, and therefore, the first slave device 1 can communicate with the master device instead of the second slave device 2.
  • the same serial communication method of the above-mentioned serial communication system includes the following steps: When the second slave device 2 performs data exchange with the master device S, the first slave device 1 monitors the data and determines whether the exchanged data meets a specific requirement (ie, whether a specified sequence occurs);
  • the amplitude of the clock signal generated by the master device S is lowered by the level pull-down circuit 4, and the first slave device 1 replaces the second slave device 2 with the master device S for data exchange.
  • the communication device includes the first slave device 1 and the level pull-down circuit 4 described above.
  • the communication device can be added as an external slave device to the existing serial communication system to form a new serial communication system as shown in FIG. 3 to FIG. 5, through the first slave device 1 (as the device body) According to the actual needs, it can have the functions of data communication, processing, etc., and the pull-down circuit 4 makes the data communication of the new peer serial communication system more flexible, and achieves the object of the present invention. Since the above description has completely revealed this concept and scheme, it will not be described herein.
  • the homogenous serial communication system described in the present invention can be applied to many fields, such as the printing system shown in FIG. 7, which includes a printer 7 and an ink cartridge 8 mountable in the printer 7, the printer 7 including a processing unit 71 and
  • the controller 72 is connected to the data bus 10, and the data bus 10 includes a clock line, a reset line, a data line, and the like.
  • the ink cartridge chip 81 is disposed on the ink cartridge 8. When the ink cartridge chip 81 is mounted in the printer 7 with the ink cartridge 8, the processing unit 71, the controller 72 and the ink cartridge chip 81 are electrically connected and constitute the serial communication shown in FIG.
  • the system wherein the processing unit 71 corresponds to the main device S, the controller 72 corresponds to the second slave device 2, and the ink cartridge chip 81 corresponds to the first slave device 1 and the level pull-down circuit 4.
  • the working principle can be referred to the above description.
  • the printing system can reduce the amplitude of the clock signal by the level pull-down circuit 4 when the processing unit 71 and the controller 72 perform data exchange, so that the ink cartridge chip 81 can exchange data with the processing unit 71 instead of the controller 72.
  • the ink cartridge chip 81 includes a memory 82 that stores information related to the ink cartridge 8 and is connected to the data bus 10 and communicates with the processing unit 71 and the controller 72 via the data bus 10.
  • the ink cartridge chip 81 is further provided with a detecting unit 83, an executing unit 84, an output unit 85, and a level pull-down circuit 4.
  • the detecting unit 83 monitors the communication between the processing unit 71 and the controller 72, and receives the detection signal sent by the controller 72, and sends the detection information to the executing unit 84 according to the corresponding signal, and the executing unit 84 sends out according to the detecting unit 83.
  • the detection information control output unit 85 and the level pull-down circuit 4 operate.
  • FIG. 8 An electrical schematic diagram of the detection unit 83, the execution unit 84, and the level pull-down circuit 4 of the ink cartridge chip 81 connected to the clock line is shown in FIG. 8, wherein the level pull-down circuit 4 is composed of a transistor Q1 and a Zener diode QD.
  • the DC power supply VCC is loaded to the clock line through the current limiting resistor R1, and the clock driving circuit 3 generates a weak clock signal which is amplified by the transistor QS and input to the clock line.
  • the detecting unit 83 monitors and receives the signal sent by the controller 72, and determines whether a specific requirement is met, that is, whether it is a detection signal, and if so, sends detection information to the executing unit 84, and the executing unit 84 drives the transistor Q1 to be turned on, the clock line. The amplitude of the clock signal on it is reduced.
  • the controller 72 considers that the clock signal is at a low level, and the ink cartridge chip 81 considers that the clock signal is at a high level and continues to operate.
  • the execution unit 84 issues control information to the output unit 85, and the output unit 85 communicates with the processing unit 71 instead of the controller 72.
  • the first slave device i.e., the ink cartridge chip 81
  • the first slave device lowers the amplitude of the clock signal and operates in place of the second slave device, but in actual use, the first slave device can also reduce the amplitude of the reset signal.
  • FIG. 9 is an electrical schematic diagram of a detection unit, an execution unit, a level pull-down circuit and a reset line of the ink cartridge chip when the serial communication system of the present invention is applied in a printing system
  • FIG. 10 is a diagram. 9 The working waveform of the power signal, reset signal, controller signal and data signal in the circuit.
  • the level pull-down circuit of this embodiment is constituted only by the transistor Q1, and the collector of the transistor Q1 is connected to the reset line.
  • a voltage dividing device such as a Zener diode, between the transistor Q1 and the reset line, which keeps the amplitude of the reset signal in a stable range.
  • the DC power supply VCC loads a signal to the reset line through the resistor R2, and the reset drive circuit 5 generates a weak reset signal, which is amplified by the transistor QS and input to the reset line, and forms a reset signal on the reset line. At this time, the power signal and the reset signal are high. Level, controller 72 and cartridge chip 81 can both operate normally with this reset signal.
  • the detecting unit 83 monitors and receives the signal sent by the controller 72, and sends out detection information to the executing unit 84 when it is determined that the signal meets a specific requirement, and the executing unit 84 sends a driving signal to the base of the transistor Q1 to cause the transistor Q1 to conduct Bypass, the amplitude of the reset signal decreases rapidly.
  • the controller 72 is reset under the reduced reset signal, receiving new information again, and the ink cartridge chip 81 is not affected by the reset signal, and the output unit 85 sends a message to the data bus.
  • the controller 72 Since the controller 72 needs to receive new information after reset, the information is sent, so the amplitude of the signal is reset. After the reduction, the controller 72 is in a waiting state to stop transmitting information. At the same time, the output unit 85 transmits information to the processing unit 71 through the data line, thereby operating the processing unit 71 instead of the controller 72.
  • the ink cartridge 8 contains ink, and an inductive device for detecting the presence or absence of ink may be disposed in the ink cartridge 8, such as a detecting probe, which is two non-contacting inks disposed in the ink.
  • the electrodes when energized, the two electrodes are electrically conducted by the conduction of the ink. If the ink between the two electrodes is exhausted, the electrodes cannot be electrically connected, BP, if the electrodes are not conductive. , it means that the ink between the electrodes has been exhausted, so as to achieve the purpose of detecting the ink.
  • the ink cartridge chip 81 may be a microcontroller, and the microcontroller includes a signal input terminal connected to the sensing device.
  • the detection result of the sensing device is input into the signal input terminal, and the ink cartridge chip 81 determines whether the control level is required to be pulled down according to the detection result. Circuit 4 reduces the amplitude of the clock signal. Further, the cartridge chip 8 can output a corresponding value to the processing unit 71 based on the different results detected by the sensing device.
  • the communication device of the present invention may be an ink cartridge chip 81, which includes a first slave device 1 (as a device body, which may have functions of data communication, processing, etc. according to actual needs) and a level pull-down circuit 4, an ink cartridge chip
  • a first slave device 1 as a device body, which may have functions of data communication, processing, etc. according to actual needs
  • a level pull-down circuit 4 an ink cartridge chip
  • the invention is not limited to the above embodiments in terms of its broader form. Similar to the implementation of the level pull-down circuit 4, the manner in which the master device generates the clock signal or the reset signal, and the number of slave devices, etc., can be appropriately changed, and various minor changes and equivalent transformations like this should be included. It is within the scope of the claims. Industrial applicability
  • the communication device provided by the invention can be added to the existing serial communication system, and the amplitude of the clock signal or the reset signal can be reduced by the level pull-down circuit, so that flexible data communication can be performed.
  • the synchronous serial communication system provided by the present invention can reduce the amplitude of the clock signal or the reset signal by using the level pull-down circuit during the communication between the second slave device and the master device, the first slave device can be replaced.
  • the second slave device communicates with the master device, so the data communication method is more flexible than the existing serial communication system.
  • the serial communication method provided by the present invention can be implemented in the second slave device and the master device.
  • the level pull-down circuit is used to reduce the amplitude of the clock signal or the reset signal, so that the first slave device can replace the second slave device to perform data communication with the master device, and has a very flexible data communication mode.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

La présente invention concerne un appareil de communication, un système de communication série en synchronisation et un procédé correspondant. L'appareil de communication et le système de communication en série de synchronisation comportent un circuit de rétablissement de niveau électrique. Le système de communication série en synchronisation et son procédé correspondant réduisent l'amplitude du signal d'horloge ou du signal de remise à zéro au moyen du circuit de rétablissement de niveau électrique de sorte que l'appareil esclave spécifique puisse remplacer un autre appareil esclave pour échanger des données et le mode de communication série est plus flexible.
PCT/CN2008/070126 2007-01-21 2008-01-17 Appareil de communication, système de communication série en synchronisation et procédé correspondant WO2008089685A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN2007100265233A CN101227264B (zh) 2007-01-21 2007-01-21 通讯装置、同步串行通讯系统及方法
CN200710026523.3 2007-01-21
CNU2007200503701U CN201039212Y (zh) 2007-04-10 2007-04-10 芯片及容器
CN200720050370.1 2007-04-10

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WO2008089685A1 true WO2008089685A1 (fr) 2008-07-31

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6557063B1 (en) * 1999-02-26 2003-04-29 Semtech Corporation Power conservation with a synchronous master-slave serial data bus
CN1637256A (zh) * 2004-01-07 2005-07-13 株式会社日立制作所 数据通信装置及使用该装置的控制器
CN1744069A (zh) * 2004-09-02 2006-03-08 北京中星微电子有限公司 一种适应于串行外围设备接口总线通信方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6557063B1 (en) * 1999-02-26 2003-04-29 Semtech Corporation Power conservation with a synchronous master-slave serial data bus
CN1637256A (zh) * 2004-01-07 2005-07-13 株式会社日立制作所 数据通信装置及使用该装置的控制器
CN1744069A (zh) * 2004-09-02 2006-03-08 北京中星微电子有限公司 一种适应于串行外围设备接口总线通信方法

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