WO2008087849A1 - 回路装置の解析装置、解析方法、解析プログラムおよび電子媒体 - Google Patents

回路装置の解析装置、解析方法、解析プログラムおよび電子媒体 Download PDF

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Publication number
WO2008087849A1
WO2008087849A1 PCT/JP2007/075215 JP2007075215W WO2008087849A1 WO 2008087849 A1 WO2008087849 A1 WO 2008087849A1 JP 2007075215 W JP2007075215 W JP 2007075215W WO 2008087849 A1 WO2008087849 A1 WO 2008087849A1
Authority
WO
WIPO (PCT)
Prior art keywords
analyzing
circuit board
arithmetic operation
elecronic
medium
Prior art date
Application number
PCT/JP2007/075215
Other languages
English (en)
French (fr)
Inventor
Kazuhide Uriu
Toru Yamada
Masahiro Yamaoka
Original Assignee
Panasonic Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corporation filed Critical Panasonic Corporation
Priority to KR1020097001244A priority Critical patent/KR20090111798A/ko
Priority to EP07860436A priority patent/EP2040186A4/en
Priority to JP2008553999A priority patent/JP5001304B2/ja
Priority to US12/374,353 priority patent/US8132140B2/en
Publication of WO2008087849A1 publication Critical patent/WO2008087849A1/ja

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G06F30/23—Design optimisation, verification or simulation using finite element methods [FEM] or finite difference methods [FDM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

　解析処理時間を大幅に短縮することができる回路基板の解析方法及び解析装置を提供すること。 　演算装置１１０と、演算装置１１０に接続された記憶装置１４０と、演算装置１１０に接続された入力装置１６０とを備え、演算装置１１０は、回路基板に形成される配線のデータを取得する配線データ取得部３１０と、配線をメッシュ分割して、セルと、互いに隣接するセル間を接続するブランチとを設定する基本回路図作成部３２０と、各セル及び各ブランチに設定された素子に対して、当該素子を無視する範囲を設定する干渉解析設定部３３０とを含むことを特徴とする、回路基板の解析装置である。
PCT/JP2007/075215 2007-01-15 2007-12-27 回路装置の解析装置、解析方法、解析プログラムおよび電子媒体 WO2008087849A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020097001244A KR20090111798A (ko) 2007-01-15 2007-12-27 회로 장치의 해석 장치, 해석 방법, 해석 프로그램 및 전자매체
EP07860436A EP2040186A4 (en) 2007-01-15 2007-12-27 ANALYSIS DEVICE FOR CIRCUIT DEVICE, ANALYSIS METHOD, ANALYSIS PROGRAM, AND ELECTRONIC MEDIUM
JP2008553999A JP5001304B2 (ja) 2007-01-15 2007-12-27 回路装置の解析装置、回路装置の解析方法、回路装置の設計方法、回路装置の解析プログラムおよび記憶媒体
US12/374,353 US8132140B2 (en) 2007-01-15 2007-12-27 Analyzing device for circuit device, circuit device analyzing method, analyzing program, and electronic medium

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007-005610 2007-01-15
JP2007005609 2007-01-15
JP2007-005609 2007-01-15
JP2007005610 2007-01-15

Publications (1)

Publication Number Publication Date
WO2008087849A1 true WO2008087849A1 (ja) 2008-07-24

Family

ID=39635854

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/075215 WO2008087849A1 (ja) 2007-01-15 2007-12-27 回路装置の解析装置、解析方法、解析プログラムおよび電子媒体

Country Status (5)

Country Link
US (1) US8132140B2 (ja)
EP (1) EP2040186A4 (ja)
JP (1) JP5001304B2 (ja)
KR (1) KR20090111798A (ja)
WO (1) WO2008087849A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8185864B2 (en) 2008-04-03 2012-05-22 Panasonic Corporation Circuit board analyzer and analysis method
JP2013030186A (ja) * 2012-10-01 2013-02-07 Hitachi Ltd ノイズ解析設計方法およびノイズ解析設計装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4720964B2 (ja) * 2001-05-31 2011-07-13 日本電気株式会社 Ｆｅｍ解析方法、プログラム、およびシステム
WO2011127420A1 (en) * 2010-04-09 2011-10-13 Gift Technologies, Llc Multi-element wind turbine airfoils and wind turbines incorporating the same
CN102306222B (zh) * 2011-08-31 2012-12-26 南通泰慕士服装有限公司 一种浆料用量的计算方法
JP6365264B2 (ja) * 2014-11-25 2018-08-01 富士通株式会社 配線のトポロジ表示プログラム、配線のトポロジ表示方法、および情報処理装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10214281A (ja) * 1996-11-27 1998-08-11 Matsushita Electric Ind Co Ltd プリント回路基板用ｃａｄ装置
JP2006127495A (ja) * 2004-09-29 2006-05-18 Matsushita Electric Ind Co Ltd 配線基板の設計システム、設計データの解析方法および解析プログラム
WO2006112411A1 (ja) * 2005-04-15 2006-10-26 Matsushita Electric Industrial Co., Ltd. 回路配線の干渉解析装置、干渉解析プログラム並びに干渉解析装置に用いられるデータベース、非対称結合線路モデル

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US5309371A (en) * 1989-06-28 1994-05-03 Kawasaki Steel Corporation Method of and apparatus for designing circuit block layout in integrated circuit
AU1562195A (en) * 1994-01-25 1995-08-08 Advantage Logic, Inc. Apparatus and method for partitioning resources for interconnections
KR19980042821A (ko) 1996-11-27 1998-08-17 모리시다요이치 설계 파라미터를 설정하는 프린트 회로 기판용 캐드 장치
US6317859B1 (en) * 1999-06-09 2001-11-13 International Business Machines Corporation Method and system for determining critical area for circuit layouts
JP3341730B2 (ja) * 1999-08-20 2002-11-05 日本電気株式会社 パターンデータ密度検査装置
US6480992B1 (en) * 1999-11-08 2002-11-12 International Business Machines Corporation Method, apparatus, and program product for laying out capacitors in an integrated circuit
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JP2005217321A (ja) * 2004-01-30 2005-08-11 Nec Electronics Corp 自動配置配線装置、半導体装置の配置配線方法、半導体装置の製造方法及び半導体装置
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Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10214281A (ja) * 1996-11-27 1998-08-11 Matsushita Electric Ind Co Ltd プリント回路基板用ｃａｄ装置
JP2006127495A (ja) * 2004-09-29 2006-05-18 Matsushita Electric Ind Co Ltd 配線基板の設計システム、設計データの解析方法および解析プログラム
WO2006112411A1 (ja) * 2005-04-15 2006-10-26 Matsushita Electric Industrial Co., Ltd. 回路配線の干渉解析装置、干渉解析プログラム並びに干渉解析装置に用いられるデータベース、非対称結合線路モデル

Non-Patent Citations (1)

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Title
See also references of EP2040186A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8185864B2 (en) 2008-04-03 2012-05-22 Panasonic Corporation Circuit board analyzer and analysis method
JP2013030186A (ja) * 2012-10-01 2013-02-07 Hitachi Ltd ノイズ解析設計方法およびノイズ解析設計装置

Also Published As

Publication number Publication date
KR20090111798A (ko) 2009-10-27
JP5001304B2 (ja) 2012-08-15
EP2040186A1 (en) 2009-03-25
EP2040186A4 (en) 2012-08-22
JPWO2008087849A1 (ja) 2010-05-06
US20090249264A1 (en) 2009-10-01
US8132140B2 (en) 2012-03-06

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