WO2008077421A1 - Décodeur de canal à itérations de décodage en nombre variable - Google Patents

Décodeur de canal à itérations de décodage en nombre variable Download PDF

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Publication number
WO2008077421A1
WO2008077421A1 PCT/EP2006/012461 EP2006012461W WO2008077421A1 WO 2008077421 A1 WO2008077421 A1 WO 2008077421A1 EP 2006012461 W EP2006012461 W EP 2006012461W WO 2008077421 A1 WO2008077421 A1 WO 2008077421A1
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WO
WIPO (PCT)
Prior art keywords
iteration
controller
input
decoding unit
decoding
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Application number
PCT/EP2006/012461
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English (en)
Inventor
Yu Pan
Huifeng Shi
Original Assignee
Micronas Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Micronas Gmbh filed Critical Micronas Gmbh
Priority to PCT/EP2006/012461 priority Critical patent/WO2008077421A1/fr
Publication of WO2008077421A1 publication Critical patent/WO2008077421A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/2975—Judging correct decoding, e.g. iteration stopping criteria
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2948—Iterative decoding

Definitions

  • the invention regards to an iteration controller for itera- tion-decoding-codes according to pre-characterizing part of claim 1, and to a method for controlling such an iteration controller .
  • FEC Forward Error Correction
  • Essential parts of the FEC are iteration-decoding-codes, like Low Density Parity Check (LDPC) codes and Turbo codes, etc. Their common characteristics are required iteration-decoder to complete decoding. Because of the deterioration of the bits received, different blocks need different iteration times. Generally, the decoder will set the maximum iteration times, thus throughput of the decoder is corresponding to the maximum iteration times. The smaller the maximum iteration times are, the higher the throughput of the decoder is. Of course, the performance of the iteration-decoding-codes is also corresponding to the maximum iteration times. The smaller the maximum iteration times are, the worse performance is. So there is a trade-off between the performance and the throughput. But sometimes, when deterioration of the bits of a block is not so severe, the block perhaps require several iteration times to get the correct bits. In sometime, after maximum-iteration- times iteration decoding, the block still have error bits.
  • LDPC
  • Fig. 3 describes block diagrams of a known iterative decoder 1.
  • Input data, especially input data blocks are inputted via an input line to an iteration decoder unit 2.
  • Iteration decoding unit 2 is the main module in the iterative decoder 1.
  • the iteration decoding u- nit 2 module has the different structure from each other.
  • it will adopt BP algorithm (BP: Brief Propagation) for LDPC codes, and adopt BCJR algorithm (BJCR: Algorithm suggested by L. Bahl, J. Cocke, F. Jelinek, and J. Raviv 1974 to decode fold codes) for Turbo codes, etc.
  • An iteration controller unit 3 is coupled to the iteration decoder unit 2.
  • the iteration controller unit 3 is constructed to receive decoding information from the iteration decoder u- nit 2 and to sent instruction to stop or not to stop iteration process to the iteration decoder unit 2.
  • the iteration controller unit 3 is mainly to calculate how many iteration times the iterative decoder 1 has completed. When it gets to the maximum iteration times "maxiter", it will stop the current iteration-loop in the iteration decoder unit 2 whether it decodes successfully or not. Simultaneously, it also receives the decoding information from the iterative decoding unit to judge whether the iteration-loop should stop or not.
  • modules 4 receiving decoded data from the iteration decoding unit 2 are assistant modules of the iterative decoder, like Error Calculator module, etc.
  • assistant modules of the iterative decoder like Error Calculator module, etc.
  • the throughput of the iterative decoder 1 is decided by decoding parallel factor "parallel”, maximum iteration ti ⁇ mes "maxiter”, and working frequency, as following:
  • This iterative decoder 1 has to satisfy the important condition that input data rate of the decoder must be less than the throughput of the decoder.
  • Fig. 4 shows BER performance of such iteration decoder.
  • the complexity of one iterative decoder is decided by the ability of parallel processing m it. Given the maximum throughput one iterative decode has to meet, the ability of parallel processing is inverse proportional with iteration times, which is a fixed number m decoder.
  • the main drawback of the exist- ing solutions is the fixed maximum iteration times. For every block iterative decoder always sets the same value of maxiter, which results in the wasting of the iteration times for the decoding-success blocks, because in general, when the block is decoded successfully, the iteration times of current iteration-loop is always less than or equal to the maxiter.
  • iteration decoder or an iteration controller for iteration-decoding- codes providing better performance with the same throughput, or higher throughput with the same performance.
  • iteration decoder shall provide same performance and throughput, needing less parallel-processing-unit in decoder. Further, there should be provided a method for controlling such an iteration controller.
  • an iteration controller for it- eration-decoding-codes comprising an iteration decoding unit adapted to receive data having an data rate and to perform iterations for decoding codes, and an iteration controller adapted for controlling number of iterations in iteration decoding unit, the iteration controller being constructed and/or controlled as an adaptive iteration controller, and being adapted to instruct variable number of iteration times depending on input data to be processed by iteration decoding unit.
  • an iteration decoding unit receives data having an data rate and performs a number of iterations for decoding codes, and number of iterations in iteration decoding unit being controlled, said maximum number of iterations in iteration decoding unit being adapted dynamically depending on input data to be processed by iteration decoding unit.
  • variable maximum iteration times instead of using the fixed maximum iteration times.
  • For every block iterative decoder sets a current maximum iteration times from current status of the iterative decoder. In this way, iterative decoder will get better performance with the same average it- eration times.
  • iterative requires less average iteration times, so it can get higher throughput. Therefore, to get same performance and same throughput, it will need less parallel, which defines the number of the parallel-processing-unit that results in the decrease of the hardware resource.
  • an iteration controller wherein the adaptive iteration controller being adapted either to instruct iteration decoding unit to use variable maximum iteration times or to instruct iteration decoding unit to stop or not to stop iteration.
  • the adaptive iteration controller being adapted to instruct number of iteration times depending on decoding information, especially decoding status received from the iteration decoding unit.
  • decoder comprises an input controller adapted to receive input data and to forward such input data as the data to the iteration decoding unit, the input controller having and/or controlling a buffer for temporarily buffering the input data under condition, that input data rate of input data would be larger than the current throughput of the iteration decoding unit.
  • such adaptive iteration controller is coupled with the input controller.
  • adaptive iteration controller being adapted to inform input controller regarding decoding state of iteration decoding unit. It is preferred, when this input controller forwards inputted input data and/or buffered input data as data to the iteration decoding unit depending on such information regarding decoding state of itera- tion decoding unit.
  • such adaptive iteration controller being coupled with the input controller to get input controller information regarding the input data received by the input controller and/or buffered within the input controller.
  • the adaptive iteration controller being adapted such that every data block in the iterative decoder unit will be iterated by an adaptive current maximum iteration time depending on number of input data buffered by input controller such that there will be no buffer overflow in buffer.
  • such input rate of the iterative decoder unit depends on decoding parallel factor of such decoder and a working frequency of the iterative decoder unit on one hand and depends on especially the inverse value of minimum current maximum iteration times of the iterative decoding unit.
  • input data to be forwarded as the data to the iteration decoding unit being temporarily buffered under condition that input data rate of input data would be larger than current the throughput of the iteration decoding unit.
  • input data are buffered depending on decoding state of iteration decoding unit.
  • input data can be forwarded to the iteration decoding unit depending on information regarding the input data received by the input controller and/or buffered within the input controller.
  • every data block in the iterative decoder unit will be iterated in maximum by an adaptive current maximum it- eration time depending on number of input data buffered such that there will be no buffer overflow.
  • an input rate of the iterative decoder unit depends on decoding parallel factor and a working frequency of the iterative decoder unit on one hand and depends on especially the inverse value of minimum current maximum iteration times of the iterative decoding unit.
  • FIG. 1 block diagrams of iterative decoder with adaptive iteration controller
  • FIG. 3 block diagrams of iterative decoder according to prior art
  • Fig. 1 shows a block diagram of an iterative decoder 1 having an input controller 5, an iteration decoding unit 2, and an adaptive iteration controller 6.
  • Input data, especially input data blocks are inputted via an input line to the input controller 5.
  • Input controller 5 is constructed and controlled to buffer inputted data and to output inputted data directly or to output buffered data as new data to the iteration decoder unit 2.
  • Iteration decoding unit 2 is the main module in the iterative decoder 1.
  • the iteration decoding unit 2 module has the different structure from each other. For example, it will adopt BP algorithm for LDPC codes, and adopt BCJR algorithm for Turbo codes, etc.
  • Adaptive iteration controller 6 unit is coupled to the iteration decoder unit 2.
  • the adaptive iteration controller 6 is constructed to receive decoding information from the iteration decoder unit 2, and to sent instruction to stop or not to stop iteration process to the iteration decoder unit 2.
  • adaptive iteration controller 6 unit is coupled to the input controller 5.
  • the adaptive iteration controller 6 is constructed to receive input controller information from the input controller 5, and to sent information regarding decoder state ready or decoder state not ready to the input controller 5.
  • modules 4 coupled to the iteration decoder unit 2 are constructed and controlled to receive decoded data from the iteration decoding unit 2, and being assistant modules of the iterative decoder 1, like Error Calculator module, etc.
  • the main part of the module constructing the input controller 5 is an FIFO unit (FIFO: First Input First Output), whose function is to buffer the input data.
  • the input controller 5 will provide some information, like status of the FIFO, data ready or not, to the module building up the adaptive iteration controller 6.
  • the adaptive iteration controller 6 gets the information from the module input controller 5 to set the current maximum iteration times for the current block, i.e. for the data block being forwarded/outputted by the input control ⁇ ler 5 and/or being buffered in the input controller 5.
  • Such FIFO unit can be adapted by a buffer device or any other storage device.
  • Every block in the iterative decoder with adaptive iteration controller 6 will be allowed at least eqiter iteration times decoding, so eqiter is the minimum current maximum iteration times of the iterative decoding unit 2. If one block costs less iteration times, then the next block can get more iteration times. And value of curmaxiter can be dynamically adjusted for every block through the empty space of the FIFO to guarantee, that the iterative decoder unit 2 can work properly under rate Tinput, which means that the throughput of the iterative decoder is Tinput.
  • the throughput of the iterative decoder 1 with adaptive iteration controller 6 is defined according to
  • minmaxiter is the minimum current maximum iteration times of the iterative decoder unit 2.
  • Equation (3) minmaxiter is less, especially always less than maxiter in equation (1) . So at the same throughput, the iterative decoder 1 with adaptive iteration controller 6 can select less parallel than that without adaptive iteration controller 6, which means that the iterative decoder 1 with adaptive iteration controller 6 will need less hardware resource than that without adaptive iteration controller 6.
  • adaptive iteration controller 6 when the input rate is variable, the iterative decoder with adaptive iteration controller 6 will adjust the curmax- iter automatically to get the best performance. Thus, when the input rate is lower, the BER performance is better because the curmaxiter is larger. In another word, we can call adaptive iteration controller 6 as "Performance Adaptive Controller" because adaptive iteration controller 6 will always adjust the curmaxiter through the input rate to get the best performance.
  • the hardware resource of the iterative decoder with adaptive iteration controller 6 can decrease nearly 50% in comparison with that without adaptive iteration controller 6 because of the FIFO resource.

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

Décodeur pour codes de décodage itératif, tels que des turbocodes et des LDPL, ledit décodeur comprenant un tampon d'entrée, un module de décodage itératif (2) conçu pour recevoir des données issues dudit tampon d'entrée, et un régulateur d'itérations conçu pour réguler le nombre d'itérations dans ledit module de décodage itératif (2) en fonction de l'espace utilisé dans ledit tampon d'entrée de manière à empêcher son débordement et d'informations issues dudit module de décodage itératif.
PCT/EP2006/012461 2006-12-22 2006-12-22 Décodeur de canal à itérations de décodage en nombre variable WO2008077421A1 (fr)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9692553B2 (en) 2011-10-05 2017-06-27 Telefonaktiebolaget Lm Ericsson (Publ) Method and device for decoding a transport block of a communication signal
US20180123616A1 (en) * 2016-10-28 2018-05-03 Mstar Semiconductor, Inc. Decoding method for convolutional code decoding device in communication system and associated determination module
CN108111250A (zh) * 2016-11-25 2018-06-01 晨星半导体股份有限公司 用于通信系统中回旋码解码装置的解码方法及相关的判断模块

Citations (5)

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Publication number Priority date Publication date Assignee Title
WO1999055008A1 (fr) * 1998-04-18 1999-10-28 Samsung Electronics Co., Ltd. Codeur/decodeur de canaux et procede relatif a un systeme de telecommunications
EP0973292A2 (fr) * 1998-07-17 2000-01-19 Nortel Networks Corporation Décodeur à multiplexage statistique pour turbocodage
WO2000027037A2 (fr) * 1998-11-05 2000-05-11 Qualcomm Incorporated Decodage iteratif efficace
WO2001063869A1 (fr) * 2000-02-25 2001-08-30 Nokia Corporation Procede et dispositif adaptatifs permettant de mettre en oeuvre une redondance par accroissement dans la reception
DE10214393A1 (de) * 2001-03-27 2003-02-06 Univ Dresden Tech Verfahren zur iterativen Decodierung von verketteten Codes

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999055008A1 (fr) * 1998-04-18 1999-10-28 Samsung Electronics Co., Ltd. Codeur/decodeur de canaux et procede relatif a un systeme de telecommunications
EP0973292A2 (fr) * 1998-07-17 2000-01-19 Nortel Networks Corporation Décodeur à multiplexage statistique pour turbocodage
WO2000027037A2 (fr) * 1998-11-05 2000-05-11 Qualcomm Incorporated Decodage iteratif efficace
WO2001063869A1 (fr) * 2000-02-25 2001-08-30 Nokia Corporation Procede et dispositif adaptatifs permettant de mettre en oeuvre une redondance par accroissement dans la reception
DE10214393A1 (de) * 2001-03-27 2003-02-06 Univ Dresden Tech Verfahren zur iterativen Decodierung von verketteten Codes

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9692553B2 (en) 2011-10-05 2017-06-27 Telefonaktiebolaget Lm Ericsson (Publ) Method and device for decoding a transport block of a communication signal
US20180123616A1 (en) * 2016-10-28 2018-05-03 Mstar Semiconductor, Inc. Decoding method for convolutional code decoding device in communication system and associated determination module
TWI650954B (zh) * 2016-10-28 2019-02-11 晨星半導體股份有限公司 用於通訊系統中迴旋碼解碼裝置的解碼方法及相關的判斷模組
CN108111250A (zh) * 2016-11-25 2018-06-01 晨星半导体股份有限公司 用于通信系统中回旋码解码装置的解码方法及相关的判断模块

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