WO2008075125A1 - Procédé et décodeur pour décodage en boucle - Google Patents

Procédé et décodeur pour décodage en boucle Download PDF

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Publication number
WO2008075125A1
WO2008075125A1 PCT/IB2006/003719 IB2006003719W WO2008075125A1 WO 2008075125 A1 WO2008075125 A1 WO 2008075125A1 IB 2006003719 W IB2006003719 W IB 2006003719W WO 2008075125 A1 WO2008075125 A1 WO 2008075125A1
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WO
WIPO (PCT)
Prior art keywords
bits
decoder
convolutionally encoded
encoded sequence
sequence
Prior art date
Application number
PCT/IB2006/003719
Other languages
English (en)
Inventor
Jean-François BERGEVIN
Gwenael Poitau
Original Assignee
Wavesat Inc.
Sk Telecom Cl., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wavesat Inc., Sk Telecom Cl., Ltd. filed Critical Wavesat Inc.
Priority to PCT/IB2006/003719 priority Critical patent/WO2008075125A1/fr
Publication of WO2008075125A1 publication Critical patent/WO2008075125A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4123—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing the return to a predetermined state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/413—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors tail biting Viterbi decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H03M13/6505—Memory efficient implementations

Definitions

  • TITLE METHOD AND DECODER FOR TAIL-BITING DECODING
  • the present invention relates to Viterbi decoding, and more particularly to a method and an apparatus for performing decoding of tail-biting convolutionally encoded sequence of bits.
  • Convolutional encoding consists in multiplying all the bits of a sequence with a generator matrix so as to create codewords.
  • the generator matrix can be subdivided in three specific types: zero-tail matrix, a direct truncation matrix and a tail-biting matrix.
  • the zero-tail matrix requires that last eight bits of the bits of sequence to be encoded be zeroes.
  • This type of generator matrix advantageously allows having a known end state of zeroes when decoding encoded data. However, this requirement introduces a throughput reduction on an encoder.
  • the direct truncation matrix proceeds with direct encoding, without knowing a prior state of the encoder or decoder.
  • the direct truncation matrix is thus the weakest of the three types of generator matrix, as it does not provide any initializing.
  • the tail-biting matrix uses the last bits of the codewords to initialize its encoding pattern. This subcategory of generator matrix introduces decoding difficulties such as an unknown initial and ending states, while allowing maximal throughput.
  • IEEE 802.16-2004 and IEEE 802.16e-2005 specifics for the generator matrix of the zero tail-biting and tail- biting types for modulation techniques such as Orthogonal Frequency Division Multiplexing (OFDM) and Orthogonal Frequency Division Multiplexing Access (OFDMA).
  • OFDM Orthogonal Frequency Division Multiplexing
  • OFDMA Orthogonal Frequency Division Multiplexing Access
  • Encoding however means that decoding is required to recover the original bits of the sequence.
  • Andrew J. Viterbi developed a technique known as the Viterbi Decoder Algorithm in the late 1960s,.
  • the Viterbi Decoder Algorithm uses a trellis representation to decode codewords relying on a maximum likelihood analysis.
  • the trellis representation is a redundant description of a state diagram of an encoder.
  • Viterbi provides a simple way for recovering the original bits of a sequence from codewords.
  • errors happen in a transmission of the codewords, as often is the case because of interference or poor transmission or reception of wireless data communications, some additional efforts must be made to recover the original bits of the sequence.
  • Viterbi further describes a method for calculating a number of erroneous bits for each path on the trellis, and thus evaluating a most likely number of errors based on the number of calculated erroneous bits.
  • Other improvements have been made to the Viterbi Decoder Algorithm, to address cases where an initial state of an encoder is known and when it is not known. Those improvements are referred to as zero tailing and tail-biting.
  • the zero tailing improvement of the Viterbi Decoder Algorithm requires a start and end states of a decoder to be forced to zero values. This improvement of the Viterbi Decoder Algorithm results in a reduction of the throughput.
  • the tail- biting of the Viterbi Decoder Algorithm is used when the start and end states of the encoder are unknown. As not knowing the start and end states of the decoder greatly increases the possible paths taken along the trellis, analysis of each path is required, resulting in an important processing power, and latency when decoding the codewords. To overcome that added difficulty efficiently, last bits of the codewords are used to initialize the decoder, thus recreating an identical start and end states and thereby reducing the number of paths to be analyzed on the trellis.
  • tail-biting alternatives have been proposed in the past.
  • One of the most referenced alternative has been proposed by Howard H. Ma and Jack K. Wolf, and was described in an article titled "On Tail-Biting Convolutional Codes", published at IEEE Transactions on Communications, Volume COM- 34, No. 2, pp.104-111 , February 1986. That paper proposes two algorithms for solving latency issues with tail-biting convolutional decoding.
  • the first algorithm consists of identifying, through trial and error, which starting state returns the same ending state.
  • this algorithm is suboptimal because it does not compensate for codewords including many errors, which can result in start and end state that are the same, even though they are not the right ones.
  • the second algorithm consists of using algebraic structure of the convolution code to obtain the starting state, thus reducing a number of iterations.
  • both these algorithms require that the whole codewords be processed iteratively to reach an optimal bit error rate, thus resulting in important latency.
  • the first algorithm consists of storing the path with the largest metric together with its metrics for each start and end states, and eliminate all other paths.
  • the second algorithm re-uses results from the first algorithm, and selects the path with the largest metrics' end state, and uses a start state equivalent to the end state and reuses those end state and start state for all other stored paths.
  • the present invention provides a decoding method and a decoder requiring less processing capability than decoders described in the prior art, while being capable of a lower latency and being appropriate for real-time applications and applications such as wireless data transfers and mobile applications, by being non-iterative.
  • the method of the present invention includes a step of decoding the convolutionally encoded sequence of bits using a Viterbi decoder. The method then proceeds with re-decoding a first portion of the convolutionally encoded sequence of bits. The method then outputs the decoded sequence of bits, wherein an outputted decoded first portion of the convolutionally encoded sequence of bits corresponds to re-decoded first portion of the convolutionally encoded sequence of bits.
  • the present invention is directed to a decoder for decoding a convolutionally encoded sequence of bits.
  • the decoded includes an an input port for receiving the convolutionally encoded sequence of bits.
  • the decoder also includes a Viterbi decoder for decoding the convolutionally encoded sequence of bits and re-decoding a first portion of the convolutionally encoded sequence of bits.
  • the decoder also includes an output port for outputting the decoded convolutionally encoded sequence of bits, wherein the first portion of the decoded convolutionally encoded sequence of bits corresponds to re-decoded first portion of the convolutionally encoded sequence of bits.
  • Figure 1a and b are flowcharts of methods in accordance with aspects of the present invention.
  • Figures 2a and 2b are schematic representations of examples of post fixing in accordance with two aspects of the present invention
  • Figure 3 is a schematic view of a decoder in accordance with an aspect of the present invention
  • Figure 4 is a schematic view of a decoder in accordance with an aspect of the present invention in use in a modem
  • Figure 5 is a graph depicting bit error rate performances of a decoder in accordance with aspects of the present invention.
  • the present invention relates to a method and a decoder for decoding tail- biting convolutionally encoded sequence of bits. More particularly, the method and decoder of the present invention decodes a convolutionally encoded sequence of bits, and re-decodes a first portion of the convolutionally encoded sequence of bits. The method and decoder then outputs a decoded sequence of bits wherein the first portion of the decoded sequence of bits corresponds to the re-decoded first portion.
  • the present invention is characterized by many advantages over prior art solutions. First and foremost, the present invention describes a tail-biting
  • Viterbi decoder that is non-iterative. By removing the usual iterative approach, the present invention results in a simpler and lower cost solution by allowing use of a zero-tail decoder, also known as a standard state "00"
  • Viterbi decoder Because of its simplicity, can be implemented in an on-chip system, rendering it implementable in wireless communications systems for data transfers.
  • FCH Frame Control Header
  • FIG. 1a depict flowcharts of two aspects of a method 10 for decoding a tail-biting convolutionally encoded sequence of bits, in accordance with the present invention.
  • the method of Figure 1a starts by receiving a sequence of bits at step 11.
  • the method continues with a step 14 of decoding the received sequence of bits.
  • the decoding of step 14 further includes re-decoding a first portion of the received bits.
  • the first portion has a length equal to a number of bits required to initialize a decoder performing the decoding step.
  • the method completes with a step of outputting 19 the decoded sequence of bits.
  • the decoded sequence of bits outputted in step 19 is preferably composed of the first portion and a remaining portion of the decoded sequence of bits.
  • the first portion corresponds to the re-decoded sequence of bits, while the remaining portion corresponds to the remaining portion of the decoded sequence of bits.
  • the method further includes a step copying and appending (step 12) a first portion of the convolutionally encoded sequence of bits at an end of the convolutionally encoded sequence of bits.
  • Such copying and appending of the first portion of the convolutionally encoded sequence of bits is one possible way of facilitating the later re-decoding of the first portion of the encoded sequence of bits. This operation can also be named post fixing.
  • the first portion of bits has a length equal to a number of bits required to initialize a Viterbi decoder.
  • the first portion of bits may have a length equal to (2* a number of bits required to initialize the Viterbi decoder), i.e. x bits.
  • the first portion of bits has a length equal to x bits, i.e. equal to a number of bits required to initialize the Viterbi decoder.
  • step 14 the convolutionally encoded sequence of bits and the appended first portion.
  • the step of re- decoding is thus automatically performed when the decoding is performed.
  • the method pursues at step 16 with replacing a part of the first portion of the sequence of bits after decoding with corresponding bits of the first portion appended at the end of the sequence of bits.
  • first bits of the sequence are used to initialize the Viterbi decoder, it is the first bits of the first portion of the sequence of bits that are replaced.
  • step 18 the appended first portion of bits is removed.
  • the method then completes as on Figure 1 a with the step of outputting the decoded sequence of bits.
  • the decoding step 14 of Figures 1a and 1b is preferably performed using a Viterbi decoder.
  • the Viterbi decoder can be a tail-biting decoder, while in another aspect of the invention, the decoder may consists more particularly of a zero-tailing tail-biting Viterbi decoder.
  • Figure 3 represents a schematic block diagram of a decoder 30 in accordance with a first aspect of the present invention.
  • the decoder 30 includes an input module 32 and an output module 34.
  • the input module 32 and output module 34 can additionally be combined into an input/output port if desired.
  • the input module 32 receives the convolutionally encoded sequence of bits 31 , and forwards it to a Viterbi decoder 36.
  • the Viterbi decoder 36 is adapted to decode the encoded sequence of bits 31.
  • the Viterbi decoder is a normal state "00" Viterbi decoder.
  • the decoder 36 decodes the encoded sequence of bits 31 and re-decodes a first portion thereof. Then, the Viterbi decoder 36 sends the decoded sequence of bits 37 to a replacing module 38.
  • the replacing module 38 is adapted to removing a part of the first portion of the sequence of bits after decoding and replace it with corresponding bits of the first portion which have been re- decoded.
  • the decoded sequence of bits is then provided to the output module 34, which outputs the decoded sequence of bits, wherein the first portion of the decoded sequence of bits corresponds to re-decoded first portion of the sequence of bits.
  • Figure 3 represents a schematic block diagram of a decoder 30 in accordance with another aspect of the present invention.
  • the decoder 30 includes an input module 32 and an output module 34.
  • the input module 32 receives the convolutionally encoded sequence of bits 31 , and forwards it to an affixing module 35.
  • the affixing module 35 is adapted to copy and append a first portion of the convolutionally encoded sequence of bits at an end of the convolutionally encoded sequence of bits.
  • the affixing module 35 forwards the resulting sequence of bits 33 to a Viterbi decoder 36.
  • the Viterbi decoder 36 is adapted to decode the resulting sequence of bits 33, which corresponds to the convolutionally encoded sequence of bits with the appended first portion. Then, the Viterbi decoder 36 sends the decoded sequence of bits 37 to a replacing module 38.
  • the replacing module 38 is adapted to removing a part of the first portion of the sequence of bits after decoding and replace it with corresponding bits of the first portion appended at the end of the sequence of bits which have also been decoded.
  • the replacing module 38 may further be adapted to remove the first portion of the convolutionally encoded sequence of bits appended at the end of the convolutionally encoded sequence of bits.
  • a deleting module 39 if preferred may also perform the removing of the appended first portion.
  • FIG 4 depicts a decoder in accordance with an aspect of the invention, in use in a modem.
  • decoders such as the one of the present invention are used to communicate between computers.
  • Computers communicate with one another either through a Local Area Network, through an Ethernet Network, through an Internet Protocol (IP) Network all of which being wired or wireless.
  • IP Internet Protocol
  • a computer 40 is used to communicate with at least one other computer or server, through an IP network 42.
  • the computer communicates with the IP network 42 wirelessly.
  • the computer uses a modem 44 to connect and exchange data with the IP network 42.
  • Modems such as the modem 44 depicted in Figure 4, are composed of many different components, two of which are a decoder 46 and a buffer 48. Other components of the modem 44 will not be discussed herein, but those skilled in the art know the various possible components generally used in modems. Because of its simplicity and good accuracy, the decoder of the present invention is particularly interesting for use in the modem 40, and more particularly for the modem 40 being used with standards such as Wireless Broadband, OFDMA, etc. Since the decoder 46 of the present invention is a non-iterative decoder, it requires less processing capability and allows using a much smaller buffer 48 than in previous modem for tail-biting decoding. Reduction of the buffer and reduction of the required processing capability are important advantages for a successful decoder on the market.
  • the graph represents bit error rate curves computed through simulations for a Wireless Broadband OFDMA system.
  • the graph shows results obtained for four different sets of modulation parameters.
  • a first set of modulation parameters depicted is the Quadrature Phase-Shift Keying (QPSK) Vz tail-biting modulation, which is shown at reference 50.
  • the second set of modulation parameters is the QPSK ⁇ A zero-tailing modulation, represented using reference 52.
  • QPSK ⁇ A tail- biting and QPSK ⁇ A zero-tailing show similar performances.
  • a third set of modulation parameters depicted is the 64 Quadrature Amplitude Modulation (QAM) VA tail-biting modulation parameters, referenced 54.
  • QAM Quadrature Amplitude Modulation
  • the fourth set of modulation parameters represented is the 64 QAM 3 A zero-tailing modulation parameters, represented by reference 56. From this graph, it can o 3 7 ,

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

La présente invention concerne un procédé et un décodeur pour décoder une suite de bits codés par convolution. Le procédé et le décodeur décodent la suite de bits codée par convolution et en recodent une première partie. Le procédé et le décodage se poursuivent avec la production de la suite de bits décodée. La première partie de la suite décodée de bits correspond à la première partie redécodée de la suite de bits.
PCT/IB2006/003719 2006-12-20 2006-12-20 Procédé et décodeur pour décodage en boucle WO2008075125A1 (fr)

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PCT/IB2006/003719 WO2008075125A1 (fr) 2006-12-20 2006-12-20 Procédé et décodeur pour décodage en boucle

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2605410A1 (fr) * 2010-08-11 2013-06-19 ZTE Corporation Procédé de décodage de canal et décodeur convolutif en boucle

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0611098A2 (fr) * 1993-02-11 1994-08-17 AT&T Corp. Décodeur viterbi circulaire pour codes convolutionels en boucle
US5721746A (en) * 1996-04-19 1998-02-24 General Electric Company Optimal soft-output decoder for tail-biting trellis codes

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0611098A2 (fr) * 1993-02-11 1994-08-17 AT&T Corp. Décodeur viterbi circulaire pour codes convolutionels en boucle
US5721746A (en) * 1996-04-19 1998-02-24 General Electric Company Optimal soft-output decoder for tail-biting trellis codes

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
MA H H ET AL: "ON TAIL BITING CONVOLUTIONAL CODES", IEEE TRANSACTIONS ON COMMUNICATIONS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. COM-34, no. 2, February 1986 (1986-02-01), pages 104 - 111, XP002038443, ISSN: 0090-6778 *
QIANG WANG ET AL: "AN EFFICIENT MAXIMUM LIKELIHOOD DECODING ALGORITHM FOR GENERALIZED TAIL BITING CONVOLUTIONAL CODES INCLUDING QUASICYCLIC CODES", IEEE TRANSACTIONS ON COMMUNICATIONS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 37, no. 8, 1 August 1989 (1989-08-01), pages 875 - 879, XP000047627, ISSN: 0090-6778 *
SHAO R Y ET AL: "An iterative bidirectional decoding algorithm for tail biting codes", INFORMATION THEORY AND COMMUNICATIONS WORKSHOP, 1999. PROCEEDINGS OF THE 1999 IEEE KRUGER NATIONAL PARK, SOUTH AFRICA 20-25 JUNE 1999, PISCATAWAY, NJ, USA,IEEE, US, 20 June 1999 (1999-06-20), pages 122, XP010345496, ISBN: 0-7803-5268-8 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2605410A1 (fr) * 2010-08-11 2013-06-19 ZTE Corporation Procédé de décodage de canal et décodeur convolutif en boucle
EP2605410A4 (fr) * 2010-08-11 2014-01-01 Zte Corp Procédé de décodage de canal et décodeur convolutif en boucle

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