WO2008069383A1 - Method and apparatus for modulo n calculation - Google Patents
Method and apparatus for modulo n calculation Download PDFInfo
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- WO2008069383A1 WO2008069383A1 PCT/KR2007/002971 KR2007002971W WO2008069383A1 WO 2008069383 A1 WO2008069383 A1 WO 2008069383A1 KR 2007002971 W KR2007002971 W KR 2007002971W WO 2008069383 A1 WO2008069383 A1 WO 2008069383A1
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000007796 conventional method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/727—Modulo N arithmetic, with N being either (2**n)-1,2**n or (2**n)+1, e.g. mod 3, mod 4 or mod 5
Definitions
- the present invention relates to a modulo calculating method in a modulo calculating apparatus, and more particularly, to a method and an apparatus capable of performing modulo N calculation on an Ml*M2-bit binary integer K, e.g., a 4*M2-bit binary integer K by using a simplified logic circuit (Ml and M2 are integers that are 0 or greater).
- a conventional modulo 3 calculation device includes a first counter for counting up to an input integer K and a second counter for counting 0, 1 and 2 circularly.
- FIG. 1 is a flowchart illustrating a conventional method for modulo 3 calculation.
- the first counter completes counting up to the input integer K
- the current value of the second counter is detected and outputted as a result value.
- the numbers of counting times by the two counters correspond to the input integer, so that the greater the input integer is, the more time is spent.
- a modulo N calculating method for an Ml*M2-bit binary integer wherein N, Ml and M2 are integers, the method including the steps of: dividing the Ml*M2-bit binary integer into
- the specific binary integer may be binary value
- the specific binary integer may be binary value 1010.
- the specific value may be added by the steps of (a) performing the AND operation on the Ml least significant bits of the Ml*M2-bit binary integer and a binary value 0101 ; (b) adding one value of 0, 1 and 2 to the value of the output register depending on the AND operation result of the step (a); (c) performing the AND operation on the Ml least significant bits of the Ml*M2-bit binary integer and a binary value 1010; (d) adding one value of 0, 2 and 4 to the value of the output register depending on the AND operation result of the step (c); (e) shifting the Ml*M2-bit binary integer by Ml bits to the right; and (f) performing the steps (a) to (e) M2 times.
- the specific value is added by the further steps of (g) after performing the step (f), determining whether the value of the output register is 3 or smaller; and (h) performing the steps (a) to (d) repeatedly, until it is determined in the step (g) that the value of the output register is 3 or smaller.
- a modulo N calculating apparatus including an input unit for receiving an M 1 *M2-bit binary integer, wherein N, Ml and M2 are integers; and an AND operation unit for performing AND operation on the Ml*M2-bit binary integer and a specific binary integer.
- the specific binary integer may be binary value
- the specific binary integer may be binary value 1010.
- AND operation unit performs AND operation on each M 1 bits and the specific binary integer and a specific value depending on the AND operation result is added.
- the modulo 3 calculation can be efficiently performed on any input integer K by addition of a logic circuit for the two AND operations, so that the modulo result can be obtained more rapidly.
- FIG. 1 is a flowchart illustrating a conventional modulo 3 calculating method
- FIG. 2 and 3 are flowcharts illustrating a modulo N calculating method in a modulo N calculating apparatus of preferred embodiment in accordance with the present invention.
- FIG. 2 and 3 are flowcharts illustrating a modulo N calculating method in a modulo
- N calculating apparatus of a preferred embodiment in accordance with the present invention N calculating apparatus of a preferred embodiment in accordance with the present invention.
- Ml*M2-bit operation S200
- the value of the output register may be initialized to 0.
- step S204 when it is determined in step S204 that the AND operation result is binary value 0101, 2 is added to the value of the output register (S206). When the result is 0, 0 is added to the value of the output register (S216). When the AND operation result is neither binary value 0101 nor 0, 1 is added to the value of the output register (S218).
- step S210 when it is determined in step S210 that the AND operation result is binary value 1010, 4 is added to the value of the output register (S212). When the AND operation result is 0, 0 is added to the value of the output register (S220). When the AND operation result is neither binary value 1010 nor 0, 2 is added to the value of the output register (S222).
- the input integer K is shifted by 4 bits to the right (S214). After the 4 least significant bits are discarded by this manner, the new 4 least significant bits are subject to the above steps from S202 to S222. This process corresponds to step S224 of FIG. 2. In the case of 4*M2-bit operation, the shift-right operation is performed M2 times (S226).
- the value of the output register is compared with 3 (S228).
- the value of the output register is smaller than 3, it is directly outputted as the result value (S250).
- the value of the output register is equal to 3 (S229), 0 is outputted as the result value (S252).
- Steps S228 to S248 are repeatedly performed until the value of the output register is equal to 3 or less.
- the value of the output register is stored as an input for the AND operation and the value of the output register is initialized to 0.
- One value of 0, 1 and 2 is added to the value of the output register depending on the result of the AND operation with binary value 0101 and one value of 0, 2 and 4 is added to the value of the output register depending on the result of the AND operation with binary value 1010. Consequently, in the case that the value of the output register is smaller than or equal to 3, the value of the output register or 0 is outputted as the result value, respectively, in the same manner described above.
- the input for the AND operation is reset and the value of the output register is initialized to 0 in the same manner described above, and the same process is repeatedly performed.
- the modulo 3 calculation for an input value 37 i.e., 0000 0000 0010
- the input value is further shifted by 4 bits to the right and the AND operation is sequentially performed on the least significant bits 0000 and the binary value 0101, and on the least significant bits 0000 and the binary value 1010. Since the AND operation results are both 0, 0 is added to the values of the output register twice. Subsequently, the input value is further shifted by 4 bits to the right and the AND operation is performed on the least significant bits 0000 in the same manner.
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Abstract
A modulo N calculating method for an M1*M2-bit binary integer, wherein N, Ml and M2 are integers, includes the steps of dividing the M1*M2-bit binary integer into M1 bits and performing AND operation on each M1 bits and a specific binary integer; and changing a value of an output register depending on the AND operation result and storing the value thereto. A modulo N calculating apparatus includes an input unit for receiving an M1*M2-bit binary integer, wherein N, M1 and M2 are integers; and an AND operation unit for performing AND operation on the M1*M2-bit binary integer and a specific binary integer. Furthermore, when the M1 and the N may be 4 and 3, respectively, the specific binary value may be 1010 or 0101.
Description
Description
METHOD AND APPARATUS FOR MODULO N CALCULATION Technical Field
[1] The present invention relates to a modulo calculating method in a modulo calculating apparatus, and more particularly, to a method and an apparatus capable of performing modulo N calculation on an Ml*M2-bit binary integer K, e.g., a 4*M2-bit binary integer K by using a simplified logic circuit (Ml and M2 are integers that are 0 or greater).
Background Art [2] Modulo 3 calculation is necessarily used to match speeds of turbo codes, including puncturing of the 3rd generation partnership project (3GPP). [3] A conventional modulo 3 calculation device includes a first counter for counting up to an input integer K and a second counter for counting 0, 1 and 2 circularly. [4] FIG. 1 is a flowchart illustrating a conventional method for modulo 3 calculation.
[5] In the conventional modulo 3 calculating method as shown in FIG. 1, until the first counter counts up to the input integer K, the second counter circularly counts 0, 1, 2, 0,
1, 2.... Then, the first counter completes counting up to the input integer K, the current value of the second counter is detected and outputted as a result value. [6] In such a modulo calculating apparatus, the numbers of counting times by the two counters correspond to the input integer, so that the greater the input integer is, the more time is spent.
Disclosure of Invention
Technical Problem [7] It is, therefore, an object of the present invention to provide a method of rapidly performing modulo N calculation using a simplified logic circuit.
Technical Solution [8] In accordance with an aspect of the invention, there is provided a modulo N calculating method for an Ml*M2-bit binary integer, wherein N, Ml and M2 are integers, the method including the steps of: dividing the Ml*M2-bit binary integer into
Ml bits and performing AND operation on each Ml bits and a specific binary integer; and changing a value of an output register depending on the AND operation result and storing the value thereto. [9] When the Ml is 4 and the N is 3, the specific binary integer may be binary value
0101. [10] Further, when the Ml is 4 and the N is 3, the specific binary integer may be binary value 1010.
[11] It is preferable that after the AND operation, a specific value depending on the AND operation result is added to the value of the output register.
[12] Further, the specific value may be added by the steps of (a) performing the AND operation on the Ml least significant bits of the Ml*M2-bit binary integer and a binary value 0101 ; (b) adding one value of 0, 1 and 2 to the value of the output register depending on the AND operation result of the step (a); (c) performing the AND operation on the Ml least significant bits of the Ml*M2-bit binary integer and a binary value 1010; (d) adding one value of 0, 2 and 4 to the value of the output register depending on the AND operation result of the step (c); (e) shifting the Ml*M2-bit binary integer by Ml bits to the right; and (f) performing the steps (a) to (e) M2 times.
[13] It is preferable that the specific value is added by the further steps of (g) after performing the step (f), determining whether the value of the output register is 3 or smaller; and (h) performing the steps (a) to (d) repeatedly, until it is determined in the step (g) that the value of the output register is 3 or smaller.
[14] In accordance with another aspect of the invention, there is provided a modulo N calculating apparatus including an input unit for receiving an M 1 *M2-bit binary integer, wherein N, Ml and M2 are integers; and an AND operation unit for performing AND operation on the Ml*M2-bit binary integer and a specific binary integer.
[15] When the Ml is 4 and the N is 3, the specific binary integer may be binary value
0101.
[16] Further, when the Ml is 4 and the N is 3, the specific binary integer may be binary value 1010.
[17] It is preferable that after the Ml*M2-bit binary integer is divided into Ml bits, the
AND operation unit performs AND operation on each M 1 bits and the specific binary integer and a specific value depending on the AND operation result is added.
Advantageous Effects
[18] As described above, in the method for modulo 3 calculation in accordance with the present invention, the modulo 3 calculation can be efficiently performed on any input integer K by addition of a logic circuit for the two AND operations, so that the modulo result can be obtained more rapidly. Brief Description of the Drawings
[19] The above and other objects and features of the present invention will become apparent from the following description of embodiments given in conjunction with the accompanying drawings, in which:
[20] FIG. 1 is a flowchart illustrating a conventional modulo 3 calculating method; and
[21] FIG. 2 and 3 are flowcharts illustrating a modulo N calculating method in a modulo
N calculating apparatus of preferred embodiment in accordance with the present invention.
Best Mode for Carrying Out the Invention
[22] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.
[23] FIG. 2 and 3 are flowcharts illustrating a modulo N calculating method in a modulo
N calculating apparatus of a preferred embodiment in accordance with the present invention.
[24] First, a determination is made as to whether an input integer K is subject to
Ml*M2-bit operation (S200), and an AND operation is performed on the Ml least significant bits of the input integer and a specific binary value. For example, when M 1=4 and N=3, an AND operation is performed on the 4 least significant bits of the input integer and a binary value 0101 (S202), as illustrated in FIG. 2.
[25] A determination is made as to what the AND operation result is and a value of an output register is changed depending on the AND operation result. The value of the output register may be initialized to 0.
[26] For example, when it is determined in step S204 that the AND operation result is binary value 0101, 2 is added to the value of the output register (S206). When the result is 0, 0 is added to the value of the output register (S216). When the AND operation result is neither binary value 0101 nor 0, 1 is added to the value of the output register (S218).
[27] The AND operation is then performed on the 4 least significant bits of the input integer and another binary value 1010 (S208). A determination is made as to what the AND operation result is and the value of the output register is changed depending on the AND operation result.
[28] For example, when it is determined in step S210 that the AND operation result is binary value 1010, 4 is added to the value of the output register (S212). When the AND operation result is 0, 0 is added to the value of the output register (S220). When the AND operation result is neither binary value 1010 nor 0, 2 is added to the value of the output register (S222).
[29] The input integer K is shifted by 4 bits to the right (S214). After the 4 least significant bits are discarded by this manner, the new 4 least significant bits are subject to the above steps from S202 to S222. This process corresponds to step S224 of FIG. 2. In the case of 4*M2-bit operation, the shift-right operation is performed M2 times (S226).
[30] After the shift-right operation is performed M2 times, the value of the output register is compared with 3 (S228). When the value of the output register is smaller than 3, it is
directly outputted as the result value (S250). When the value of the output register is equal to 3 (S229), 0 is outputted as the result value (S252).
[31] Steps S228 to S248 are repeatedly performed until the value of the output register is equal to 3 or less. When the value of the output register is greater than 3, the value of the output register is stored as an input for the AND operation and the value of the output register is initialized to 0. One value of 0, 1 and 2 is added to the value of the output register depending on the result of the AND operation with binary value 0101 and one value of 0, 2 and 4 is added to the value of the output register depending on the result of the AND operation with binary value 1010. Consequently, in the case that the value of the output register is smaller than or equal to 3, the value of the output register or 0 is outputted as the result value, respectively, in the same manner described above. In the case that the value of the output register is greater than 3, the input for the AND operation is reset and the value of the output register is initialized to 0 in the same manner described above, and the same process is repeatedly performed.
[32] As one example, the modulo 3 calculation for an input value 37, i.e., 0000 0000 0010
0101 in 16-bit operation using the method in accordance with the present invention will now be described.
[33] First, the AND operation is performed on the 4 least significant bits 0101 and a binary value 0101. Since the AND operation result is 0101, 2 is added to the value of the output register.
[34] The AND operation is then performed on the 4 least significant bits 0101 and binary value 1010. Since the result is 0, 0 is added to the value of the output register.
[35] Thus, the current value of the output register becomes 2.
[36] Then, the input value is shifted by 4 bits to the right and the AND operation is performed on the 4 least significant bits 0010 and the binary value 0101. Since the AND operation result is 0, 0 is added to the value of the output register.
[37] Then, the current value of the output register is still 2.
[38] The AND operation is then performed on the 4 least significant bits 0010 and the binary value 1010. Since the AND operation result is neither 1010 nor 0, 2 is added to the value of the output register.
[39] Thus, the value of the output register becomes 4.
[40] Next, the input value is further shifted by 4 bits to the right and the AND operation is sequentially performed on the least significant bits 0000 and the binary value 0101, and on the least significant bits 0000 and the binary value 1010. Since the AND operation results are both 0, 0 is added to the values of the output register twice. Subsequently, the input value is further shifted by 4 bits to the right and the AND operation is performed on the least significant bits 0000 in the same manner.
[41] Since the AND operation results are both 0 as well, 0 is added to the values of the
output register twice. Therefore, the final value of the output register becomes 4.
[42] Since the value of the output register is neither smaller than 3 nor equal to 3, a binary value 0100 is stored as the input for the AND operation and the value of the output register is initialized to 0. Depending on the result of the AND operation performed on 0100 and 0101, 1 is added to the value of the output register, and depending on the result of the AND operation performed on 0100 and 1010, 0 is added to the value of the output register. The final value of the output register becomes 1, which is smaller than 3. Accordingly, 1 is outputted as the result value of the modulo 3 calculation.
[43] While the invention has been shown and described with respect to the embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.
Claims
[1] A modulo N calculating method for an Ml*M2-bit binary integer, wherein N,
Ml and M2 are integers, the method comprising the steps of: dividing the Ml*M2-bit binary integer into Ml bits and performing AND operation on each Ml bits and a specific binary integer; and changing a value of an output register depending on the AND operation result and storing the value thereto.
[2] The method of claim 1, wherein when the Ml is 4 and the N is 3, the specific binary integer is binary value 0101.
[3] The method of claim 1, wherein when the Ml is 4 and the N is 3, the specific binary integer is binary value 1010.
[4] The method of claim 1, wherein after the AND operation, a specific value depending on the AND operation result is added to the value of the output register.
[5] The method of claim 4, wherein the specific value is added by the steps of:
(a) performing the AND operation on the Ml least significant bits of the Ml*M2-bit binary integer and a binary value 0101;
(b) adding one value of 0, 1 and 2 to the value of the output register depending on the AND operation result of the step (a);
(c) performing the AND operation on the Ml least significant bits of the Ml*M2-bit binary integer and a binary value 1010;
(d) adding one value of 0, 2 and 4 to the value of the output register depending on the AND operation result of the step (c);
(e) shifting the Ml*M2-bit binary integer by Ml bits to the right; and
(f) performing the steps (a) to (e) M2 times.
[6] The method of claim 5, the specific value is added by the further steps of:
(g) after performing the step (f), determining whether the value of the output register is 3 or smaller; and
(h) performing the steps (a) to (d) repeatedly, until it is determined in the step (g) that the value of the output register is 3 or smaller. [7] A modulo N calculating apparatus comprising: an input unit for receiving Ml*M2-bit binary integer, wherein N, Ml and M2 are integers; and an AND operation unit for performing AND operation on the Ml*M2-bit binary integer and a specific binary integer. [8] The apparatus of claim 7, wherein when the Ml is 4 and the N is 3, the specific binary integer is binary value 0101.
[9] The apparatus of claim 7, wherein when the Ml is 4 and the N is 3, the specific binary integer is binary value 1010. [10] The apparatus of claim 7, wherein after the Ml*M2-bit binary integer is divided into Ml bits, the AND operation unit performs AND operation on each Ml bits and the specific binary integer and a specific value depending on the AND operation result is added.
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US12/517,893 US8417757B2 (en) | 2006-12-07 | 2007-06-19 | Method and apparatus for modulo N calculation wherein calculation result is applied to match speeds in wireless communication system |
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KR1020070044653A KR100901280B1 (en) | 2006-12-07 | 2007-05-08 | Method and apparatus for modulo 3 calculation |
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Citations (4)
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US5249148A (en) * | 1990-11-26 | 1993-09-28 | Motorola, Inc. | Method and apparatus for performing restricted modulo arithmetic |
US5724279A (en) * | 1995-08-25 | 1998-03-03 | Microsoft Corporation | Computer-implemented method and computer for performing modular reduction |
US5793660A (en) * | 1997-04-14 | 1998-08-11 | Hewlett-Packard Company | Circuit for finding m modulo n |
US7031995B2 (en) * | 2000-05-05 | 2006-04-18 | Infineon Technologies Ag | Method and device for modulo calculation |
-
2007
- 2007-06-19 WO PCT/KR2007/002971 patent/WO2008069383A1/en active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5249148A (en) * | 1990-11-26 | 1993-09-28 | Motorola, Inc. | Method and apparatus for performing restricted modulo arithmetic |
US5724279A (en) * | 1995-08-25 | 1998-03-03 | Microsoft Corporation | Computer-implemented method and computer for performing modular reduction |
US5793660A (en) * | 1997-04-14 | 1998-08-11 | Hewlett-Packard Company | Circuit for finding m modulo n |
US7031995B2 (en) * | 2000-05-05 | 2006-04-18 | Infineon Technologies Ag | Method and device for modulo calculation |
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