WO2008066605A2 - System for optimizing the performance and reliability of a storage controller cache offload circuit - Google Patents

System for optimizing the performance and reliability of a storage controller cache offload circuit Download PDF

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Publication number
WO2008066605A2
WO2008066605A2 PCT/US2007/021692 US2007021692W WO2008066605A2 WO 2008066605 A2 WO2008066605 A2 WO 2008066605A2 US 2007021692 W US2007021692 W US 2007021692W WO 2008066605 A2 WO2008066605 A2 WO 2008066605A2
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
blocks
cache
nonvolatile memories
raid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2007/021692
Other languages
English (en)
French (fr)
Other versions
WO2008066605B1 (en
WO2008066605A3 (en
Inventor
Mohamad El-Batal
Charles Nichols
John Sherman
Keith Holt
Jason Stuhlsatz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
LSI Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Corp filed Critical LSI Corp
Priority to CN2007800439252A priority Critical patent/CN101542449B/zh
Priority to EP07852642A priority patent/EP2097822A4/en
Priority to JP2009538383A priority patent/JP4996693B2/ja
Publication of WO2008066605A2 publication Critical patent/WO2008066605A2/en
Publication of WO2008066605A3 publication Critical patent/WO2008066605A3/en
Publication of WO2008066605B1 publication Critical patent/WO2008066605B1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1441—Resetting or repowering
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2211/00—Indexing scheme relating to details of data-processing equipment not covered by groups G06F3/00 - G06F13/00
    • G06F2211/10—Indexing scheme relating to G06F11/10
    • G06F2211/1002—Indexing scheme relating to G06F11/1076
    • G06F2211/1009—Cache, i.e. caches used in RAID system with parity
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2211/00—Indexing scheme relating to details of data-processing equipment not covered by groups G06F3/00 - G06F13/00
    • G06F2211/10—Indexing scheme relating to G06F11/10
    • G06F2211/1002—Indexing scheme relating to G06F11/1076
    • G06F2211/1059—Parity-single bit-RAID5, i.e. RAID 5 implementations

Definitions

  • the present invention relates to storage controllers generally and, more particularly, to a method and/or apparatus for optimizing the performance and reliability of a storage controller cache offload circuit.
  • a conventional storage controller Upon power loss of AC power, a conventional storage controller is forced to offload a cache content as quickly and reliably as possible from a cache memory to a local persistent storage device using power from a limited-reserve battery backup unit.
  • the persistent storage device (i) is commonly local to avoid counting on remote devices to be powered up and (ii) utilizes very low amounts of power to avoid large batteries. The very low power results in the persistent storage device having a limited access bandwidth. Large batteries are very expensive and have decreasing reliability over time.
  • the present invention concerns a method for offloading a cache memory.
  • the method generally comprises the steps of (A) reading all of a plurality of cache lines from the cache memory in response to an assertion of a signal to offload of the cache memory, (B) generating a plurality of blocks by dividing the cache lines in accordance with a RAID configuration and (C) writing the blocks among a plurality of nonvolatile memories in the RAID configuration, wherein each of the nonvolatile memories has a write bandwidth less than a read bandwidth of the cache memory .
  • the objects, features and advantages of the present invention include providing a method and/or apparatus for optimizing the performance and reliability of a storage controller cache offload circuit that may (i) arrange multiple nonvolatile memories in a RAID configuration, (ii) write two or more of the nonvolatile memories substantially simultaneously,
  • FIG. 1 is a block diagram of a system in accordance with a preferred embodiment of the present invention
  • FIG. 2 is a diagram of an example implementation of a nonvolatile memory circuit
  • FIG. 3 is a flow diagram of an example method for offloading a cache memory
  • FIG. 4 is a diagram of an example RAID 0 configuration
  • FIG. 5 is a diagram of an example RAID 1 configuration
  • FIG. 6 is a diagram of an example RAID 5 configuration.
  • the present invention generally achieves a rapid cache offload architecture using multiple nonvolatile drives in parallel.
  • the nonvolatile drives may be arranged in a RAID configuration, such as a RAID 0 configuration, a RAID 1 configuration or a RAID 5 configuration.
  • Other RAID configuration may be implemented to meet the criteria of a particular application.
  • a parallel write nature of several RAID configurations generally allows for a higher performance and a higher reliability on the cache offload interface compared with the conventional techniques.
  • the system (or apparatus) 100 may be implemented as a cache-based processing system.
  • the system 100 generally comprises a circuit (or module) 102, a circuit (or module) 104, a circuit (or module) 106, a circuit (or module) 108, a circuit (or module) 110 and a circuit (or module) 112.
  • a signal e.g., PWR
  • a signal e.g., OFFLOAD
  • An interface 114 may enable the circuit 102 and the circuit 104 to communicate with each other.
  • the circuit 104 may communicate with the circuit 106 through an interface 116.
  • An interface 118 may permit the circuit 104 to communicate with the circuit 108.
  • the circuit 104 may communicate with the circuit 112 through an interface 120.
  • the circuit 102 may be implemented as a processor circuit.
  • the circuit 102 may be operational to perform a variety of functions by executing software programs.
  • the circuit 102 may read and write instructions and/or data for the software programs to and from the circuits 106, 108 and 112 through the circuit 104.
  • the circuit 104 may be implemented as a memory controller circuit.
  • the circuit 104 may be operational to control the circuit 106, the circuit 108 and the circuit 112.
  • the circuit 104 may exchange the data and the instructions of the software programs with the circuit 102 through the processor interface 114.
  • the data and the instructions may be exchanged between the circuit 104 and (i) the circuit 106 through the cache interface 116, (ii) the circuit 108 through the Flash interface 118 and (iii) the circuit 112 through the memory interface 120.
  • the circuit 104 may be further operational to offload all of the information (e.g., data and instructions) stored in the circuit 106 into the circuit 108 through the interface 118 (see arrow 128) in response to an asserted state (e.g., a logical low) of the signal OFFLOAD.
  • information e.g., data and instructions
  • the circuit 106 may be implemented as a volatile memory.
  • the circuit 106 may be implemented as a volatile cache memory.
  • the circuit 106 is generally operational to buffer the data and the instructions used and generated by the software executing in the circuit 102.
  • the information stored in the circuit 106 may be arranged as cache lines 124a-124n. Each of the cache lines 124a-124n may be swapped with the circuit 112 based on cache hits and cache misses.
  • the cache lines may be read from the circuit 106 at a first read bandwidth and written at a first write bandwidth.
  • the circuit 108 may be implemented as an array of nonvolatile memories 126a-126d.
  • the memories (or components) 126a-126d may be arranged in a RAID (Redundant Array of Independent Disks) configuration.
  • each memory "disk" 126a-126d of the circuit 108 may be implemented as a Flash memory.
  • Other nonvolatile memory technologies may be implemented to meet the criteria of a particular application.
  • Information may be written into each of the memories 126a-126d at a second write bandwidth and read at a second read bandwidth.
  • the circuit 110 may be implemented as a backup power unit.
  • the circuit 110 may be operational to store, convert, regulate and/or filter electrical power received in the signal PWR into one or more power networks suitable for use by the circuits 102, 104, 106, 108 and 112.
  • the circuit 110 may also be operational to provide electrical power for a limited time suitable to operate at least the circuits 104, 106 and 108 for a sufficient time to offload the information from the circuit 106 into the circuit 108.
  • the circuit 110 may monitor the condition of the power flowing in via the signal PWR and assert the signal OFFLINE in response to a severe drop and/or complete loss of power in the signal PWR.
  • the circuit 110 may be implemented as one or more batteries.
  • the circuit 110 may be implemented as one or more super-capacitors or ultra-capacitors.
  • the circuit 112 may be implemented as a main memory circuit.
  • the circuit 112 may be implemented as a volatile random access memory.
  • the circuit 112 may be operational to store the data and the instructions for the software executing on the circuit 102.
  • the circuit 112 may provide cache lines to the circuit 106 and receive cache lines from the circuit 106 as determined by the circuit 104.
  • the circuit 108 may comprise multiple sockets 130a-130d.
  • Each of the sockets (or ports) 130a- 13Od is generally arranged to couple to a single memory 126a- 126d. Coupling may include physical connections, electrical power connections and communication connections.
  • the sockets 130a-130d may be populated by a single memory component (e.g., 126a) .
  • two or more memories 126a-126d may be installed in the sockets 130a-130d.
  • the method 140 generally implements a rapid offload method that moves data from the circuit 106 to the circuit 108.
  • the method 140 generally comprises a step (or block) 142, a step (or block) 144, an optional step (or block) 146 and a step (or block) 148.
  • the method 140 may be triggered by an assertion of the signal OFFLOAD.
  • Other triggers such as a command from the circuit 102, may also initiate the method 140.
  • the circuit 110 may assert the signal OFFLOAD upon detecting a loss of electrical power in the signal PWR. The assertion of the signal OFFLOAD may be sensed by the circuit 104.
  • the circuit 104 may read (offload) the cache lines 124a-124n from the circuit 106 in the step 144.
  • a transfer speed of the information from the circuit 106 to the circuit 104 may be governed by a read bandwidth of the circuit 106.
  • the circuit 104 may/may not stripe the information in the cache lines 124a-124n in the step 146.
  • the blocks of information/stipes of information and error correction information (if any) may then be written to the memories 126a-126d by the circuit 104 in the step 148.
  • a transfer speed of the blocks/stripes from the circuit 104 to the circuit 108 may be determined by write bandwidths of the memories 126a-126d. Since the information may be written from the circuit
  • the combined write bandwidth to the memories 126a-126d may be larger (faster) than the read bandwidth from the circuit 106.
  • the higher combined write bandwidth generally reduces a time consumed executing the transfer compared with conventional techniques.
  • An architecture of the system 100 may utilize removable nonvolatile memory components 126a-126d at low cost.
  • Example memory components 126a-126d may include, but are not limited to, secure digital (SD) Flash cards and USB Flash drives.
  • the present invention generally uses several nonvolatile memories such that the capacity and the speed of the nonvolatile memories may be increased using RAID technology to create a virtual nonvolatile memory (circuit 108) that is larger and faster than a single common nonvolatile memory element.
  • the circuit 104 and the circuit 108 may be scaled in proportion to the amount of cache ordered by the customer.
  • the circuit 104 may support cache size options of 8 gigabytes (GB) , 16GB and 32GB in the circuit 106.
  • the circuit 104 may be configured to control several (e.g., four) memory components 126a-126d in the circuit 108, each with a size of 8GB.
  • an 8GB cache system 100 may be built with a single 8GB memory (e.g., 126a) .
  • a 16GB cache system 100 may be built with two 8GB memories (e.g., 126a and
  • a 32GB cache system would be built with four 8GB memories
  • each of the memories 126a-126d has an example write speed of 20 megabytes per second (MB/sec) .
  • the write bandwidth to the circuit 108 is generally doubled due to using RAID technology to configure two of the memories (e.g., 126a and 126b) .
  • the cache offload time may be maintained at approximately 400 seconds. Larger numbers of the memory components 126a-126d may be utilized to decrease the offload time, permit larger cache sizes and/or implement other RAID configurations.
  • the RAID 0 configuration may implement a striped array made from the memory components 126a-126d.
  • the circuit 104 may group the cache lines 124a-124n read from .the circuit 106 into blocks (e.g., A-H). Each of the individual blocks A-H may be written to a single memory 126a-126d, with several blocks written substantially simultaneously along parallel paths 150a-150d. For example, the circuit 104 may write the block A to the memory 126a, the block B to the memory 126b, the block C to the memory 126c and the block D to the memory 126d in parallel or in a staggered start sequence.
  • the circuit 104 may begin writing the block A while still assembling the block B from the cache lines 124a- 124n. Once the block B is ready, the circuit 104 may start writing the block B, continue the write of the block A and begin assembling the block C.
  • a RAID 0 configuration is generally implemented with at least two of the memories 126a-126d.
  • the RAID 1 configuration generally implements duplexing of mirrored pairs using multiple (e.g., eight) of the memories 126a-126h.
  • the circuit 104 may group the cache lines 124a-124n read from the circuit 106 into the blocks A-H.
  • Each of the individual blocks A-H may be written to two of the memories 126a-126h, with several blocks written substantially simultaneously along the paths 150a-15Oh.
  • the block A may be written to both of the memories 126a and 126b
  • the block B may be written to both of the memories 126c and 126d, and so on.
  • the RAID 1 configuration generally provides for fault tolerance of the stored information. For each memory pair, the blocks written into the pair may be recovered even if one of the memory components has failed.
  • a RAID 1 configuration may be implemented with at least four of the memories 126a-126h.
  • the RAID 5 configuration may implement data striping with distributed parity.
  • the circuit 104 may read the cache lines 124a-124n from the circuit 106 in response to assertion of the signal OFFLOAD.
  • the read information may be assembled into the blocks A-H.
  • Each of the blocks A-H may then be striped.
  • the block A may become stripes AO, Al and A2
  • block B may become stripes BO, Bl and B3
  • the block C may become stripes CO, C2 and C3
  • the block D may become stripes Dl, D2 and D3 and so on.
  • the stipes of a given block may be written in order into a single memory 126a- 126d.
  • a parity stripe may be calculated by the circuit 104 for all stipes in a same rank and then written into a single memory 126a-126d. For example, a zero rank parity (e.g., 0
  • PARITY may be generated from the stripe AO, a stipe BO and a stripe CO and written into the memory 126d.
  • a first rank parity may be generated from the stripe AO, a stipe BO and a stripe CO and written into the memory 126d.
  • a RAID 5 configuration generally provides an ability to recover the stored information in the event of a single memory component 126a-126d failure.
  • the use of the distributed parity may permit efficient use of the memories 126a-126d.
  • a RAID 5 configuration may be implemented with three or more of the memories 126a-126d.
  • Other RAID configurations may be implemented in the circuit 108 to meet the criteria of a particular application.
  • FIGS. 1 and 3 may be implemented using a conventional general purpose digital computer programmed according to the teachings of the present specification, as will be apparent to those skilled in the relevant art(s).
  • Appropriate software coding can readily be prepared by skilled programmers based on the teachings of the present disclosure, as will also be apparent to those skilled in the relevant art(s).
  • the present invention may also be implemented by the preparation of ASICs, FPGAs, or by interconnecting an appropriate network of conventional component circuits, as is described herein, modifications of which will be readily apparent to those skilled in the art(s).
  • the present invention thus may also include a computer product which may be a storage medium including instructions which can be used to program a computer to perform a process in accordance with the present invention.
  • the storage medium can include, but is not limited to, any type of disk including floppy disk, optical disk, CD-ROM, magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, Flash memory, magnetic or optical cards, or any type of media suitable for storing electronic instructions.
  • the term "simultaneously” is meant to describe events that share some common time period but the term is not meant to be limited to events that begin at the same point in time, end at the same point in time, or have the same duration.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
PCT/US2007/021692 2006-11-27 2007-10-09 System for optimizing the performance and reliability of a storage controller cache offload circuit Ceased WO2008066605A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2007800439252A CN101542449B (zh) 2006-11-27 2007-10-09 优化存储控制器高速缓存卸载电路性能和可靠性的系统
EP07852642A EP2097822A4 (en) 2006-11-27 2007-10-09 SYSTEM FOR OPTIMIZING THE PERFORMANCE AND RELIABILITY OF A MEMORY DISCHARGE CIRCUIT FOR STORAGE CONTROLLER COVER
JP2009538383A JP4996693B2 (ja) 2006-11-27 2007-10-09 記憶装置コントローラキャッシュオフロード回路の性能および信頼性を最適化するためのシステム

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/604,631 US7904647B2 (en) 2006-11-27 2006-11-27 System for optimizing the performance and reliability of a storage controller cache offload circuit
US11/604,631 2006-11-27

Publications (3)

Publication Number Publication Date
WO2008066605A2 true WO2008066605A2 (en) 2008-06-05
WO2008066605A3 WO2008066605A3 (en) 2008-09-18
WO2008066605B1 WO2008066605B1 (en) 2008-10-30

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PCT/US2007/021692 Ceased WO2008066605A2 (en) 2006-11-27 2007-10-09 System for optimizing the performance and reliability of a storage controller cache offload circuit

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US (1) US7904647B2 (enExample)
EP (1) EP2097822A4 (enExample)
JP (1) JP4996693B2 (enExample)
KR (1) KR101214206B1 (enExample)
CN (1) CN101542449B (enExample)
WO (1) WO2008066605A2 (enExample)

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CN101542449A (zh) 2009-09-23
WO2008066605B1 (en) 2008-10-30
WO2008066605A3 (en) 2008-09-18
KR101214206B1 (ko) 2012-12-20
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