WO2008064880A1

WO2008064880A1 - Movable phase step micro mirror and a method for its manufacture

Info

Publication number: WO2008064880A1
Application number: PCT/EP2007/010325
Authority: WO
Inventors: Jan Uwe Schmidt; Thor Bakke; Martin Friedrichs; Peter Dürr
Original assignee: Micronic Laser Systems Ab; Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Priority date: 2006-11-28
Filing date: 2007-11-28
Publication date: 2008-06-05
Also published as: DE102006057568A1

Abstract

The invention relates to micro-optical elements having a substrate, and to a method for manufacturing these elements. The substrates have at least one vertical step at an optically effective surface. They can be deflected, preferably electrostatically, around a rest position. It is the object of the invention to provide micro-optical elements which have vertical steps at optically effective surfaces, observe a homogeneous reflectivity at both sides of the vertical step(s) and maintain a high planarity permanently and independently of the temperature. The micro-optical elements in accordance with the invention are formed with a substrate that is made as one piece and from a homogeneous material or from a nanolaminate.

Description

MOVABLE PHASE STEP MICRO MIRROR AND A METHOD FOR ITS MANUFACTURE

The invention relates to micro-optical elements hav- ing a substrate, and to a method for manufacturing these elements. The substrates have at least one vertical step at an optically effective surface. They can be deflected, preferably electrostatically, a- round a rest position.

In addition to the increase in stiffness and strength against twisting and deflection, vertical steps can also achieve optical influences. A phase modulation of reflected or transmitted electromagnetic waves is possible, for instance. In this connection, a use for optical grids as well as for the anti-reflection coating of surfaces by grid-like interference structures is possible. A particular application is represented by spatial light modulators (SLM) in the form of matrices which can be formed with a plurality of reflecting elements which can be deflected in a translatory or rotary manner. To be able to use phase contrast techniques in particular for the exposure of masks or wafers on an application of such elements in microlithography, it is necessary to realize mutually associated deflection states of the micro-optical elements for which electromagnetic radiation can be reflected with equal intensity, but with a phase position displaced by up to 180° .

Conventional SLMs in which the tiltable micro- mechanical elements have a planar surface are not able to do this . They achieve maximum reflectivity in the resting state. Radiation phase-shifted by 180° with respect to the electromagnetic radiation reflected in the resting state can admittedly demon- strated for the deflected element, but only with a fraction of the intensity. The phase contrast can thereby only be utilized with limitations. It has therefore been proposed for the solution of the problem to introduce an optical path difference of an odd number multiple of λ/4 (λ working wavelength) between the planoparallel reflecting zones separated by the axis of rotation, with the reflectivity of both zones having to remain approximately constant. In this case, the intensity reflected perpendicularly by the non-deflected element is minimal and increases to a maximum value of approximately half the incident intensity as the deflection increases. As demanded, the phase position of the reflected radiation differs by 180° for the two possible directions of the deflec- tion. A suitable micro-optical element and possibilities for its manufacture are described in WO 2005/057291 Al.

In this connection, conventionally transparent or semi-transparent layers are applied to a substrate and structured lithographically to form vertical steps, for example to achieve the mentioned path differences. A corresponding embodiment can be illustrated by Figure 24. A substrate 10 is here held at a carrier 1 by means of posts 11. Electrodes 3 and 4 for an electrostatic deflection of the substrate 10 are present on the carrier 1. The vertical step has been made with an additional layer 10.1 formed by a mate- rial differing from the substrate material.

In the known solutions, problems occur, however, with respect to the planarity and to an increased temperature dependence .

In this context, a substrate without a coating can be reliably made available in planar form. If then, however, a coating takes place, the coated zone only is and remains planar in the desired form if no forces act at the interface to the coating. However, this is not the case as a rule since the layer tensions are not the same in the substrate and in the coating.

Since the thermal coefficients of expansion of the coating and the carrier are furthermore not identical, mechanical stresses are generated by temperature changes (e.g. caused by laser radiation) or by local temperature gradients (heat loss from circuits optionally integrated into the SLM) in the reflecting elements of the described kind, such as in a bimetallic strip, said stresses resulting in a bending or a deterioration of the planarity, whereby the imaging properties of the element deteriorate dramatically.

The different reflectivity in coated and uncoated zo- nes can result in a locally different heating, and thus in high mechanical stresses, on operation with extremely short laser pulses. In the extreme case, even a delamination of the coating can occur as the case may be.

On the manufacture of micro-optical elements in question, it is necessary to observe a permanent and temperature-independent planarity as well as in particular to take account of further parameters with opti- cally effective surfaces over their total area.

It is thus desired in micro-optical elements with phase-shifting properties to be able to set and maintain the phase jump or jumps in an exactly reproduci- ble manner and as homogeneously as possible. A homogeneous reflectivity or transparency should be able to be maintained over the total optically effective surface .

A use should also be possible in the wavelength range of DUV radiation (in particular at 248 nm, 193 nm) VUV (157 nm) and EUV radiation (in particular at 13.4 nm) .

Known and proven technologies should be made use of in the manufacture .

It is therefore the object of the invention to provide micro-optical elements which have vertical steps at optically effective surfaces, maintain a homogeneous reflectivity at both sides of the vertical step(s) and maintain a high planarity permanently and independent of the temperature .

This object is solved in accordance with the inven- tion by micro-optical elements having the features of claim 1. They can be manufactured using a method in accordance with claim 15. Advantageous uses are named by claim 25.

Advantageous aspects and further developments of the invention can be achieved using features designated in the subordinate claims.

The micro-optical elements having a substrate in ac- cordance with the invention are made such that at least one vertical step is formed at an optically effective surface.

The substrate having the vertical step(s) is formed in this connection as one piece from a homogeneous material or from a nanolaminate . In this connection, the optically effective upper side should be formed directly by the substrate. There is, however, the possibility of providing the total upper side with a suitable coating, for example a highly reflective coating. Such a coating should likewise be formed from a homogeneous material and have a constant layer thickness over the total surface to avoid the disadvantages of the solution known from WO 2005/057291 Al. The layer can be reflective for the electromagnetic radiation. The material forming the coating should have a thermal coefficient of expansion which is at least almost the same as the substrate and a tension state adapted thereto, at least when it is only applied to the upper side. Differences in the stress state and/or the thermal coefficient of expansion between substrate and a coating at its upper side can be largely compensated if a coating which is the same with respect to material, stress state and layer thickness is also formed at the lower side. The substrate can be enclosed by two layers at its upper side and lower side. The two layers should enclose the substrate symmetrically and/or each have the same layer thickness. Materials which form the substrate should have an amorphous or nanoc- rystalline structure, in particular when the layers are made of aluminum.

The one, or optionally also the plurality of vertical step(s) is formed directly at the substrate without a further material being present as an additional layer for this purpose. No additional material or material mixture is therefore present at the substrate with which the one or the plurality of vertical steps is formed.

A layer stack consisting of a plurality of mutually connected individual layers should be called a nano- laminate here. A substrate formed with a nanolaminate can be formed with at least three individual thin layers (films) which differ in the manner of the material and/or in other layer properties. A nanolaminate can preferably be formed with layers made of at least two different materials or material mixtures. A structure of alternating thin layers of different materials can advantageously be selected for a substrate made as a nanolaminate in this connection, said structure being symmetrical to the center plane of the nanolaminate in the direction of the layer normal . To achieve a phase-shifting effect already addressed, the at least one vertical step can have a step height of λ/4 or an odd number multiple of λ/4 of the se- lected working wavelength of an electromagnetic radiation. It can then advantageously be arranged at an axis of rotation and/or aligned parallel thereto at a micro-optical element pivotable around the axis of rotation.

An optical grid can, however, also be made available with a plurality of vertical steps aligned parallel to one another and arranged at a suitable spacing from one another.

In a particularly advantageous embodiment, the substrate having vertical step(s) can have a constant layer thickness over the total surface. Slight deviations at the transition of the vertical step can, ho- wever, be tolerated in this context.

Electrodes can be arranged beneath the substrate, that is at the side disposed opposite an optically effective surface, and can be electrically controlled in a suitable manner to achieve a desired deflection/pivoting .

The substrate of the micro-optical element can be connected to a carrier by means of posts and can be kept at a spacing from said carrier. The substrate can be connected to the posts via elastically deform- able spring elements . The spring elements can be made as torsion springs with a micro-optical element pivotable around an axis of rotation.

The carrier can preferably be a silicon substrate in the form of a wafer with an integrated CMOS circuit which is in turn electrically contacted to the already addressed electrodes.

A plurality of micro-optical elements in accordance with the invention can naturally also be made available in the form of an array.

A procedure can be followed in the manufacture such that at least one sacrificial layer is first formed on a surface of a carrier. The sacrificial layer should have a homogeneous layer thickness and only a slight surface roughness. It can preset the spacing of the substrate to the surface of the carrier after its later removal. Sacrificial layer (s) can be formed using amorphous silicon, silicon dioxide, photoresist, polyimide, Ti_xAI_y, aluminum, Mo_xSi_yN_z, Ta_xSi₇N₂, Co_xSi₇N₂, Si_xN_yO₂, GeO_x (where 0<x≤l, O≤y, z<l) and/or molybdenum .

The substrate is then formed on the one sacrificial layer, optionally, however, also on a second sacrificial layer, or is applied there. The formation of the substrate can take place by the formation of a layer. This can be achieved by an evaporation known per se in vacuum, by a CVD process or also by sputtering. The substrate can be made from silicon, aluminum, but also from another material which has the desired optical properties in the working wavelength, for exam- pie also from a nanolaminate . Aluminum can, for example, be used as a highly reflective material.

Alternatively to this, there is, however, also the possibility of utilizing a separate element, which is connected to the surface of a sacrificial layer, e.g. by bonding, in a firmly bonded manner for the manu- facture of a substrate having vertical step(s) . How the vertical step(s) is/are then formed in the two alternatives will be explained in the following in the description of embodiments .

After the formation of a substrate, openings are formed with the help of which a removal of the sacrificial layer can take place by etching processes and the substrate can thereby be exposed.

The forming of the substrate with vertical step(s) can be achieved by a specific embodiment of a second sacrificial layer, in the coating with substrate material in two steps and a local structuring, but also by structuring of an element connected to the sacrificial layer. Corresponding possibilities for this again follow below in the description of three examples .

There are shown:

Figure 1, a sectional representation of a first example of a micro-optical element in accordance with the invention having a vertical step and being tiltable around an axis of rotation;

Figure 2, a sectional representation of a second example of a micro-optical element in accordance with the invention having a vertical step and being til- table around an axis of rotation;

Figure 3, a sectional representation of a third example of a micro-optical element in accordance with the invention having a vertical step and being tiltable around an axis of rotation; Figures 4 to 6, successive first method steps for the manufacture of the three examples in accordance with Figures 1 to 3 ;

Figure 7, the embodiment of stoppers in the examples in accordance with the Figures 1 and 2;

Figures 8 to 11, successive further method steps for the manufacture of the first example in accordance with Figure 1;

Figures 12 to 15, successive further method steps for the manufacture of the second example in accordance with Figure 2 ;

Figures 16 to 23, successive further method steps for the manufacture of the third example in accordance with Figure 3 ; and

Figure 24, an example of the prior art.

A carrier 1 is used for the manufacture of the three examples of micro-optical elements in accordance with the invention. Said carrier is a silicon substrate having a fixedly wired electrode array or an integrated CMOS circuit. The latter is contacted via electrically conductive connections to a counterelec- trode 3, a substrate electrode 4 and an address elec- trode 5. The named connections are embedded in a dielectric passivation layer 2 which is formed from silicon dioxide and/or aluminum oxide.

A dielectric passivation layer 6 is applied thereto, for example in CVD technology. It is later smoothed, for example by chemically mechanical polishing and is partly removed in this process. It forms an electrical insulation between the electrodes 3, 4 and 5. Stoppers 7 can then be deposited as layers on electrodes and structured. They can avoid an electrical short circuit between the substrate 10 and the electrodes 3, 4 and 5 in the event of deflections accidentally occurring which are too high.

A first sacrificial layer 8 is deposited thereon in CVD technology or sputtering technology or by spin coating of a liquid precursor. They can, for example, be made of amorphous silicon, silicon oxide or of a polymer (e.g. polyimide) . It determines the later spacing between the substrate 10 and the electrodes 3, 4 and 5 and thus also defines the voltage deflection characteristic on the electrical operation with deflection of the micro-optical element.

Up to this method step, the procedure in the manufac- ture of the three examples of micro-optical elements in accordance with the invention does not differ from one another. In the example in accordance with Figure 3, only no stoppers 7 are formed.

In the first example, however, a second sacrificial layer 9 is then deposited whose layer thickness corresponds to an odd number multiple of λ/4 of a preset working wavelength. The second sacrificial layer 9 should differ from the material of the first sacrifi- cial layer 8 with respect to its composition such that a structuring of the sacrificial layer 9 is possible selectively with respect to the sacrificial layer 8 (Fig. 8) .

The second sacrificial layer 9 is then structured and removed locally selectively with respect to the sac- rificial layer 8 by an etching process so that it only remains in the zones in which zones of vertical steps which are later raised are formed (Fig. 9) .

The arrangement and dimension with step height of the vertical step(s) are already fixed at this time.

Subsequently, the structuring of openings takes place in the sacrificial layer 8 at the location of the Ia- ter connections between the carrier 1 and the substrate 10. The formation of the substrate 10 by a coating process then takes place on this topology formed by sacrificial layer 8 and partially sacrificial layer 9. The posts 11 which represent the connection between the electrode 4 and the substrate 10 are formed by the portion of the substrate material deposited in these openings .

Optionally, a reflective layer can be formed over the full area on the upwardly facing upper side of the substrate 10 provided with a vertical step. A further compensating layer which compensates the layer stress and thermal expansion of the reflective layer on the upper side can additionally be formed on the rear si- de of the substrate 10 disposed opposite the upper side for the observation of a temperature-independent planarity. In this connection, these layers directly enclosing the substrate 10 should, where possible, be made of the same material and with the same layer thickness since the thermal compensation of the layer stack structure can be ensured by the symmetrical compensation.

A substrate 10 can be made, for example, from tita- nium aluminum (having a higher strength and stiffness) and the layers can be made from aluminum. Subsequently, openings 13 are formed through the substrate 10 and parts of the sacrificial layers 8 and 9, e.g. by reactive ion etching (RIE), whereby the lateral boundaries of the micro-optical element and of the posts 11 are defined. The substrate 10 is connected to the electrode 4 and to the carrier 1 via spring elements, not shown here, between the substrate 10 and the posts 11, as shown in Figure 10.

In a final anisotropic dry etching process, the sacrificial layers 8 and 9 between the substrate 10 and the carrier 1 are completely removed and the substrate 10 is exposed. The fully manufactured micro- optical element is shown in Figure 1.

In this example, the raised and sunk zones of the substrate 10 have the same structure, thus have an identical reflectivity, layer thickness, inherent voltage, electrical and thermal conductivity as well as, with a corresponding process optimization, disappearing middle stress gradients. A thermal expansion which may occur is the same all over substrate 10. A permanently high temperature-independent planarity is ensured.

On the manufacture of modified micro-optical elements in accordance with the invention in accordance with Figure 2, the same procedure as in the first example is initially followed.

After completion of the first sacrificial layer 8, however, openings 13' are formed through it with the exception of the electrode 4 in order later to be able to form posts 11 there with which the substrate 10 remains connected to the carrier 1 after removal of the sacrificial layer 8. The sacrificial layer 8 can be made from amorphous silicon, silicon oxide, but also from polyimide. A first part of the substrate material is then deposited in a thickness which corresponds to the desired vertical step of λ/4 of the preset wavelength over the whole area of the sacrificial layer 8 and into the openings 13 ' and subsequently removed again locally in the zones where later the regions of a lower position are disposed by an etching process (preferably RIE) , as is shown in the right hand half in Figure 12.

Following on from this, the total surface is coated homogeneously with a further layer of substrate mate- rial (Fig. 13) .

With the help of openings 13 formed e.g. by means of RIE etching through the substrate material for the later formation of posts 11 and at the outer edge of a substrate 10, the sacrificial layer 8 below the substrate 10 can subsequently be removed e.g. by isotropic etching.

A finished micro-optical element completed in this manner is then shown in Figure 15.

Although the substrate 10 should be formed in two steps by coating in this second example, the desired advantages are given with respect to the prior art. The substrate 10 is also formed from a single material in this case. The reflectivity is thereby again the same over the total surface in raised and sunk regions. It is thermally compensated, i.e. temperature fluctuations do not influence the planarity. Gradients of the layer stresses impairing the planarity can be avoided in making the layers forming the substrate 10.

In the manufacture of a third example, the procedure can again be the same initially as in the two previ- ously described examples.

Subsequent to the formation of the one sacrificial layer 8, no further layers are formed by deposition initially (Fig. 16) .

Instead, a membrane 12 is applied to the sacrificial layer 8 by bonding. In this connection, it can preferably be a thin membrane of an SOI (silicon on insulator) wafer. However, different membranes, for exam- pie metallic individual layers or nanolaminates can also be used.

The SOI wafer can be abraded down to the oxide layer after the bonding process . The oxide layer then ex- posed is likewise removed by an etching process so that ultimately only the membrane 12 bonded on sacrificial layer 8 remains from which the substrate 10 is formed in the following.

Subsequent to this, the formation of the vertical step takes place by masking and dry etching at the previously exposed surface of the membrane 12, as is shown in Figure 17. Openings 13 are first formed by means of RIE etching up to the sacrificial layer 8 in the membrane 12 which now forms the substrate 10.

An auxiliary layer of silicon oxide can be formed on the total surface and in the openings 13 by means of PE-CVD technology to form posts 11 (Fig. 19) .

The material of the auxiliary layer 14 and the mate- rial of the sacrificial layer 8 are again removed by an etching process for openings 13 ' provided for the post formation (Fig. 20) .

The total surface is then coated with a conductive material for the formation of posts 11, as can be seen from Figure 21.

This material is removed locally selectively with re- spect to the auxiliary layer 14 by etching with the exception of the zone close to the posts 11. The posts 11 with which the substrate 10 can be held at the carrier 1 are thereby formed (Fig. 22) .

Subsequent to this, the auxiliary layer 14 and the sacrificial layer 8 can be removed through the openings 13. The substrate 10 with the vertical step is then formed with the bonded membrane and is connected in a firmly bonded manner with the electrode 4 and the carrier 1 via posts 11, as shown in Figure 23.

The working of the element 12 for the formation of vertical steps can take place by suitable wet etching processes and/or dry etching processes (with silicon membranes e.g. using wet etching based on KOH, TMAH, HF/HN03 or using chlorine based or fluorine based dry etching C12, SF6, XeF2). Alternatively, on the use of a monocrystalline silicon membrane as the element 12, the vertical step(s) can be formed with the help of local oxidation of silicon using a nitride mask (LOCOS process) . For this purpose, a silicon nitride layer is deposited on an SOI wafer at the surface. The silicon is again exposed locally in the zones later disposed at a lower location by a subsequent et- ching of the silicon nitride and it can be oxidized in these zones. The depth of the oxidation and thus the height of the vertical step(s) to be formed can be set very precisely and homogeneously using the o- xidation parameters - temperature, time, humidity and oxygen content. After removal of the nitride mask and of the grown oxide, the vertical step/steps are formed at the silicon membrane. The membrane of the SOI wafer is now temporarily bonded onto an auxiliary carrier and the lower part of the SOI wafer is abraded and the oxide then exposed is removed. The mem- brane is bonded to the sacrificial layer 8 of the carrier 1 and is thus connected to it in a firmly bonded manner at the now exposed original lower side. It should be observed in this connection that the vertical step(s) are positioned precisely with re- spect to the electrodes 3, 4 and 5. Subsequent to this, the auxiliary carrier is removed so that the surface of the membrane is aligned with the upwardly facing vertical step(s) . Subsequently, the sacrificial layer 8 is also removed by an isotropic etching process in this example (Fig. 23) .

If the sacrificial layer is SiO₂, the direct bonding can be used between silicon and SiO₂. On the removal of the sacrificial layer 9, the SiO₂ passivation be- tween the electrodes 3, 4 and 5 can simultaneously be removed, whereby electrostatic charge effects can be reduced.

In contrast to the previously explained variants in which the tiltable elements are integrated monolithi- cally onto the substrate 10 using methods of surface micromechanics, in the last-named example, an integration of the tiltable element takes place by heterogeneous integration, i.e. by a transfer process of a prefabricated membrane on a carrier by means of bonding, for the establishment of a firmly bonded connection. A very good homogeneity of the substrate 10 can thus be observed. The zones of the substrate 10 are also made from the same homogeneous material here and the permanent observation of the planarity is thus given.

Claims

1. A micro-optical element having a substrate at which at least one vertical step is formed at an optically effective surface, characterized in that the substrate (10) is formed from one piece from a homogeneous material or from a nanolaminate and at least one vertical step is made at the substrate (10) .

2. An element in accordance with claim 1, characterized in that the vertical step(s) is/are formed with a step height of λ/4 or with an odd number multiple of λ/4 of a preset working wavelength.

3. An element in accordance with either of claims 1 or 2, characterized in that the at least one vertical step is aligned paral- IeI to an axis of rotation of the element.

4. An element in accordance with one of the preceding claims, characterized in that the element can be deflected in a translatory or rotary manner.

5. An element in accordance with one of the preceding claims, characterized in that an optical grid is formed using vertical steps.

6. An element in accordance with one of the preceding claims, characterized in that the optically effective surface is formed with a reflective layer formed on the substrate (10) .

7. An element in accordance with one of the preceding claims, characterized in that the substrate (10) is enclosed at its upper side and lower side by two layers each made of the same material .

8. An element in accordance with claim 7, characterized in that the two layers enclose the substrate (10) symmetrically and/or each have the same layer thickness .

9. An element in accordance with either of claims 7 or 8, characterized in that the layers are made of aluminum.

10. An element in accordance with one of the preceding claims, characterized in that the material (s) forming the substrate (10) have an amorphous or nanocrystalline structures and/or are formed by a nanolaminate .

11. An element in accordance with one of the preced- ing claims, characterized in that the substrate (10) has a constant layer thickness over the entire surface.

12. An element in accordance with one of the preced- ing claims, characterized in that electrodes (3, 4, 5) for a deflection of the element are arranged below the substrate (10) or laterally next to the substrate (10) .

13. An element in accordance with one of the preceding claims, characterized in that the substrate (10) is connected by means of posts (11) and/or by means of spring elements to a carrier (1) and is arranged at a spacing thereto.

14. An element in accordance with one of the preceding claims, characterized in that the carrier (1) is made as a silicon substrate with an integrated CMOS circuit or with an array of fixedly wired externally controllable electrodes .

15. A method for the manufacture of an element in accordance with one of the claims 1 to 14, wherein at least one sacrificial layer (8) is for- med on a carrier (1) ; at least one layer forming the substrate (10) with the at least one vertical step at the optically effective surface is formed above the at least one sacrificial layer (8, 9); or an element (12) forming the substrate (10) is connected to the surface of a sacrificial layer (8) and is structured for the forming of at least one vertical step; subsequently, openings (13) are formed through the substrate (1) through which a removal of the sacrificial layer (8, 9) takes place by etching processes .

16. A method in accordance with claim 15, characterized in that two sacrificial layers (8 and 9) are formed, with the sacrificial layer (9) being selectively structured at the substrate (10) for the formation of the at least one vertical step at the substrate (10) and in so doing being partly removed again before the layer forming the substrate (10) is applied.

17. A method in accordance with claim 15, characterized in that the second sacrificial layer (9) is formed with a layer thickness which corresponds to an odd number multiple of λ/4 of a preset working wave- length λ of the electromagnetic radiation used.

18. A method in accordance with claim 15, characterized in that a first layer is applied to a sacrificial layer (8) for the forming of at least one vertical step; subsequently a locally defined removal of this layer is carried out and then a second layer is applied which forms, together with the first layer, the substrate (10) provided with at least one vertical step.

19. A method in accordance with claim 15, characterized in that a separately manufactured membrane is used as an element (12) forming a substrate (10) , the membrane being etched back regionally for the for- mation of the at least one vertical step, whereupon openings (13) are formed in the element (12), a further auxiliary layer (14) is then formed on the structured surface of the element (12) and then at least one opening (13 ') is formed through the auxiliary layer (14) , the structured element (12) and the sacrificial layer (8) ;

then a coating is applied for the formation of posts (11) on the auxiliary layer (14) and in the opening (s) (13 ') and is removed again except in the regions forming the post(s) (11), whereupon the remaining part of the auxiliary layer (14) and the sacrificial layer (8) below the substrate (10) are removed.

20. A method in accordance with any one of the claims 15 to 19, characterized in that the sacrificial layer(s) (8, 9) are made using amorphous silicon, SiO_2x, photoresist, polyim- ide, spin-on-glass (SOG) , aluminum, Ti_xAl₇, Mo_x. Si_yN_z, Ta_xSi_yN_z, Co_xSi_yN_z, Si_xN_yO_z, GeO_x (where O≤x≤l, O≤y, z<l) and/or molybdenum.

21. A method in accordance with one of the claims 15 to 20, characterized in that the substrate (10) is formed using silicon, a semiconductor material, a metal, a dielectric or a nanolaminate which is formed using the named materials.

22. A method in accordance with claim 17, characterized in that the auxiliary layer (14) is made using amorphous silicon, SiO_2x, photoresist, polyimide, spin-on- glass (SOG) , aluminum, Ti_xAl_x, Mo_xSi₇N₂, Ta_xSi₇N₂,

Co_xSi₇N₂, Si_xN₇O₂, GeO_x (where O≤x≤l, O≤y, z<l) and/or molybdenum.

23. A method in accordance with one of the claims 15 to 22, characterized in that a passivation layer (6) is applied to the car- rier (1) having electrodes (3, 4, 5), said passivation layer electrically insulating the electrodes (3, 4, 5) and then being removed again until the exposing of the electrodes (3, 4, 5) .

24. A method in accordance with one of the claims 14 to 22, characterized in that stoppers (7) of a dielectric or high-ohm material are applied to electrodes (3, 4, 5) .

25. Use of an element in accordance with one of the claims 1 to 14 for the direct exposure of wafers, the manufacture of masks for the wafer exposure, exposure of circuit boards, the projection of two-dimensional or three-dimensional patterns or images, the modification and correc- tion of imaging properties of optical systems or applications in adaptive optics.