WO2008060184A1 - Hétérostructure semi-conductrice d'un transistor à effet de champ - Google Patents

Hétérostructure semi-conductrice d'un transistor à effet de champ Download PDF

Info

Publication number
WO2008060184A1
WO2008060184A1 PCT/RU2007/000395 RU2007000395W WO2008060184A1 WO 2008060184 A1 WO2008060184 A1 WO 2008060184A1 RU 2007000395 W RU2007000395 W RU 2007000395W WO 2008060184 A1 WO2008060184 A1 WO 2008060184A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
heterostructure
field
channel
template
Prior art date
Application number
PCT/RU2007/000395
Other languages
English (en)
Russian (ru)
Inventor
Alexej Nikolaevich Alexeev
Yury Vasilievich Pogorelsky
Igor Albertovich Sokolov
Dmitry Mikhailovich Krasovitsky
Viktor Petrovich Chaly
Alexej Petrovich Shkurko
Original Assignee
'svetlana-Rost' Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 'svetlana-Rost' Limited filed Critical 'svetlana-Rost' Limited
Priority to DE112007002782T priority Critical patent/DE112007002782T5/de
Publication of WO2008060184A1 publication Critical patent/WO2008060184A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the invention relates to heterostructures of semiconductor devices, mainly field-effect transistors.
  • microwave field-effect transistors the power of which is several times greater than the power of such transistors, made on the basis of traditional materials
  • nitride-based transistors have unique thermal stability and can operate in continuous operation at a temperature of 300-50O 0 C 5 which was completely unavailable on traditional devices.
  • An AlN nucleation layer is placed on the sapphire substrate, then a GaN buffer layer and an AlGaN barrier layer.
  • This heterostructure requires compensating doping of the buffer layer with magnesium (or carbon, iron, etc.) to reduce current leakage.
  • magnesium or carbon, iron, etc.
  • cracking of the barrier layer occurs even at relatively low tensile stresses, since the crystal lattice constant of sapphire differs significantly (by 17%) from the crystal lattice constant of GaN.
  • the presence of a very thin AlN nucleation layer between the substrate and the GaN layer practically does not affect the aforementioned mismatch.
  • heterostructures on a sapphire substrate are known, in particular, a heterostructure of a field effect transistor, RU 2222845 Cl; the heterostructure consistently includes a substrate, an insulating layer made of Al y Ga 1-y N, a channel layer and a barrier layer made of Al z Gai -z N, the channel layer is made of Al x Ga] _ X N, where 0.12>x> 0.03, while on the border of the channel and insulating layers l ⁇ y ⁇ x + 0.1, on the border of the channel and barrier layers l>z> x + 0, l, and the thickness of the channel layer is in the range from 3 to 20 nm, with x, y, z being the molar fractions of Al in the composition of the AlGaN compound.
  • This heterostructure is characterized by the disadvantages of
  • GaN is about 3%, which eliminates a number of drawbacks of the analogues described above, reduces the density of intrinsic defects, and virtually eliminates cracking of the barrier layer.
  • a semiconductor heterostructure of a field-effect transistor including a single-crystal substrate of AlN, an epitaxial template layer of AlN, a channel layer of GaN, and a barrier layer of Al x Ga 1 _ X N, see X.
  • Hu atal Trisistors Arsel Letsters, heterofigured filed a on sipgl-crustal bulk AlN "vol. 82, N8, 2003, R.P. 1299-1301, AMERICAP IPSITO OF PHYSICS, USA (a copy of the link is attached).
  • the disadvantage of the prototype is the following circumstance.
  • the GaN channel layer is grown directly on the AlN template layer in the first stage of this process, at a small channel layer thickness, significant compressive stresses of the channel layer arise.
  • the channel layer relaxes with the formation of a large number of defects, which is unacceptable.
  • Limiting the thickness of the GaN layer significantly limits the conductivity of the channel layer and, accordingly, limits the operating currents and power of the device. Disclosure of invention
  • the objective of the present invention is to increase the conductivity of the channel layer of a semiconductor heterostructure and, therefore, increase the operating currents and power of field-effect transistors.
  • this problem is solved due to the fact that in a semiconductor heterostructure of a field-effect transistor including a single crystal AlN substrate, an AlN template layer, a GaN channel layer and an Al x Ga 1 -X N barrier layer, are located one above the other between the template and channel layers, accordingly, the transition layer is Al y Ga ⁇ y N, the buffer layer is Al z Gai -z N, the value of y at the boundary with the template layer is 1, and at the boundary with the buffer layer it is equal to the value z of the buffer layer, with 0.3 ⁇ x ⁇ 0 5, a 0, l ⁇ z ⁇ 0.5;
  • the buffer layer at the interface with the channel layer can be doped with Si to a depth of 50–15 ⁇ A.
  • the semiconductor heterostructure of the field-effect transistor created in accordance with the claimed features makes it possible to grow a channel layer of a given thickness in accordance with the required operating currents and the installed power of the device; this is due to the fact that high conductivity of the channel layer of GaN is ensured due to the prevention of the formation of reducing mobility electron defects with an increase in its thickness above a critical value.
  • the presence of doped Si in the upper sublayer of the buffer layer provides an additional increase in the conductivity of the channel layer by increasing the concentration of electrons in it.
  • the single crystal substrate 1 is made of aluminum nitride and has a thickness of 500 ⁇ m, crystallographic orientation (0001). On the substrate 1 is a template layer 2
  • AlN thickness in a specific example, 2100 A.
  • transition layer 3 Al y Gai -y N with a thickness of 1400 A.
  • the value of y varies in thickness of the transition layer from 1 at the border with the template layer to the z value of the buffer layer 4.
  • the z value is constantly the entire buffer layer and is 0, l ⁇ z ⁇ 0.5.
  • the thickness of the buffer layer 4 in this example is 4200 A, the value of z is 0.3.
  • the channel layer 5 GaN has a thickness of 1400 A.
  • the buffer layer 4 at the interface with the channel layer is doped with Si to a depth of 100 A with a concentration of l xl ⁇ 19 cm "3 .
  • the first embodiment corresponds to claim 1 of the claims
  • the buffer layer at the interface with the channel layer is Si doped.
  • the characteristics of both variants of the heterostructures are shown in table 1.
  • Tests showed a significant improvement in the parameters of heterostructures in comparison with the prototype.
  • the resulting heterostructures are the basis of high power field effect transistors.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

L'invention concerne des hétérostructures d'instruments semi-conducteurs et principalement des transistors à effet de champ. Elle vise principalement à augmenter la conductivité de la couche canal d'une hétérostructure semi-conductrice et, partant, à augmenter les courants effectifs et la puissance des transistors à effet de champ. Selon l'invention, dans l'hétérostructure semi-conductrice d'un transistor à effet de champ, on a prévue un substrat monocristallin (1) en AlN, une couche de gabarit (2) en AlN, une couche canal (5) en GaN et une couche barrière (6) en AlxGa1-xN. Entre la couche de gabarit (2) et les couches canal (5) on a déposé l'une sur l'autre, couche par couche, une couche de passage (3) AlyGa1-yN et une couche tampont (4) AlzGa1-zN. La valeur 'y' à la frontière avec la couche de gabarit (2) est égale à '1', et à la frontière avec la couche tampon (4) elle est égale à 'z' de la couche tampon (4), à condition que 0,3≤x≤0,5 and 0,1≤z≤0,5. Dans l'hétérostructure semi-conductrice la couche tampon (4) à la frontière de la couche canal (5) peut être dopée par Si à une profondeur de 50 à 150 Å.
PCT/RU2007/000395 2006-11-14 2007-07-12 Hétérostructure semi-conductrice d'un transistor à effet de champ WO2008060184A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE112007002782T DE112007002782T5 (de) 2006-11-14 2007-07-12 Halbleiterheterostruktur für einen Feldeffekttransistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
RU2006140699/28A RU2316076C1 (ru) 2006-11-14 2006-11-14 Полупроводниковая гетероструктура полевого транзистора
RU2006140699 2006-11-14

Publications (1)

Publication Number Publication Date
WO2008060184A1 true WO2008060184A1 (fr) 2008-05-22

Family

ID=39110139

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/RU2007/000395 WO2008060184A1 (fr) 2006-11-14 2007-07-12 Hétérostructure semi-conductrice d'un transistor à effet de champ

Country Status (3)

Country Link
DE (1) DE112007002782T5 (fr)
RU (1) RU2316076C1 (fr)
WO (1) WO2008060184A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2517788C1 (ru) * 2012-12-25 2014-05-27 Федеральное Государственное Унитарное Предприятие "Научно-Производственное Предприятие "Пульсар" Биполярный транзистор свч
RU2534002C1 (ru) * 2013-06-18 2014-11-27 федеральное государственное автономное образовательное учреждение высшего профессионального образования "Национальный исследовательский ядерный университет МИФИ" (НИЯУ МИФИ) Высоковольтный нитрид-галлиевый транзистор с высокой подвижностью электронов
CN110501773B (zh) * 2019-08-29 2020-06-02 南京大学 应用于日盲光电探测器的AlN/AlGaN多周期一维光子晶体滤波器及日盲光电探测器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2222845C1 (ru) * 2003-04-01 2004-01-27 Закрытое акционерное общество "Научное и технологическое оборудование" Полевой транзистор
US20050133816A1 (en) * 2003-12-19 2005-06-23 Zhaoyang Fan III-nitride quantum-well field effect transistors
US20060049426A1 (en) * 2004-09-08 2006-03-09 Samsung Electro-Mechanics Co., Ltd. Nitride based hetero-junction field effect transistor
US7030428B2 (en) * 2001-12-03 2006-04-18 Cree, Inc. Strain balanced nitride heterojunction transistors

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7030428B2 (en) * 2001-12-03 2006-04-18 Cree, Inc. Strain balanced nitride heterojunction transistors
RU2222845C1 (ru) * 2003-04-01 2004-01-27 Закрытое акционерное общество "Научное и технологическое оборудование" Полевой транзистор
US20050133816A1 (en) * 2003-12-19 2005-06-23 Zhaoyang Fan III-nitride quantum-well field effect transistors
US20060049426A1 (en) * 2004-09-08 2006-03-09 Samsung Electro-Mechanics Co., Ltd. Nitride based hetero-junction field effect transistor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HU X. ET AL.: "AlGaN/GaN heterostructure field-effect transistors on single-crystal bulk AlN", vol. 82, no. 8, 2003, pages 1299 - 1301, XP012034877, DOI: doi:10.1063/1.1555282 *

Also Published As

Publication number Publication date
RU2316076C1 (ru) 2008-01-27
DE112007002782T5 (de) 2009-09-10

Similar Documents

Publication Publication Date Title
JP5524235B2 (ja) 半導体素子用エピタキシャル基板および半導体素子用エピタキシャル基板の製造方法
EP3067921B1 (fr) Procédé de production d'un substrat épitaxial pour un élément semi-conducteur
US6781164B2 (en) Semiconductor element
JP5456783B2 (ja) 半導体素子用エピタキシャル基板、半導体素子用エピタキシャル基板の製造方法、および半導体素子
US8653561B2 (en) III-nitride semiconductor electronic device, and method of fabricating III-nitride semiconductor electronic device
US7626217B2 (en) Composite substrates of conductive and insulating or semi-insulating group III-nitrides for group III-nitride devices
US9419125B1 (en) Doped barrier layers in epitaxial group III nitrides
JP6731584B2 (ja) 窒化物半導体装置および窒化物半導体基板
EP1886352A2 (fr) Structures en nitrure de gallium comprenant des substrats et procedes associes
WO2009119357A1 (fr) Substrat épitaxial pour élément semiconducteur, élément semiconducteur, et procédé de production de substrat épitaxial pour élément semiconducteur
JP2005085852A (ja) 半導体電子デバイス
CN109564855B (zh) 使用离子注入的高电阻率氮化物缓冲层的半导体材料生长
JP2009231561A (ja) 窒化物半導体結晶薄膜およびその作製方法、半導体装置およびその製造方法
JP2008140812A (ja) ＧａＮ系高電子移動度電界効果トランジスタ
US8994032B2 (en) III-N material grown on ErAIN buffer on Si substrate
IL293444B1 (en) Gallium nitride transistors with high electron mobility with reduced current collapse and improved power addition efficiency
Zhang et al. N-polar AlN nucleation layers grown by hot-wall MOCVD on SiC: Effects of substrate orientation on the polarity, surface morphology and crystal quality
US20220157980A1 (en) Nitride semiconductor device
US20110049573A1 (en) Group iii nitride semiconductor wafer and group iii nitride semiconductor device
JP2006114652A (ja) 半導体エピタキシャルウェハ及び電界効果トランジスタ
WO2008060184A1 (fr) Hétérostructure semi-conductrice d'un transistor à effet de champ
JP2009246307A (ja) 半導体装置及びその製造方法
JP2006196557A (ja) 半導体エピタキシャルウェハ及び電界効果トランジスタ
di Forte Poisson et al. MOCVD growth of group III nitrides for high power, high frequency applications
Xie et al. AlxIn1-xN/GaN heterostructure field effect transistors

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07794092

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 1120070027827

Country of ref document: DE

RET De translation (de og part 6b)

Ref document number: 112007002782

Country of ref document: DE

Date of ref document: 20090910

Kind code of ref document: P

122 Ep: pct application non-entry in european phase

Ref document number: 07794092

Country of ref document: EP

Kind code of ref document: A1

REG Reference to national code

Ref country code: DE

Ref legal event code: 8607