WO2008045779A2 - Préforme de feuille de fixation de puce en or - Google Patents

Préforme de feuille de fixation de puce en or Download PDF

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Publication number
WO2008045779A2
WO2008045779A2 PCT/US2007/080552 US2007080552W WO2008045779A2 WO 2008045779 A2 WO2008045779 A2 WO 2008045779A2 US 2007080552 W US2007080552 W US 2007080552W WO 2008045779 A2 WO2008045779 A2 WO 2008045779A2
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WO
WIPO (PCT)
Prior art keywords
die bond
die
package
gold
preform
Prior art date
Application number
PCT/US2007/080552
Other languages
English (en)
Other versions
WO2008045779A3 (fr
Inventor
David Jech
Kothandapani Ramesh
James W. Snyder
Original Assignee
Williams Advanced Materials, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Williams Advanced Materials, Inc. filed Critical Williams Advanced Materials, Inc.
Publication of WO2008045779A2 publication Critical patent/WO2008045779A2/fr
Publication of WO2008045779A3 publication Critical patent/WO2008045779A3/fr

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Classifications

    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C27/00—Alloys based on rhenium or a refractory metal not mentioned in groups C22C14/00 or C22C16/00
    • C22C27/04—Alloys based on tungsten or molybdenum
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C5/00—Alloys based on noble metals
    • C22C5/02—Alloys based on gold
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • This invention relates to the die bonding of semiconductor chips to ceramic or metals, and more particularly, to die bonding of semiconductor chips to semiconductor package using a gold die bond sheet preform.
  • Die bonding of semiconductor chips to ceramic typically involves metalizing the semiconductor package with gold alloy and bonding of the die to the substrate.
  • metalizing the semiconductor package with gold alloy and bonding of the die to the substrate.
  • power devices for example, that require a high quality die bond to dissipate heat from the package, and, in some cases, provide a low impedance interface between the bottom of the die and the die bond area.
  • the amount of gold in the gold layers plated onto the semiconductor package is a critical factor in the quality of the die bond.
  • the amount of gold plated onto the semiconductor package is a major factor in the cost of the package.
  • the thickness of the gold layer on the package must be enough to provide a secure wire bond surface for the wire bonds from the die to the leads and sufficient gold for the die attach process.
  • variations in the amount of gold on the bottom of the die from one manufacturer to another, and to different die types by the same manufacturer when the die is manufactured affects the amount of gold under the die [0004] Therefore, it can be appreciated that a ceramic package that requires less gold than conventional packages is highly desirable.
  • the invention comprises, in one form thereof, a method of forming a die bond site on a semiconductor package by forming a die bond sheet preform, placing the die bond sheet preform on a die bond area of the semiconductor package, and tack bonding the die bond sheet preform to the semiconductor package.
  • An advantage of the present invention is that the amount of gold normally plated onto the ceramic package can be reduced.
  • FIG. 1 is a top view of an example ceramic package with a preform according to the present invention
  • FIG. 2 is a combination cross section of the ceramic package of FIG. 1 and an electrical schematic of a method of tack welding the preform to the ceramic package;
  • FIG. 3 is a top view of the ceramic package of FIG. 1 with a semiconductor chip or die bonded to the ceramic package;
  • FIG. 4A is a top view of a non-ceramic package with a preform according to the present invention.
  • FIG. 4B is a sectional side view taken along line 4B-4B of the package shown in FIG. 4A;
  • FIG. 5 is a combination cross section taken along line 5-5 of the non-ceramic package of FIG. 4 A and an electrical schematic of a method of tack welding preform to the package;
  • FIGs. 6A and 6B top views of die bond strips showing alternative tack welding patterns.
  • one embodiment 10 of the present invention includes a dual chip ceramic package 12 with rectangular gold, or a gold alloy such as AuSn and AuGe, die bond sheet preforms 14 attached to die bond areas 16 by tack welds 18.
  • the package 12 in this embodiment has a copper-tungsten base with BeO ceramic regions formed thereon in a conventional manner. Separate conductive regions are formed conventionally by putting down patterned molymaganeze metallization on the ceramic and plating the ceramic package 12 with layers of nickel and gold.
  • the lead frame has a horizontal member 20 which spans the width of the package and is electrically connected to conductive regions 22 and 24 on the ceramic.
  • Two upper leads 26 and 28 are electrically connected to conductive regions 30 and 32 on the ceramic, respectively.
  • the conductive regions 30 and 32 include the die bond regions 16.
  • Two lower leads 34 and 36 are electrically connected to conductive regions 38 and 40, respectively.
  • Conductive U-shaped bridges 42 span the upper leads 26 and 28 to help reduce any voltage variation across the conductive regions 30 and 32
  • the thickness of the plated gold plus the thickness of the gold die bond sheet preform must be enough for a reliable die bond of a semiconductor die to the package 12. Since the plated gold covers the entire package while the gold or gold alloy die bond sheet preform is generally only slightly larger than the bottom of the die, the amount of gold on the package with the gold die bond sheet preform in place will depend on the relative ratios of the thicknesses of the plated gold and the gold die bond sheet preform 14. Were this thickness ratio the only criteria for selecting the thicknesses of the plated gold and the gold die bond sheet preform 14, the plated gold would be at minimal thickness. In one embodiment the plated gold has a minimum thickness of 30 ⁇ inches (.762 ⁇ m).
  • the package prevents the package from oxidizing during the die attachment operation, and also provides a suitable surface for reliable wire bonds.
  • the total gold thickness on the package required for a reliable die bond is about 100 to 250 ⁇ inches (2.54 to 6.35 ⁇ m).
  • a plated gold thickness of about 60 ⁇ inches (1.52 ⁇ m) is used with a gold die bond sheet preform of about 40 to 190 ⁇ inches (1.02 to 4.83 ⁇ m).
  • the plated gold on the package would be 250 ⁇ inches (6.35 ⁇ m) thick resulting in much more total gold on the package than a combination of the package 12 and the gold die bond sheet preform 14.
  • the tack weld needs to be strong enough to keep the gold die bond sheet preform 14 attached to the package 12 until a die is attached to the package. When the die is attached, the plated gold on the package, the gold die bond sheet preform and the gold on the bottom of the die flow together, and the tack weld is no longer present.
  • the tack weld 18 is formed using a tack welder having a welding electrode 46, an electrical generator 48, and a flat contacts 50.
  • the tack weld 18 may be a spot weld or one of other types of tack welds.
  • the flat contact 50 is pressed onto the appropriate lead 26 or 28 and the pointed electrode 46 is pressed onto the corresponding preform 14 at the tack weld position 18 as shown in FIG. 2.
  • the welding electrode in one embodiment is 80% tungsten and 20% copper, a RWMA class 12 alloy.
  • the tack welder electrical generator 48 may provide a DC current and voltage of generally between 5 and 13 watt- seconds depending on the thickness of the gold die bond sheet preform.
  • FIG. 3 shows the dual chip ceramic package 12 after semiconductor chips 52 and 54 have been die bonded onto the package 12.
  • FIG. 4A is a top view of a non-ceramic package 60 with a preform 62 according to the present invention.
  • the non-ceramic package 60 has mounting holes 64 and grooves 66 formed in a copper tungsten frame 68.
  • a copper plate 68 with an opening 70 is brazed onto a copper tungsten frame 72, and then the lead frame receives a thin layer of gold plating.
  • the perform 62 is placed in the opening 70 and tack welded with three tack welds 74 in the embodiment shown in FIG. 4A.
  • the perform 62 can be of any of the materials described above with respect to performs 14.
  • FIG. 4A is a top view of a non-ceramic package 60 with a preform 62 according to the present invention.
  • the non-ceramic package 60 has mounting holes 64 and grooves 66 formed in a copper tungsten frame 68.
  • a copper plate 68 with an opening 70 is brazed onto a copper tungsten frame 72,
  • FIG. 4B is a sectional side view of the package 60 shown in FIG. 4 A.
  • FIG. 5 is a combination cross section of the non-ceramic package 60 of FIG. 4 A and an electrical schematic of a method of tack welding the preform to the package 60.
  • the welding equipment has three electrodes 46 (described above), an electrical generator 80, and the flat contacts 50.
  • the electrical generator 80 is the electrical generator 48 of FIG. 2 modified to provide three tack welds instead of a single tack weld.
  • FIGs. 6A and 6B top views of preforms 86 and 88 showing two alternative tack welding patterns. In FIG. 6A two tack welds are used, and in FIG.
  • the tack welds are staggered rather than in a straight line as shown in FIG. 4A.
  • the gold die bond sheet preform shown in the drawings is rectangular, the preform will be generally shaped to the contour of the bottom of the die.
  • the total amount of gold used on the package, including the gold die bond sheet preform is significantly reduced. Also, for accommodating chips which have different thickness of gold on the bottom of the chips, the same basic ceramic package can be used, and the thickness of the gold die bond sheet preform can be adjusted for a particular die type.
  • this variability of the gold bond die sheet preform means that the package for a particular die can be set up near the end of the manufacturing cycle thus reducing the time needed to package the first samples of a new die type. Moreover, since the cost of manufacturing a custom thickness gold die bond sheet preform is much less than manufacturing a package with a custom thickness of gold plating, the cost of each of the packages for a new die type is reduced, which can become significant for small package orders by the semiconductor manufacturer.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

L'invention concerne la réduction de la quantité d'or nécessaire pour plaquer un boîtier électronique destiné à un boîtier de semi-conducteur en réduisant l'épaisseur de la plaque d'or sur le substrat de boîtier, et en utilisant une préforme de feuille de fixation de puce en or. La préforme, seulement légèrement plus grande qu'une puce de semi-conductrice devant être fixée sur le boîtier, est placée à l'endroit de fixation de puce puis soudée sur le boîtier. L'épaisseur du placage d'or sur le boîtier et la préforme fournissent l'épaisseur appropriée de l'or pour une fixation sûre de la puce au boîtier.
PCT/US2007/080552 2006-10-06 2007-10-05 Préforme de feuille de fixation de puce en or WO2008045779A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US85001006P 2006-10-06 2006-10-06
US60/850,010 2006-10-06

Publications (2)

Publication Number Publication Date
WO2008045779A2 true WO2008045779A2 (fr) 2008-04-17
WO2008045779A3 WO2008045779A3 (fr) 2008-12-04

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014150643A1 (fr) * 2013-03-15 2014-09-25 Materion Corporation Préforme de feuille de fixation de puce en or soudée par points à une aire de soudure semiconductrice sur un boîtier de semi-conducteur et procédé de production approprié

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3495322A (en) * 1967-07-20 1970-02-17 Motorola Inc Process for bonding a silicon wafer to a ceramic substrate
US3660632A (en) * 1970-06-17 1972-05-02 Us Navy Method for bonding silicon chips to a cold substrate
US3728090A (en) * 1970-06-30 1973-04-17 Texas Instruments Inc Semiconductor bonding alloy
US4872047A (en) * 1986-11-07 1989-10-03 Olin Corporation Semiconductor die attach system
US5037778A (en) * 1989-05-12 1991-08-06 Intel Corporation Die attach using gold ribbon with gold/silicon eutectic alloy cladding
US5667884A (en) * 1993-04-12 1997-09-16 Bolger; Justin C. Area bonding conductive adhesive preforms

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3495322A (en) * 1967-07-20 1970-02-17 Motorola Inc Process for bonding a silicon wafer to a ceramic substrate
US3660632A (en) * 1970-06-17 1972-05-02 Us Navy Method for bonding silicon chips to a cold substrate
US3728090A (en) * 1970-06-30 1973-04-17 Texas Instruments Inc Semiconductor bonding alloy
US4872047A (en) * 1986-11-07 1989-10-03 Olin Corporation Semiconductor die attach system
US5037778A (en) * 1989-05-12 1991-08-06 Intel Corporation Die attach using gold ribbon with gold/silicon eutectic alloy cladding
US5667884A (en) * 1993-04-12 1997-09-16 Bolger; Justin C. Area bonding conductive adhesive preforms

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014150643A1 (fr) * 2013-03-15 2014-09-25 Materion Corporation Préforme de feuille de fixation de puce en or soudée par points à une aire de soudure semiconductrice sur un boîtier de semi-conducteur et procédé de production approprié
US8975176B2 (en) 2013-03-15 2015-03-10 Materion Corporation Gold die bond sheet preform
CN105122436A (zh) * 2013-03-15 2015-12-02 美题隆公司 点焊至在半导体封装件上的半导体接合区的含金的晶片接合片状预制体和相应的制造方法

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