WO2008041063A1 - Circuit de polarisation et procédé de polarisation d'un transistor dans un amplificateur de classe c - Google Patents

Circuit de polarisation et procédé de polarisation d'un transistor dans un amplificateur de classe c Download PDF

Info

Publication number
WO2008041063A1
WO2008041063A1 PCT/IB2006/054678 IB2006054678W WO2008041063A1 WO 2008041063 A1 WO2008041063 A1 WO 2008041063A1 IB 2006054678 W IB2006054678 W IB 2006054678W WO 2008041063 A1 WO2008041063 A1 WO 2008041063A1
Authority
WO
WIPO (PCT)
Prior art keywords
class
amplifier
transistor
bias circuit
voltage
Prior art date
Application number
PCT/IB2006/054678
Other languages
English (en)
Inventor
Jean Jacques Bouny
Original Assignee
Freescale Semiconductor, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor, Inc. filed Critical Freescale Semiconductor, Inc.
Priority to PCT/IB2006/054678 priority Critical patent/WO2008041063A1/fr
Publication of WO2008041063A1 publication Critical patent/WO2008041063A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0261—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/306—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in junction-FET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/108—A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/18—Indexing scheme relating to amplifiers the bias of the gate of a FET being controlled by a control signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the present invention relates to a bias circuit and method for biasing a transistor in a Class C amplifier.
  • a Doherty amplifier consists of two amplifiers, namely a main (or carrier) amplifier and an auxiliary (or peaking amplifier) connected in parallel with their outputs joined by a quarter-wave transmission line.
  • the main amplifier is typically a Class B or Class AB type linear power amplifier and the auxiliary amplifier is typically a Class C type non-linear power amplifier.
  • the direct current (DC), or quiescent current, biasing point is a critical design parameter which has significant effects on the characteristics and performance (e.g., linearity, signal distortion, power efficiency) of the amplifier.
  • the optimal DC biasing point of a transistor in an amplifier depends on the application of the amplifier and the characteristics of the transistor, which are affected by environmental and other factors such as temperature variations and process variations.
  • the bias circuits for the main (class B or AB) amplifiers in a Doherty amplifier are set by measuring the quiescent current of the amplifiers when no RF signal is applied. This process is relatively easy to perform in a production line. However, in class C amplifiers, no quiescent current is consumed in the absence of an RF signal. Thus, the quiescent conditions of such amplifiers are not easily measurable. This problem is further complicated by part-to-part variations between the threshold voltages of transistors in the amplifiers.
  • a class C bias circuit like a class A or class AB bias circuit, should be capable of delivering a correct bias level with thermal compensation to maintain the bias point during the operation of the amplifier.
  • the class C bias circuit should also have a low impedance (ideally zero Ohms), to prevent parasitic modulation appearing at the input of the amplifier's transistor, since otherwise, the parasitic modulation would generate undesirable memory effects and non-linearity.
  • the bias circuit should be easy to tune.
  • the bias circuit should compensate for part-to-part variation in the threshold voltages of an amplifier's transistors, so that adjustment of the bias circuit is unnecessary.
  • the bias circuit should also have low power consumption to prevent any degradation in the overall efficiency of the amplifier; and to ensure that the bias circuit can be supplied with power by small reference voltages or directly from low cost DACs (digital to analog converters).
  • Figures 1 (a) and 1 (b) are circuit diagrams of two bias circuits for a transistor in a class C amplifier, wherein the circuits comprise adjustable analogue circuits to provide thermal compensation;
  • Figure 2 is a circuit diagram of another bias circuit for the transistor in the class C amplifier;
  • Figure 3 is a circuit diagram of another bias circuit for the transistor in the class C amplifier, wherein the circuit allows for the integration of a reference and a buffer; and
  • Figure 4 is a circuit diagram of an integrated bias circuit for a transistor in a class AB amplifier;
  • Figure 5 is a circuit diagram of a bias circuit for the transistor in the class C amplifier in accordance with a first embodiment;
  • Figure 6 is a circuit diagram of a bias circuit for the transistor in the class C amplifier in accordance with a second embodiment, wherein a current source in the first embodiment shown in Figure 5, is replaced by a resistor and a voltage source; and
  • Figure 7 is a circuit diagram of a single stage transistor biased using the bias circuit of the first or second embodiment.
  • class C amplifiers were used to amplify constant envelope signals, wherein the biasing of the amplifiers' transistors was not important.
  • a bias circuit for a class C amplifier was set by connecting the gate (or the base) of the amplifier's transistor to ground, so that tuning was unnecessary.
  • the biasing of its class C (peaking) amplifier is critical to the overall linearity and efficiency of the Doherty amplifier.
  • a commonly used procedure for biasing a transistor in a Class C amplifier comprises the steps of: applying a voltage on the gate or the base of the transistor; increasing the voltage to obtain a class AB quiescent current; measuring the applied voltage (which is transistor dependent); subtracting from the applied voltage a fixed value (Vdelta) to achieve the desired class C bias point; and applying this voltage to the transistor.
  • the bias circuit 16 comprises an AB reference module 18, which generates a reference voltage Vref (by putting a fixed current lref into a reference transistor 20) corresponding with a bias voltage for a Class AB amplifier.
  • the bias circuit 16 further comprises a voltage source 21 , which generates a fixed voltage Vdelta.
  • the bias circuit further 16 comprises a buffer 22 connected between the AB reference module 18 and the transistor 24 to be biased.
  • the buffer 22 ensures a fast response rate from the transistor 24.
  • the buffer 22 further ensures low output impedance from the bias circuit 16.
  • the buffer 22 also comprises an operational amplifier 26, which subtracts the fixed voltage Vdelta from the reference voltage Vref, to generate a correct bias level Vbias for the transistor 24. If integrated onto the same die as the transistor 24, the bias circuit 16 compensates for part-to-part and thermal variation. With this approach, the process of tuning is reduced to setting a fixed voltage proportional to the voltage Vdelta. This voltage being known, no more adjustment of the bias circuit 16 is required, which solves most of the problems encountered during manufacturing.
  • the bias circuit 16 could be implemented by integrating the AB reference module 18 with the buffer 22.
  • the main limitation on this approach is the speed and output impedance of the operational amplifier 26.
  • the buffer 26 could be simplified by providing a high decoupling capacitor (not shown) between the bias circuit 16 and the transistor 24. In this case, low impedance at modulation frequencies is provided by the capacitor (not shown).
  • a derivative of this solution is described in US Patent number US6917246.
  • This system can provide most of the required performance of a bias circuit if it is implemented externally to the transistor to be biased. However, this system is not suitable for integration with a high power transistor because of problems with the design of the buffer (i.e. high consumption, low speed or need for high capacitors).
  • FIG 3 shows a Doherty amplifier bias circuit 27 comprising a class C bias circuit 28 and a current mirror circuit 30.
  • the class C bias circuit 28 comprises a scaling/level shifting circuit 32 and a voltage buffer 34.
  • the current mirror circuit 30 comprises a reference transistor 36, a voltage follower 38 and a current source 40.
  • the collector of the reference transistor 36 is connected to the current source 40 at the node 42.
  • the voltage follower 38 comprises a transistor whose drain is connected to a DC power supply 44 (Vdd).
  • the source of the transistor is connected to a node 46 and the gate of the transistor is connected to the current source 40 and the reference transistor 36 through the node 42.
  • the transistor is configured so that the output at node 46 tracks the voltage at node 42. This output at node 46 is effectively a Class AB amplifier bias voltage (i.e. a reference voltage).
  • the reference voltage is input to the class C bias circuit 28 at the scaling/level shifting circuit 32, which subtracts a desired voltage Vdelta from the reference voltage.
  • the output voltage from the scaling/level shifting circuit 32 is input to the voltage buffer 30 to ensure appropriate output impedance from the bias circuit 27. Compensation for thermal and part-to-part variation is provided by integrating the reference transistor 36 and an associated current source 40 on the same die as a transistor 50 to be biased. However, as before, the performance of the buffer 34 limits the practical implementation of the bias circuit 27.
  • French Patent Application FR2006/050657 describes an integrated bias circuit for a transistor in a class AB amplifier.
  • a transistor Tl is used as a reference and a transistor T2 is used as a buffer.
  • the high gain loop provided by this simple topology allows low impedance, high speed and low power consumption to be achieved within a compact design.
  • a first embodiment of the present bias circuit for a transistor in a class C amplifier employs a simple integrated topology which provides good part to part and thermal compensation and has low power consumption, high speed and low impedance.
  • the first embodiment allows the integration of bias circuits with high- power transistors at a low manufacturing cost for both the transistor manufacturer and the amplifier manufacturer (since no adjustment is necessary), whilst ensuring the accurate setting of the bias voltage for the transistor.
  • a bias circuit 54 in accordance with the first embodiment comprises two small transistors T1 and T2 being scaled versions of a transistor 56 to be biased.
  • the transistors T1 and T2 are provided in a looped arrangement, similar to that shown in Figure 4, wherein the drain of transistor T1 is connected to a voltage source 58 through a resistor R2.
  • the voltage source 58 is connected to the drain of transistor T2 and the gate of transistor T2 is connected to resistor R2 at node 60.
  • the gate of transistor T1 is connected to the source of transistor T2 at node 62 (which forms the output from the bias circuit 54).
  • transistor T1 acts as a reference, which has its bias point fixed by the resistor R2 and the voltage source 58.
  • Transistor T2 acts as a voltage buffer for transistor T1 and provides current to the transistor 56 when necessary. For example, since the transistor 56 effectively behaves like a capacitor, the bias circuit 54 would have to charge the transistor 56 in order to increase the bias voltage.
  • the looped arrangement of T1 and T2 ensures that the voltage on T1 controls the output voltage at node 62. In effect the voltage output from the gate of T1 is the class AB amplifier bias voltage (i.e. a reference voltage Vref).
  • the looped arrangement of T1 and T2 is further designed so that the output impedance of the bias circuit 54 is divided by the gain of the loop.
  • a resistor R1 is inserted between node 62 and the gate of the reference transistor T1.
  • a current source 64 is connected (at a node 66) between the resistor R1 and the gate of the reference transistor T1.
  • the injection of a current (from the current source 64) into R1 results in a voltage shift at node 62 (i.e. the output of the bias circuit 54).
  • the voltage (Vbias) at node 62 is shifted compared to the reference voltage on the gate of T1 , wherein this reference voltage corresponds to the class AB bias voltage.
  • the injected current does not affect the functionality of the T1 , T2 looped arrangement for generating the class AB bias voltage.
  • the reference transistor Tl When the bias circuit is integrated on the same die as the RF transistor to be biased, the reference transistor Tl provides good part-to-part compensation. If the current in the reference transistor T1 varies because of inaccuracies (from process variations) in the integrated resistor R2, the gate voltage of T1 will vary. Thus, the output voltage from the bias circuit (Vbias) will vary. However, the variation in Vbias will be very small compared to the nominal value of Vdelta. Furthermore, since the transistor T1 is integrated on the same die as the RF transistor to be biased, T1 will be at the same temperature as the RF transistor to be biased. Thus, the transistor T1 will provide almost perfect compensation for temperature variations. This thermal compensation is very fast compared to that provided by an external thermal sensor.
  • the bias circuit of the first and second embodiments reduces memory effects and improves the "linearizability" of a class C amplifier. Further, since the output impedance of the bias circuit is divided by the total loop gain, very low impedances can be achieved even with small transistors. Further, the frequency cut-off of the first and second embodiments is high even when loaded in parallel with a high capacitance capacitor. For example, 100MHz can be achieved with two transistors (T 1 and T2) being scaled down 200 times compared with the transistor to be biased.
  • power at the output of a single stage RF transistor biased according to the first embodiment can be up to 100W at 2.0GHz for a single die, and consumption at full power can be in the range of 7.0A.
  • total consumption of the bias circuit is around 1.5mA and could be further reduced. This allows supply through small low cost voltage reference or through small digital to analog Converters, and does not impact the overall efficiency of the amplifier.
  • Having an integrated bias (whose tuning is note only dependent on the external voltage Vgg) allows several dies to be combined in parallel to further increase the power without suffering from die pairing problems (arising from different threshold voltages).
  • the bias circuit Since the bias circuit is very small, its integration on the same die as the transistor to be biased, does not require any increase in die size (since the bias circuit can be put in a dead zone of the RF die). Thus, the integration of the bias circuit on the same die as the transistor to be biased does not cost anything in term of silicon area. Furthermore, the external voltage Vgg can be applied through an input RF connection, which enables the use of regular 2 leads packages (input/output, flange being the ground connection).

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Amplifiers (AREA)

Abstract

L'invention concerne un circuit de polarisation destiné à un transistor dans un amplificateur de classe C. Ce circuit de polarisation comprend une unité de génération de tension de polarisation d'amplificateur de classe AB, une résistance connectée à l'unité de génération de tension de polarisation d'amplificateur de classe AB, ainsi qu'une unité d'injection de courant connectée entre l'unité de génération de tension de polarisation d'amplificateur de classe AB et la résistance. En cours d'utilisation, lorsqu'un courant prédéfini est injecté dans la résistance à partir de l'unité d'injection de courant, une tension est soustraite d'une tension générée par l'unité de génération de tension de polarisation d'amplificateur de classe AB, ce qui permet d'obtenir une tension de polarisation d'amplificateur de classe C souhaitée.
PCT/IB2006/054678 2006-10-03 2006-10-03 Circuit de polarisation et procédé de polarisation d'un transistor dans un amplificateur de classe c WO2008041063A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/IB2006/054678 WO2008041063A1 (fr) 2006-10-03 2006-10-03 Circuit de polarisation et procédé de polarisation d'un transistor dans un amplificateur de classe c

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2006/054678 WO2008041063A1 (fr) 2006-10-03 2006-10-03 Circuit de polarisation et procédé de polarisation d'un transistor dans un amplificateur de classe c

Publications (1)

Publication Number Publication Date
WO2008041063A1 true WO2008041063A1 (fr) 2008-04-10

Family

ID=38080927

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2006/054678 WO2008041063A1 (fr) 2006-10-03 2006-10-03 Circuit de polarisation et procédé de polarisation d'un transistor dans un amplificateur de classe c

Country Status (1)

Country Link
WO (1) WO2008041063A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012066526A1 (fr) * 2010-11-18 2012-05-24 Dsp Group Ltd. Amplificateur de puissance à polarisation adaptative
US8854143B2 (en) 2013-01-28 2014-10-07 Nxp, B.V. Bias circuit
EP3736975A1 (fr) * 2019-05-10 2020-11-11 NXP USA, Inc. Systèmes et procédés de polarisation automatique d'amplificateurs de puissance utilisant une source de courant réglable

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2269716A (en) * 1992-08-03 1994-02-16 Texas Instruments Ltd Bias circuit for changing class of part of multistage amplifier
JPH08288772A (ja) * 1995-04-14 1996-11-01 Goyo Denshi Kogyo Kk 送信電力増幅器のバイアス制御回路
US6469581B1 (en) * 2001-06-08 2002-10-22 Trw Inc. HEMT-HBT doherty microwave amplifier
US20040174213A1 (en) * 2001-09-10 2004-09-09 Thompson Philip H. Doherty bias circuit to dynamically compensate for process and environmental variations

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2269716A (en) * 1992-08-03 1994-02-16 Texas Instruments Ltd Bias circuit for changing class of part of multistage amplifier
JPH08288772A (ja) * 1995-04-14 1996-11-01 Goyo Denshi Kogyo Kk 送信電力増幅器のバイアス制御回路
US6469581B1 (en) * 2001-06-08 2002-10-22 Trw Inc. HEMT-HBT doherty microwave amplifier
US20040174213A1 (en) * 2001-09-10 2004-09-09 Thompson Philip H. Doherty bias circuit to dynamically compensate for process and environmental variations

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012066526A1 (fr) * 2010-11-18 2012-05-24 Dsp Group Ltd. Amplificateur de puissance à polarisation adaptative
US9041462B2 (en) 2010-11-18 2015-05-26 Dsp Group Ltd. Power amplifier with an adaptive bias
US8854143B2 (en) 2013-01-28 2014-10-07 Nxp, B.V. Bias circuit
EP3736975A1 (fr) * 2019-05-10 2020-11-11 NXP USA, Inc. Systèmes et procédés de polarisation automatique d'amplificateurs de puissance utilisant une source de courant réglable
US10972054B2 (en) 2019-05-10 2021-04-06 Nxp Usa, Inc. Systems and methods for automatically biasing power amplifiers using a controllable current source

Similar Documents

Publication Publication Date Title
US8159298B2 (en) Linearization circuits and methods for power amplification
JP4287190B2 (ja) 高周波増幅回路
US7522001B2 (en) Power amplifier
TW531955B (en) Power amplifier module
US7579914B2 (en) Bias circuit and power amplifier
JPH09260957A (ja) 半導体増幅回路
US10498291B2 (en) Bias circuit and power amplifier circuit
AU2004252927B2 (en) Integrated power amplifier circuit
US7049893B2 (en) Apparatus, methods and articles of manufacture for power amplifier control in a communication system
TW201911740A (zh) 電流補償電路
US6882220B2 (en) Integrated power amplifier circuit
KR102631629B1 (ko) 온도 변화에 관계없이 일정한 게인을 유지할 수 있는 전력 증폭기
AU2004252929A1 (en) Integrated power amplifier circuit
WO2008041063A1 (fr) Circuit de polarisation et procédé de polarisation d'un transistor dans un amplificateur de classe c
US6825725B1 (en) Integrated power amplifier circuit
CA2335220C (fr) Circuit de polarisation de tef
CN116526985B (zh) 一种温度补偿电路及射频功率放大器芯片
US8854143B2 (en) Bias circuit
CN115001410A (zh) 适用于线性功率放大器的偏置电路
KR100425696B1 (ko) 선형 고주파 증폭기
JP2011119987A (ja) 半導体集積回路装置
US7286016B2 (en) Amplifier bias circuit, method for biasing an amplifier and integrated circuit comprising an amplifier bias circuit

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 06832159

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 06832159

Country of ref document: EP

Kind code of ref document: A1