WO2008032895A1

WO2008032895A1 - Differential signalling circuit including passive common mode feedback circuit

Info

Publication number: WO2008032895A1
Application number: PCT/KR2006/005008
Authority: WO
Inventors: Yong Jae Lee
Original assignee: Anapass Inc
Priority date: 2006-09-11
Filing date: 2006-11-27
Publication date: 2008-03-20
Also published as: KR100695064B1; TW200814527A; TWI319262B

Abstract

The present invention relates to, and in particular to a differential signaling circuit, and in particular to a differential signaling circuit including a passive common mode feedback circuit for reducing a fluctuation of a common mode voltage. The differential signaling circuit of the present invention comprises: a differential signal line including a first line and a second line; a driver for applying a differential signal to the differential signal line; a receiving resistor connected between the first line and the second line; and a passive common mode feedback circuit including a first resistor, a second resistor and a capacitor, the first resistor being connected between the first line and a first node, and the second resistor being connected between the second line and the first node, wherein a DC voltage is applied to a first terminal of the capacitor and the first node is connected to a second terminal of the capacitor.

Description

DIFFERENTIAL SIGNALLING CIRCUIT INCLUDING PASSIVE COMMON MODE FEEDBACK CIRCUIT

Technical Field

[1] The present invention relates to, and in particular to a differential signaling circuit, and in particular to a differential signaling circuit including a passive common mode feedback circuit for reducing a fluctuation of a common mode voltage.

Background Art

[2] Of various schemes for transmitting a data, there is provided a differential signaling scheme. In accordance with the differential signaling scheme, a difference between voltage levels of two lines (differential signal lines) corresponds to a transmitted signal. As a standard related to the differential signaling scheme, a low voltage differential signaling scheme, which is a RS-644 standard defined by EIA (Electronics Industry of America) is provided. Since the differential signaling scheme utilizes the difference between the voltage levels, a degradation of a performance due to a fluctuation of a common mode voltage by a noise is small. Disclosure of Invention Technical Problem

[3] However, the fluctuation of the common mode voltage brings the degradation of the performance of the differential signaling scheme. A representative example of such case is that a signal of a multi-level is transmitted via the differential signaling scheme. Transmitting the signal of the multi-level refers to, for instance, transmitting (Vcom+Vl, Vcom-Vl), (Vcom-Vl, Vcom+Vl), (Vcom+V2, Vcom-V2) or (Vcom-V2, Vcom+V2) through a differential signal line connected to a transmitter, where Vcom denotes the common mode voltage. The second voltage V2 has a higher voltage level than the first voltage Vl. In this case, a receiver compares the differential signal inputted to the differential signal line to determine a polarity of the differential signal. In addition, the receiver compares each of the signals inputted through the two lines to reference voltages Vref 1 and Vref2 to determine a level of the differential signal according to a result of the comparison. Here, Vref 1 is a voltage higher than Vcom+Vl and lower than Vcom+V2, and Vref2 is a voltage lower than Vcom-Vl and higher than Vcom-V2. When the common mode voltage Vcom is changed to have an undesired value, Vrefl may not be positioned between Vcom+Vl and Vcom+V2, and Vref2 may not be positioned between Vcom-Vl and Vcom-V2. In this case, since the receiver cannot determine the level of the differential signal, the degradation of the performance of the transmission is generated. Therefore, the fluctuation of the common mode voltage should be prevented when the signal of the multi-level is transmitted via the differential signaling scheme in particular.

Technical Solution

[4] It is an object of the present invention to provide a differential signaling circuit that prevents a fluctuation of a common mode voltage.

[5] It is another object of the present invention to provide a differential signaling circuit that prevents the fluctuation of the common mode voltage to prevent a degradation of a transmission performance even when the signal of the multi-level is transmitted via the differential signaling scheme.

[6] In order to achieve the above-described objects of the present invention, there is provided a differential signaling circuit comprising: a differential signal line including a first line and a second line; a driver for applying a differential signal to the differential signal line; a receiving resistor connected between the first line and the second line; and a passive common mode feedback circuit including a first resistor, a second resistor and a capacitor, the first resistor being connected between the first line and a first node, and the second resistor being connected between the second line and the first node, wherein a DC voltage is applied to a first terminal of the capacitor and the first node is connected to a second terminal of the capacitor.

[7] There is also provided a differential signaling circuit comprising: a differential signal line including a first line and a second line; a driver for applying a differential signal to the differential signal line; a receiving resistor including a first resistor connected between the first line and a first node, a second resistor connected between the second line and the first node; and a capacitor including a first terminal having a DC voltage applied thereto and a second terminal connected to the first node.

[8] There is also provided a differential signaling circuit comprising: a differential signal line including a first line and a second line; a driver for applying a differential signal to the differential signal line; a receiving resistor connected between the first line and the second line; a first means for obtaining a common mode voltage of the differential signal; and a second means for connecting an AC ground to a node having the common mode voltage.

[9] There is also provided a differential signaling circuit comprising: a plurality of differential signal lines including a plurality of first lines and a plurality of second lines; a timing controller IC chip for applying a plurality of differential signals to the plurality of differential signal lines; a plurality of data driver IC chips connected to the plurality of differential signal lines; and a passive common mode feedback circuit having a plurality of first resistors connected between the plurality of first lines and a first node, a plurality of second resistors connected between the plurality of second lines and the first node, and a capacitor including a first terminal having a DC voltage applied thereto and a second terminal connected the first node. Advantageous Effects

[10] As described above, the differential signaling circuit of the present invention is advantageous in that the fluctuation of the common mode voltage may be prevented, and EMI (electromagnetic interference) may be reduced.

[11] Particularly, even when the signal of the multi-level is transmitted via the differential signaling scheme, the differential signaling circuit in accordance with the present invention prevents the fluctuation of the common mode voltage to prevent a degradation of a transmission performance. Brief Description of the Drawings

[12] Fig. 1 is a diagram illustrating a differential signaling circuit in accordance with a first embodiment of the present invention.

[13] Fig. 2 is a diagram illustrating a driver 10 that may be employed in the differential signaling circuit of Fig. 1 wherein the driver is capable of driving a differential signal of a multi-level and includes an active common mode feedback circuit.

[14] Fig. 3 is a graph illustrating an effect of a passive common mode feedback circuit

40 in the differential signaling circuit of Figs. 1 and 2.

[15] Fig. 4 is a diagram illustrating a differential signaling circuit in accordance with a second embodiment of the present invention.

[16] Fig. 5 is a diagram illustrating a differential signaling circuit in accordance with a third embodiment of the present invention.

[17] Fig. 6 is a diagram illustrating a differential signaling circuit in accordance with a fourth embodiment of the present invention.

[ 18] [Description of Reference Numerals]

[19] 10: driver 20: receiving resistor

[20] 31, 32: line

[21] 40, 41, 42, 43: passive common mode feedback circuit

[22] 50: timing controller IC chip

[23] 60: data driver IC chip

Best Mode for Carrying Out the Invention

[24] Preferred embodiments of the present invention will now be described in detail with reference to the accompanied drawings. The preferred embodiments of the present invention may vary in their forms, and a scope of the present invention should not be limited to the embodiments described below. The preferred embodiments of the present invention are provided so as to give a complete description of the present invention to a skilled in the art. [25] Fig. 1 is a diagram illustrating a differential signaling circuit in accordance with a first embodiment of the present invention, wherein the differential signaling circuit is applied to a timing controller and a data driver of a display.

[26] Referring to Fig. 1, the differential signaling circuit comprises a driver 10, a receiving resistor 20, differential signal lines 31 and 32 and a passive common mode feedback circuit 40.

[27] The driver 10 outputs a differential signal to the differential signal lines 31 and 32.

The differential signal outputted from the driver 10 may be a differential signal of a single level or a differential signal of a multi-level. When the differential signal outputted from the driver 10 is the differential signal of the single level, the driver 10 generally outputs (Vcom+Vl, Vcom-Vl) or (Vcom-Vl, Vcom+Vl) through the differential signal lines 31 and 32. Vcom denotes a common mode voltage and Vl denotes a predetermined voltage. When the differential signal outputted from the driver 10 is the differential signal of the multi-level, the driver 10 may output, for instance, three types of differential voltages (Vcom+Vl, Vcom-Vl), (Vcom-Vl, Vcom+Vl) and (Vcom, Vcom) through the differential signal lines 31 and 32. In addition, in one embodiment, the driver 10 may output four types of differential voltages (Vcom+Vl, Vcom-Vl), (Vcom-Vl, Vcom+Vl), (Vcom+V2, Vcom-V2) and (Vcom-V2, Vcom+V2) through the differential signal lines 31 and 32. V2 denotes a voltage having a higher voltage level than Vl. The driver 10, when required, may be designed to output various differential signals of more than four types.

[28] As shown, the driver 10 may be included in a timing controller IC (Integrate

Circuit) chip 50. In this case, the driver 10 may embed a clock signal between a data signal wherein the clock signal has a different signal amplitude from the data signal to be transmitted to a data driver IC chip 60 through the differential signal lines 31 and 32. A scheme for embedding the clock signal between the data signal to have the different signal amplitude is disclosed in Korean Patent Application No. 10-2005-0088619 titled DISPLAY, TIMING CONTROLLER AND COLUMN DRIVER INTEGRATED CIRCUIT USING CLOCK EMBEDDED MULTI-LEVEL SIGNALING and Korean Patent Application No. 10-2005-0088611 titled DISPLAY, COLUMN DRIVER INTEGRATED CIRCUIT, AND MULTI-LEVEL DETECTOR, AND MULTI-LEVEL DETECTION METHOD filed by the Applicant. A plurality of drivers 10 may be included in the timing controller IC chip 50 as shown, or a single driver 10 may be included in the timing controller IC chip 50 on the contrary.

[29] Terminals of the receiving resistor 20 are respectively connected to the differential signal lines 31 and 32, and it is preferable that a resistance thereof is 100 for an impedance matching.

[30] As shown, the receiving resistor 20 may be included in the data driver IC chip 60. Generally, the receiving resistor 20 may be embodied per data driver IC chip 60. The data driver IC chip 60 comprises a receiver (not shown) for restoring an original signal from the differential signal transmitted from the driver 10. An example of a structure of the receiver is disclosed in Korean Application No. 10-2005-0088611.

[31] The passive common mode feedback circuit 40 is connected to the differential signal lines 31 and 32 to reduce a fluctuation of the common mode voltage of the differential signal lines 31 and 32. The passive common mode feedback circuit 40 comprises a passive network consisting of resistors Rl and R2 and a capacitor C. a voltage of a first node Nl connected to the resistors Rl and R2 is a mean value of two voltages of the differential signal lines 31 and 32, i.e. The common mode voltage Vcom because of the resistors Rl and R2 having a same resistance. The first node Nl operates as an AC ground because of the capacitor C including a first terminal having a DC voltage applied thereto and a second terminal connected to the first node Nl. That is, an AC component of the common mode voltage Vcom, i.e. the voltage of the first node Nl is removed by the capacitor C. In this manner, the passive common mode feedback circuit 40 reduces the fluctuation of the common mode voltage.

[32] An output resistance of the driver 10 equals that of the resistors Rl and R2 and the receiving resistor 20 in parallel. It is preferable that the resistors Rl and R2 respectively have the resistance of no less than 200 when the resistance of the receiving resistor 20 is 100 . When the resistors Rl and R2 have the resistance of 200 , the output resistance of the driver is 80 . Therefore, when the resistors Rl and R2 have the resistance of no less than 200 , the output resistance of the driver 10 is no less than 80 and less than 100 , and this output resistance is acceptable considering the impedance matching and the voltage of the common mode voltage. When the resistance of the receiving resistor 20 is not required to be 100 , the resistances of the receiving resistor 20 and the resistors Rl and R2 may be configured such that the resistance of the resistors Rl and R2 in serial and the receiving resistor 20 in parallel is 100 . For instance, when the resistances of the resistors Rl and R2 are 100 respectively and the resistance of the receiving resistor 20 is 200 , the output resistance of the driver 10 is 100 . In addition, since the fluctuation of the common mode voltage cannot be reduced rapidly when the resistances of the resistors Rl and R2 are excessively large, it is preferable that the resistances of the resistors Rl and R2 is no more than Ik .

[33] It is preferable that a capacitance of the capacitor C is sufficiently large such that the first node Nl may serve as the Ac ground. Therefore, it is preferable that the capacitance of the capacitor C is no lee than InF.

[34] Fig. 2 is a diagram illustrating a driver 10 that may be employed in the differential signaling circuit of Fig. 1 wherein the driver is capable of driving a differential signal of a multi-level and includes an active common mode feedback circuit. [35] Referring to Fig. 2, the driver 10 comprises a polarity steering circuit, current sources CSl and CS2, multi-level switches SWN and SWP and an active common mode feedback circuits.

[36] The polarity steering circuit determines a polarity of the differential signal outputted through output terminals OUT and OUTB according to polarity control signals PL and PLB. The polarity steering circuit comprises first and second PMOSs (P-channel metal oxide semiconductors) MPl and MP2 and first and second NMOSs (N-channel metal oxide semiconductors) MNl and MN2. First terminals (sources) of the first and second PMOSs MPl and MP2 are connected to each other and first terminals (drains) of the first and second NMOSs MNl and MN2 are connected to each other. A second terminal (drain) of the first PMOS MPl is connected to a second terminal (drain) of the first NMOS MNl, and a second terminal (drain) of the second PMOS MP2 is connected to a second terminal (drain) of the second NMOS MN2.

[37] The current sources CSl and CS2 apply a constant current to the polarity steering circuit. In accordance with the embodiment, the current source CSl provides a current I to the polarity steering circuit, and the current source CS2 provides a current 21 corresponding to a double amount of that of the current source CSl to the polarity steering circuit. The current source CSl is directly connected to the polarity steering circuit to continuously provide the current to the polarity steering circuit, and the current source CS2 is connected to the polarity steering circuit through the multi-level switch SWN to provide the current to the polarity steering circuit according to a level control signal LV.

[38] The multi-level switches SWP and SWN controls an amount of current applied to the polarity steering circuit and a voltage level of the differential signal. More specifically, when the multi-level switches SWP and SWN are turned off, a difference between two voltages of the differential signal applied to the output terminals OUT and OUTB corresponds to PRout since only the current I provided from the current source CSl flows in the polarity steering circuit. Rout denotes the output resistance of the driver 10. When the multi-level switches SWP and SWN are turned on, the difference between the two voltages of the differential signal applied to the output terminals OUT and OUTB corresponds to 3I*Rout since a current 31 provided from the current sources CSl and CS2 flows in the polarity steering circuit. Accordingly, the level of the differential signal may be controlled by the multi-level switches SWP and SWN. Preferably, the multi-level switch SWP is a PMOS transistor, and the multilevel switch SWN is a NMOS transistor. When the multi-level switches SWP and SWN configured as shown, an unnecessary power consumption may be prevented. That is, when a voltage of a low level is outputted through the output terminals OUT and OUTB, only the current I flows because only the current source CSl provides the current. When a voltage of a high level is outputted through the output terminals OUT and OUTB, only the current 31 flows because the current sources CSl and CS2 provide the current. However, while a problem that the common mode voltage Vcom fluctuates when the current is changed from I to 31 or 31 to I occurs, the problem may be overcome by the passive common mode feedback circuit 40 described with reference to Fig. 1. While a circuit wherein the fluctuation of the common mode voltage Vcom due to the switching is reduced by continuously providing the current from the current sources CSl and CS2, it is problematic that the power consumption is increased.

[39] The active common mode feedback circuit controls the common mode voltage

Vcom using active components such as an amplifier AMP, a first transistor Ml and a second transistor M2. The active common mode feedback circuit comprises third and fourth resistors R3 and R4, the amplifier AMP, the first and second transistors Ml and M2. The third and fourth resistors R3 and R4 are connected to the output terminals OUT and OUTB to obtain the common mode voltage Vcom from the differential signal. It is preferable that resistances of the third and fourth resistors R3 and R4 are few k . The amplifier AMP outputs a voltage corresponding to a difference between the common mode voltage Vcom and a reference common mode voltage Vcom_ref. resistances of the first and second transistors Ml and M2 varies according to the output of the amplifier AMP to change the level of the voltage applied to the polarity steering circuit, resulting in a variation of the common mode voltage Vcom. As a result, the active common mode feedback circuit provides a negative feedback so as to maintain the common mode voltage Vcom same as the reference common mode voltage Vcom_ref. While an example wherein the first and second transistors Ml and M2 are embodied using PMOS transistors are shown, the first and second transistors Ml and M2 may be embodied using NMOS transistors (therefore references limiting the first and second transistors to PMOS or NMOS are not used). In this case, a position of the first and second transistors Ml and M2 and that of the current sources CSl and CS2 should be exchanged.

[40] The common mode voltage of the differential signal outputted from the driver 10 may vary despite the active common mode feedback circuit. A main reason is a difference between switching times of the PMOS transistor used as the multi-level switch SWP and the NMOS transistor used as the multi-level switch SWN. That is, since the switching time of the NMOS transistor is generally shorter than that of the PMOS transistor, the multi-level switch SWN reaches an on state first even when the multi-level switches SWP and SWN are turned on simultaneously. This lowers the common mode voltage Vcom instantly and fluctuates the common mode voltage Vcom resultantly.

[41] The driver 10 may output the voltage of the single level. In this case, the driver 10 does not comprise the multi-level switches SWP and SWN, the current source CS2 and the second transistor M2. The fluctuation of the common mode voltage is not serious compared to outputting the voltage of the multi-level since the switching is not carried out.

[42] When the driver 10 embeds and transmits the clock signal between the data signal to have the amplitude different from that of the data signal through the differential signal line connected to the output terminals OUT and OUTB, the polarity control signals PL and PLB corresponds to the data signal and the level control signal LV corresponds to the clock signal.

[43] Fig. 3 is a graph illustrating an effect of a passive common mode feedback circuit

40 in the differential signaling circuit of Figs. 1 and 2. (a) of Fig. 3 illustrates the differential signal incase that only the active common mode feedback circuit is used without using the passive common mode feedback circuit 40, (b) of Fig. 3 illustrates the differential signal incase that both the active common mode feedback circuit and the passive common mode feedback circuit 40 are used.

[44] Comparing (a) and (b) of Fig. 3, the fluctuation of the differential signal is reduced to one fourth by adding the passive common mode feedback circuit 40.

[45] Fig. 4 is a diagram illustrating a differential signaling circuit in accordance with a second embodiment of the present invention. The differential signaling circuit shown in Fig. 4 is identical to the differential signaling circuit shown in Fig. 1 except that a capacitor C is commonly used in a passive common mode feedback circuit 41, when compared to the differential signaling circuit shown in Fig. 1. Therefore, a detailed description of Fig. 4 is omitted. The differential signaling circuit shown in Fig. 4 is advantageous over the differential signaling circuit shown in Fig. 1 in that only one capacitor is used.

[46] Fig. 5 is a diagram illustrating a differential signaling circuit in accordance with a third embodiment of the present invention. The differential signaling circuit shown in Fig. 5 is identical to the differential signaling circuit shown in Fig. 4 except that resistors Rl and R2 of a passive common mode feedback circuit 42 are embodied inside the timing controller IC chip 50, and the capacitor C is embodied outside the timing controller IC chip 50 when compared to the differential signaling circuit shown in Fig. 4. Therefore, a detailed description of Fig. 4 is omitted. In accordance with the differential signaling circuit shown in Fig. 5, the resistors Rl and R2 are embodied in the timing controller IC chip 50 so that a design of a board including the timing controller IC chip 50 and the data driver IC chip 60 is facilitated and a manufacturing cost thereof is reduced when compared to the differential signaling circuit shown in Fig. 4.

[47] Fig. 6 is a diagram illustrating a differential signaling circuit in accordance with a fourth embodiment of the present invention. The differential signaling circuit shown in Fig. 6 is identical to the differential signaling circuit shown in Fig. 1 except that a passive common mode feedback circuit 43 is embodied using the receiving resistor 20 when compared to the differential signaling circuit shown in Fig. 1. Therefore, a detailed description of Fig. 4 is omitted. The differential signaling circuit shown in Fig. 6 is advantageous over the differential signaling circuit shown in Fig. 1 in that the output resistance of the driver 10 is the same as that of receiving resistor, and a separate resistor is not required to embody the passive common mode feedback circuit 43.

Claims

[1] A differential signaling circuit comprising: a differential signal line including a first line and a second line; a driver for applying a differential signal to the differential signal line; a receiving resistor connected between the first line and the second line; and a passive common mode feedback circuit including a first resistor, a second resistor and a capacitor, the first resistor being connected between the first line and a first node, and the second resistor being connected between the second line and the first node, wherein a DC voltage is applied to a first terminal of the capacitor and the first node is connected to a second terminal of the capacitor.

[2] The circuit in accordance with claim 1, wherein the first resistor and the second resistor have a same resistance value.

[3] The circuit in accordance with claim 2, wherein the driver outputs the differential signal of a multi-level.

[4] The circuit in accordance with claim 2, wherein the driver comprises: a polarity steering circuit for steering a polarity of the differential signal outputted from the differential signal line according to a polarity control signal; a current source for applying a constant current to the polarity steering circuit; a multi-level switch for controlling an amount of the constant current applied to the polarity steering circuit according to a level control signal; and an active common mode feedback circuit for providing a negative feedback by changing a level of a voltage applied to the polarity steering circuit according to a difference between a common mode voltage of the differential signal and a predetermined reference voltage.

[5] The circuit in accordance with claim 4, wherein the polarity steering circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, a first terminal of the first PMOS transistor being connected to a first terminal of the second PMOS transistor, a second terminal of the first PMOS transistor being connected to the first line, a second terminal of the second PMOS transistor being connected to the second line, a first terminal of the first NMOS transistor being connected to a first terminal of the second NMOS transistor, a second terminal of the first NMOS transistor being connected to the first line, and a second terminal of the second NMOS transistor being connected to the second line.

[6] The circuit in accordance with claim 4, wherein the current source comprises first and second current sources, the first current source applying a predetermined first current to the polarity steering circuit and the second current source selectively applying a predetermined second current to the polarity steering circuit according to the level control signal.

[7] The circuit in accordance with claim 6, wherein the active common mode feedback circuit comprises: a third resistor connected between the first line and a second node; a fourth resistor connected between the second line and the second node; an amplifier outputting a voltage corresponding to a difference between a voltage of the second node which is the common mode voltage and the reference voltage; a first transistor for applying a current corresponding to the first current to the polarity steering circuit and for changing a level of a voltage applied to the polarity steering circuit according to an output of the amplifier; and a second transistor for applying a current corresponding to the second current to the polarity steering circuit and for changing the level of the voltage applied to the polarity steering circuit according to an output of the amplifier.

[8] The circuit in accordance with claim 7, wherein the multi-level switch comprises a first switch and a second switch, the first switch being connected between the second current source and the polarity steering circuit, and the second switch being connected between the second transistor and the polarity steering circuit.

[9] The circuit in accordance with claim 2, wherein the receiving resistor is 100 and the first resistor and the second resistor are no less than 200 and no larger than Ik , respectively.

[10] The circuit in accordance with claim 2, wherein a resistance value by the first and second resistor and the receiving resistor in parallel is 100 .

[11] The circuit in accordance with claim 2, wherein the capacitor is no less than 1 nF.

[12] A differential signaling circuit comprising: a differential signal line including a first line and a second line; a driver for applying a differential signal to the differential signal line; a receiving resistor including a first resistor connected between the first line and a first node, a second resistor connected between the second line and the first node; and a capacitor including a first terminal having a DC voltage applied thereto and a second terminal connected to the first node.

[13] The circuit in accordance with claim 12, wherein the first resistor and the second resistor have a same resistance value.

[14] The circuit in accordance with claim 13, wherein the driver outputs the differential signal of a multi-level.

[15] The circuit in accordance with claim 13, wherein the driver comprises: a polarity steering circuit for steering a polarity of the differential signal outputted from the differential signal line according to a polarity control signal; a current source for applying a constant current to the polarity steering circuit; a multi-level switch for controlling an amount of the constant current applied to the polarity steering circuit according to a level control signal; and an active common mode feedback circuit for providing a negative feedback by changing a level of a voltage applied to the polarity steering circuit according to a difference between a common mode voltage of the differential signal and a predetermined reference voltage.

[16] A differential signaling circuit comprising: a differential signal line including a first line and a second line; a driver for applying a differential signal to the differential signal line; a receiving resistor connected between the first line and the second line; a first means for obtaining a common mode voltage of the differential signal; and a second means for connecting an AC ground to a node having the common mode voltage.

[17] The circuit in accordance with claim 16, wherein the driver outputs the differential signal of a multi-level.

[18] The circuit in accordance with claim 16, wherein the driver comprises: a polarity steering circuit for steering a polarity of the differential signal outputted through the differential signal line according to a polarity control signal; a current source for applying a constant current to the polarity steering circuit; a multi-level switch for controlling an amount of the constant current applied to the polarity steering circuit according to a level control signal; and an active common mode feedback circuit for providing a negative feedback by changing a level of a voltage applied to the polarity steering circuit according to a difference between the common mode voltage of the differential signal and a predetermined reference voltage.

[19] A differential signaling circuit comprising: a plurality of differential signal lines including a plurality of first lines and a plurality of second lines; a timing controller IC chip for applying a plurality of differential signals to the plurality of differential signal lines; a plurality of data driver IC chips connected to the plurality of differential signal lines; and a passive common mode feedback circuit having a plurality of first resistors connected between the plurality of first lines and a first node, a plurality of second resistors connected between the plurality of second lines and the first node, and a capacitor including a first terminal having a DC voltage applied thereto and a second terminal connected the first node.

[20] The circuit in accordance with claim 19, wherein the plurality of first resistors and the plurality of second resistors are embodied inside the timing controller IC chip.

[21] The circuit in accordance with claim 19, wherein the passive common mode feedback circuit is embodied on a board including the plurality of differential signal lines, the timing controller IC chip and the plurality of data driver IC chips.

[22] The circuit in accordance with claim 19, wherein the plurality of driver IC chips output the plurality of differential signals of a multi-level.

[23] The circuit in accordance with claim 19, wherein each of the plurality of driver

IC chips comprises: a polarity steering circuit for steering a polarity of a corresponding differential signal of the plurality of differential signals outputted through a corresponding differential signal line of the plurality of differential signal lines according to a polarity control signal; a current source for applying a constant current to the polarity steering circuit; a multi-level switch for controlling an amount of the constant current applied to the polarity steering circuit according to a level control signal; and an active common mode feedback circuit for providing a negative feedback by changing a level of a voltage applied to the polarity steering circuit according to a difference between a common mode voltage of the differential signal and a predetermined reference voltage.