KR100687323B1 - LCD line inversion Vcom circuit - Google Patents

Abstract

The present invention relates to a circuit for converting a polarity signal into a common voltage whose amplitude and level are adjustable in a line inversion driving circuit of a liquid crystal display device (LCD) module.

According to an aspect of the present invention, there is provided a circuit for converting a polarity signal into a common voltage having an adjustable amplitude and level, the circuit comprising: an input unit configured to receive a polarity signal; A common voltage output unit configured to output a common voltage according to the signal output from the input unit; An amplitude adjusting unit controlling an amplitude of the common voltage output from the common voltage output unit; And a level controller for adjusting the level of the common voltage.

Description

Common voltage conversion circuit for line inversion of liquid crystal display device {LCD line inversion Vcom circuit}

1 is a common voltage conversion circuit for driving a line inversion of a conventional liquid crystal display device.

2 is a common voltage conversion circuit for driving line inversion of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a diagram illustrating a simulation result according to a change in a resistance value in a common voltage conversion circuit for driving a line inversion of a liquid crystal display according to an exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

10: input unit 20: overcurrent protection means

30: common voltage output unit 40: amplitude control unit

50: level control

N1, N2: NMOS transistor P1: PMOS transistor

21, 22, 41, 43, 51, 53: resistors 42, 52: variable resistors

12, 44: capacitor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line inversion driving circuit of a liquid crystal display (LCD) module, and more particularly to a circuit for converting a polarity signal into a common voltage.

In driving the LCD module, a signal for driving the module always includes a common voltage (Vcom) and an on / off signal for determining whether a signal is applied to each segment. In this case, the liquid crystal applied voltage is determined by the logical combination of the two signals. In the line inversion driving method, the common voltage should be alternating in amplitude and level, and the common voltage and the data voltage are changed and applied to each line. Therefore, in the above-described line inversion driving circuit, a circuit for converting a polarity signal into a common voltage whose amplitude and level are adjustable is required, and the amplitude corresponding to the difference between the maximum value and the minimum value of the polarity signal changed from line to line is adjusted. The common voltage signal is obtained by adjusting the level while keeping the amplitude constant.

1 illustrates a conventional voltage conversion circuit for inverting a line. Referring to FIG. 1, in a conventional line inversion common voltage conversion circuit, a polarity signal MPOL is input to a inverting (−) terminal of a first OPal amplifier (OP1) through a resistor R1 and is connected to the first voltage. A variable resistor VR1, resistors R2 and R3, and a capacitor C3 are connected to the non-inverting (+) terminal of the OP amplifier OP2 to adjust the amplitude of the common voltage Vcom. In addition, the variable resistor VR2 and the capacitor C1 are disposed between the inverting (-) terminal of the first OP amplifier OP1 and the output terminal of the first OP amplifier OP1 to adjust the level of the common voltage Vcom. Are connected in parallel, where they amplify the polarity signal MPOL.

In addition, there is a second OP amplifier OP2 that receives the output of the first OP amplifier OP1 as an input so that the signal amplified by the first OP amplifier OP1 is amplified again, and the second OP amplifier is The output of OP2 is a current booster for amplifying a current consisting of an NPN bipolar junction transistor (BJT), a PNP BJT, and capacitors C4 and C5 through a resistor R5. Connected to the circuit. At this time, the resistor R4 and the capacitor C2 are connected in parallel between the non-inverting (+) input terminal of the second OP amplifier OP2 and the output terminal of the current booster circuit, so that the output signal of the current booster circuit Together they become a common voltage Vcom.

However, the conventional common voltage conversion circuit for line inversion as described above is composed of a large number of circuit elements such as an expensive OP amplifier, a current booster circuit, a capacitor, and a resistor, which is expensive to manufacture and has a large area occupied by the entire circuit.

In addition, when noise is introduced from the outside, the noise component is amplified through the OP amplifier as it appears on the output side, there is a disadvantage that the screen quality of the LCD panel (Panel) is also degraded.

In order to solve the problems of the prior art as described above, the present invention does not use expensive OP amplifiers or current booster circuits, but uses only MOS (Metal Oxide Semiconductor), resistors, and capacitors. By implementing the voltage conversion circuit, the goal is to reduce the cost of circuit fabrication and to reduce the area on the printed circuit board (PCB) that the entire components occupy.

It is still another object of the present invention to provide a common voltage conversion circuit for line inversion that is independent of noise from outside by using a complementary MOS (PMOS) composed of a P-channel MOS (PMOS) transistor and an N-channel MOS (NMOS) transistor. The purpose is to provide.

In order to achieve the above object of the present invention, the present invention provides a circuit for converting a polarity signal to a common voltage signal in the case of the line inversion method of the LCD module, the input unit for inputting a polarity signal; A common voltage output unit configured to output a common voltage according to the signal output from the input unit; An amplitude adjusting unit controlling an amplitude of the common voltage output from the common voltage output unit; And a level adjusting unit adjusting the level of the common voltage.

The input unit includes an NMOS transistor and a resistor, and outputs a signal for controlling the common voltage output unit according to a polarity signal.

The common voltage output unit may include a CMOS and a capacitor in which a PMOS transistor and an NMOS transistor are connected in series, and output a common voltage by turning on the PMOS transistor or the NMOS transistor according to a signal of the input unit.

The common voltage output unit cuts the DC component and outputs a common voltage of the AC component by passing the signal output from the CMOS through a capacitor.

The input unit may include an overcurrent preventing means for preventing an overcurrent from flowing between a power supply and a ground when the PMOS transistor and the NMOS transistor constituting the common voltage output unit are turned on at the same time.

The overcurrent prevention means prevents the PMOS transistor and the NMOS transistor from being turned on at the same time by distributing a voltage applied to the gates of the PMOS transistor and the NMOS transistor constituting the common voltage output unit by connecting resistors of different sizes in series. Characterized in that.

The amplitude adjusting unit includes a plurality of resistors and a capacitor, and adjusts an amplitude corresponding to a difference between a maximum value and a minimum value of a common voltage by adjusting a variable resistor.

The level adjusting unit is configured of a plurality of resistors, characterized in that for adjusting the level of the common voltage in a state in which the amplitude is kept constant by adjusting the variable resistor.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 illustrates a common voltage conversion circuit in the LCD line inversion driving method according to an embodiment of the present invention. Referring to FIG. 2, the present invention provides an input unit 10 that receives a polarity signal MPOL; A common voltage output unit 30 outputting a common voltage Vcom according to the signal output from the input unit 10; An amplitude adjusting unit 40 for adjusting the amplitude of the common voltage Vcom output from the common voltage output unit 30; And a level controller 50 for adjusting the level of the common voltage Vcom.

The input unit 10 includes a first NMOS transistor N1 and an overcurrent preventing means 20. A drain of the first NMOS transistor N1 is connected to a power supply voltage Vcc through the overcurrent preventing means 20. ), The source is connected to a ground power source, and receives a polarity signal MPOL through a gate.

In the overcurrent preventing means 20, the first and second resistors 21 and 22 are connected in series so that the first resistor 21 is connected to the power supply voltage Vcc, and the second resistor 22 is the first NMOS. A voltage of the first node n1 between the first resistor 21 and the second resistor 22 is connected to the drain of the transistor N1, and the first PMOS transistor P1 constituting the common voltage output unit 30. Voltage of the second node n2 between the second resistor 22 and the drain of the first NMOS transistor N1 is applied to the gate of the second NMOS transistor N2 of the common voltage output unit 30. Applied to the gate.

The common voltage output unit 30 includes a CMOS and a capacitor 31 in which a drain of the first PMOS transistor P1 and a drain of the second NMOS transistor N2 are connected to each other. The first PMOS transistor P1 The source of is provided to the amplitude control unit 40, the source of the second NMOS transistor (N2) is connected to the ground power supply, the common voltage (Vcom) is the first PMOS transistor (P1) and the second NMOS transistor (N2). Is output through the first capacitor 31 connected to the drain of the capacitor.

The amplitude adjusting unit 40 has resistors 42 and 43 and a capacitor 44 connected in parallel, and a resistor 41 and a power supply voltage Vcc are connected in series. The variable resistor 42 ), A desired voltage is always applied to the source of the first PMOS transistor P1, that is, the node A.

The level adjuster 50 has resistors 51, 52, 53 and a power supply of -5 volts connected in series, and by adjusting the variable resistor 52, voltage distribution by the values of the resistors 51, 52, 53 is adjusted. As a result, the common voltage Vcom having a desired level can be output to the output terminal of the common voltage output unit 30.

Therefore, the common voltage Vcom can be adjusted to have a specific amplitude by adjusting the variable resistor 42 of the amplitude adjuster 40 of the present invention, and the amplitude is adjusted by adjusting the variable resistor 52 of the level adjuster 50. The level of the common voltage Vcom can be adjusted while keeping the constant.

The operation of the common voltage circuit according to the embodiment of the present invention as described above is as follows.

First, in order to adjust the amplitude of the common voltage Vcom, the variable resistor 42 of the amplitude adjusting unit 40 is adjusted to adjust the voltage applied to the node A. The node A has the variable resistor 42 adjusted above. ) And the remaining resistors 41 and 43 maintain a constant voltage, and the adjusted voltage becomes the amplitude of the common voltage Vcom.

When the variable resistor 52 of the level adjuster 50 is adjusted while the amplitude is kept constant, the common voltage Vcom is controlled by the variable resistor 52 of the level adjuster 50 and the remaining resistors 51 and 53. ), The amplitude does not change, only the level changes.

As described above, the polarity signal MPOL is applied to the input unit 10 while the amplitude and level of the common voltage Vcom are adjusted, and the polarity signal MPOL has a value between 0 and 3.3 volts. . When the polarity signal MPOL is applied in a state of "0", the first NMOS transistor N1 is turned off and no current flows in the input unit 10, so that the common voltage output unit 30 is applied. The power supply voltage Vcc of 5 volts is applied to the gate of the first PMOS transistor P1 and the gate of the second NMOS transistor N2. The applied voltage (5 volts) turns on the second NMOS transistor N2 of the common voltage output unit 30, and the common voltage output unit 30 is connected to the capacitor 31. The common voltage Vcom of "0" is output. At this time, by adjusting the variable resistor 52 of the level adjuster 50, the common voltage Vcom of " 0 " can be changed into a negative signal of a desired level.

When the polarity signal MPOL is applied to the gate of the first NMOS transistor N1 of the input unit 10 with 3.3 volts, the first NMOS transistor N1 is turned on and through the resistors 21 and 22. The current flows through the first PMOS transistor P1 constituting the common voltage output unit 30 because the lower resistor 22 uses 150 mA and the upper resistor 21 uses 1 mA. A low voltage is applied to the gate of the 2 NMOS transistor N2. Therefore, the first PMOS transistor P1 and the second NMOS transistor N2 are not turned on at the same time, and only the first PMOS transistor P1 is turned on so that the common state is high through the capacitor 31. The voltage Vcom is output. Here, the common voltage Vcom may be adjusted to a desired level by adjusting the variable resistor 52 of the level adjuster 50.

When the first PMOS transistor P1 and the second NMOS transistor N2 of the common voltage output unit 30 are turned on at the same time, power is supplied through the first PMOS transistor P1 and the second NMOS transistor N2. An overcurrent flows from the voltage Vcc to the ground power source. As described above, resistors 21 and 22 having different values are connected to the input unit 10 in series, so that the first PMOS transistor P1 and the second NMOS are connected in series. By preventing the transistor N2 from being turned on at the same time, overcurrent can be prevented from flowing.

FIG. 3 shows that after adjusting the variable resistor 42 of the amplitude adjusting unit 40 in the common voltage conversion circuit for inverting the LCD line according to the embodiment of the present invention, the node A is set to have a voltage of 3.8 volts. This is a result of simulating the change of the common voltage Vcom according to the change of the variable resistor 52 of the level adjuster 50. Referring to FIG. 3, when the suppression of the node A is set to 3.8 volts by adjusting the variable resistor 42 of the amplitude adjusting unit 40, the polarity signal MPOL transitions between 3.3 volts and 0 volts. It can be seen that the voltage VA of node A remains constant at 3.8 volts even if it changes.

As described above, when the amplitude is fixed and the value of the variable resistor 52 of the level adjuster 50 is changed to 1 kV, 1.5 kV, and 2 kV, the common voltage Vcom is V1, V2, and V3, respectively. In this case, the amplitude of the common voltage Vcom is kept constant at 3.8 volts even when the variable resistor 52 of the level adjuster 50 is changed and the level of the common voltage Vcom is changed. have.

As can be seen from the above simulation results, in the LCD voltage inversion common voltage conversion circuit according to the embodiment of the present invention, in converting the polarity signal MPOL into the common voltage Vcom whose amplitude and level are adjustable. The common voltage Vcom having a desired amplitude and level can be obtained by adjusting the variable resistor 42 for adjusting the amplitude and the variable resistor 52 for adjusting the level.

As described in detail above, according to the common voltage conversion circuit of the present invention, as in the case of the common voltage conversion circuit for LCD line inversion of the prior art, three MOS transistors without expensive OP Amp and many circuit elements are used. Using only resistors and capacitors can reduce the cost of circuit fabrication and reduce the area that the entire circuit occupies on the PCB.

In addition, in the case of using the OP Amp, not only the polarity signal but also the external noise is amplified by the OP Amp to appear on the common voltage which is the output signal. The screen quality of the LCD panel can be improved.

In addition, by connecting a resistor having a different value to the gates of the PMOS transistor and the NMOS transistor constituting the CMOS, the PMOS transistor and the NMOS transistor can be prevented from being turned on at the same time, and the overcurrent can be prevented from flowing.

The present invention can be practiced in various ways without departing from the spirit and scope of the invention.

Claims (7)

In the circuit for converting the polarity signal to a common voltage in the case of the line inversion method of the LCD module, An input unit for inputting a polarity signal, A common voltage output unit outputting a common voltage according to the signal output from the input unit; An amplitude adjusting unit for adjusting an amplitude of the common voltage output from the common voltage output unit; And a level controller for adjusting the level of the common voltage. The method of claim 1, wherein the input unit It consists of a first NMOS transistor and overcurrent protection means, And the drain of the first NMOS transistor is connected to a power supply voltage through an overcurrent prevention means, the source is connected to a ground power supply, and a polarity signal is provided through a gate. The method of claim 1, wherein the common voltage output unit The drain of the first PMOS transistor and the drain of the second NMOS transistor are composed of a CMOS and a capacitor connected to each other. The source of the first PMOS transistor is provided to an amplitude adjusting unit, the source of the second NMOS transistor is connected to the ground power supply, and the common voltage is output through a capacitor connected to the drain of the first PMOS transistor and the second NMOS transistor. A common voltage conversion circuit characterized by. The method of claim 2, wherein the overcurrent prevention means By applying a different voltage to the gate of the first PMOS transistor and the second NMOS transistor constituting the CMOS of the common voltage output unit, it is characterized in that the first PMOS transistor and the second NMOS transistor is not turned on at the same time Common voltage conversion circuit. The method of claim 4, wherein the overcurrent prevention means The first and second resistors are connected in series so that the first resistor leads to the power supply voltage and the second resistor leads to the drain of the first NMOS transistor. The voltage at the first node between the first resistor and the second resistor is applied to the gate of the first PMOS transistor constituting the common voltage output, and the voltage at the second node between the drain of the second resistor and the first NMOS transistor is And a common voltage conversion circuit applied to the gate of the second NMOS transistor. The method of claim 1, wherein the amplitude adjustment unit A resistor and a variable resistor adjacent thereto are connected in parallel with a capacitor, and a resistor and a power supply voltage are connected in series, so that a specific voltage is always applied to the source of the first PMOS transistor by adjusting the variable resistor. A common voltage conversion circuit. The method of claim 1, wherein the level control unit A common voltage conversion circuit comprising a resistor and a variable resistor and a power supply of -5 volts connected in series, and outputting a common voltage having a desired level to an output terminal of the common voltage output unit by adjusting the variable resistor.

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