WO2008016740A2 - Interconnect structure and process of making the same - Google Patents

Interconnect structure and process of making the same Download PDF

Info

Publication number
WO2008016740A2
WO2008016740A2 PCT/US2007/069219 US2007069219W WO2008016740A2 WO 2008016740 A2 WO2008016740 A2 WO 2008016740A2 US 2007069219 W US2007069219 W US 2007069219W WO 2008016740 A2 WO2008016740 A2 WO 2008016740A2
Authority
WO
WIPO (PCT)
Prior art keywords
liner
layer
openings
via openings
forming
Prior art date
Application number
PCT/US2007/069219
Other languages
French (fr)
Other versions
WO2008016740A3 (en
Inventor
Theodorus E. Standaert
Pegeen M. Davis
John A. Fitzsimmons
Stephen E. Greco
Tze-Man Ko
Naftali E. Lustig
Lee M. Nicholson
Sujatha Sankaran
Original Assignee
International Business Machines Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corporation filed Critical International Business Machines Corporation
Priority to CN2007800268526A priority Critical patent/CN101490827B/en
Priority to KR1020097001301A priority patent/KR101130557B1/en
Priority to EP07783916.5A priority patent/EP2047506B1/en
Priority to JP2009522906A priority patent/JP2009545889A/en
Publication of WO2008016740A2 publication Critical patent/WO2008016740A2/en
Publication of WO2008016740A3 publication Critical patent/WO2008016740A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the current invention relates to the field of semiconductor device manufacturing.
  • it relates to an interconnect structure having trenches and vias and processes of making the same.
  • interconnects or interconnect structures may be formed or created using well-known back end of line (BEOL) technologies.
  • BEOL back end of line
  • An interconnect may include for example trenches and/or vias, made of conductive and/or metal materials, and may be used to selectively connect a set of active devices to achieve a desired function or performance or a combination thereof.
  • two or more layers of interconnect structures may be formed together, creating an interconnect block, referred to herein as an interconnect unit.
  • an interconnect structure or a layer of interconnect structure may be formed by first creating one or more via openings in a layer of ILD materials.
  • the ILD layer may be formed or deposited, such as through a conventional CVD or MOCVD technique as well-known in the art, on a surface of a prior level of interconnect layer or interconnect structure.
  • one or more trench openings may be created in the same ILD layer, in regions or areas where at least one or more of the via openings have been created. The trench openings may therefore overlap at least partially with the via openings.
  • a layer of liner which may be a metal liner, may be deposited onto the bottom and/or to the sidewalls of the opening in the ILD layer.
  • the liner may be deposited to reduce and/or prevent possible diffusion of a conductive material, which fills up the via and trench opening in a follow-up step, into the ILD material for example during the manufacturing of the interconnect structure. Such diffusion of conductive metal materials into the ILD layer may cause device shortage and performance degradation, among others.
  • the metal liner may be deposited with a thickness that is sufficient to provide a relatively good coverage for the via openings.
  • the metal liner in the trench region which is deposited at the same time as that in the via region and thus having a thickness being dictated by the thickness of the metal liner deposited in the via region, may be unnecessarily thicker than it needs to be because a trench usually requires less liner coverage, as is known in the art. Consequently, a thicker metal liner in the trench region, coupled with a relatively low conductivity of the liner material, may cause an overall high resistance of the metal line formed later in the trench region.
  • the conventional process of forming interconnect structures may cause trenches or metal lines to have roughened trench bottoms.
  • the roughness at the bottom of trench is known, as described below in detail, to be caused by performing via gouging before applying the metal liner to the via and trench openings. This roughness becomes particularly severe when a layer of ultra-low dielectric k-constant (ULK) material is used as the ILD layer.
  • ULK ultra-low dielectric k-constant
  • FIGS. 1-5 are illustrations of a conventional process and/or method of forming an interconnect unit and/or an interconnect structure
  • FIGS. 6-11 are illustrations of a dual liner interconnect structure and/or interconnect unit and a process of making the same according to one embodiment of the invention.
  • Embodiments of the present invention provide a method of forming an interconnect structure in a layer of inter-layer dielectric (ILD) material.
  • One embodiment of the method teaches creating one or more via openings in the layer of ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering at least one of the one or more trenching openings and at least part of the first liner.
  • the method further teaches filling the via openings and trench openings with a conductive material; and planarizing the conductive material to be coplanar with a top surface of the layer of ILD material to form the interconnect structure, wherein the via openings are covered by the first and second liners and the trench openings are covered by the second liner.
  • the method teaches a step of, before forming the first liner, gouging the via openings to create a gouge at a bottom of the via openings in a conductive area of a prior level interconnect structure, wherein the gouging comprises ion- sputtering the bottom of the via openings to create the gouge suitable for the deposition of the first liner.
  • forming the first and/or second liner includes depositing a layer of metal lining material onto the via openings.
  • the metal lining material may be selected from the group of Ta, TaN, Ti, TiN, W, WN and Ru.
  • the layer of metal lining material has a thickness ranging from 1 metallic monolayer to tens of monolayers, and preferably between 1 and 5 monolayers.
  • creating the one or more via openings includes forming a photo-mask pattern representing a top view of the via openings and applying wet-etching to copy the pattern into the ILD material to produce the via openings.
  • creating the one or more trench openings includes forming a photo-mask pattern representing a top view of the trench openings and applying wet-etching to copy the pattern partially into the ILD material overlapping the via openings to produce the trench openings.
  • Embodiments of the present invention also provide an interconnect structure in a semiconductor chip for connecting one or more semiconductor devices.
  • the interconnect structure includes one or more vias; one or more trenches formed on top of at least one of the one or more vias; a first liner lining perimeters of at least one of the one or more vias; and a second liner lining perimeters of the one or more trenches and the first liner.
  • the first and/or second liners include Ta, TaN, Ti, TiN, W, WN and Ru materials.
  • Embodiments of the present invention further provide an interconnect structure, with tailored liner thicknesses at trench and via, serves to enhance the structural integrity of the via for reliability and reduce the parasitic electrical degradation through a more improved liner coverage, whilst optimizing conductivity performance of the trench.
  • a conventional BEOL processing may include following well-known operations or steps such as, for example, dielectric barrier (“cap”) deposition, ILD deposition, hard-mask or photo-mask deposition, lithography, wet etching or dry etching, and deposition, among others.
  • dielectric barrier (“cap") deposition ILD deposition
  • hard-mask or photo-mask deposition lithography
  • wet etching or dry etching and deposition
  • FIGS. 1-5 are schematic illustrations of a conventional process and/or method of forming an interconnect unit and/or an interconnect structure.
  • FIG. 1 illustrates that an interconnect structure 20 may be formed on top of a prior level of interconnect structure 10.
  • a dielectric barrier layer 21 may be formed or deposited directly on top of interconnect structure 10, upon which a layer of inter-level dielectric (ILD) material 22 may be subsequently formed.
  • ILD inter-level dielectric
  • Via openings 23 may or may not be etched down into dielectric barrier layer 21.
  • Interconnect structure 10 which may also be referred to as an interconnect layer or metal layer 10, may include one or more metal trenches and/or vias 14 embedded in a prior level of ILD layer 12.
  • Dielectric barrier layer 21 may be formed or deposited on top of prior interconnect layer 10 to enable adequate over-etch of ILD layer 22 and provide process tolerance due to variations. According to one conventional process, dielectric barrier layer 21 provides protection for the metal structure, for example Cu structure of prior interconnect layer 10, from destructive device processing environments, such as resist removal, and possible surface diffusion by processing chemicals into the metal structure causing reliability issues of the structure. Therefore, dielectric barrier layer 21 may not be etched through and the etching process may need to be controlled adequately.
  • FIG. 2 illustrates that after the creation, via openings 23 may be filled with certain types of planarizing materials such as, for example, an anti-reflection coating (ARC) material 32.
  • ARC material 32 may fill up via openings 23 and may cover the top surface of ILD layer 22.
  • resist poisoning may occur at this stage as is common in advanced integration construction. Resist poisoning occurs due to unfavorable interaction between dielectric structures, such as via openings 23, and resist material, such as ARC material 32. Resist poisoning may interfere with proper development of features of resist material 32 and shall be avoid if possible.
  • a top surface of ARC material 32 may be planarized either during application or using post-processing techniques.
  • the planarization may include, but not limited to, spin- on program optimization, thermal reflow, or chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • a photo-mask 34 may subsequently be formed using techniques such as, for example, a lithographic technique or other conventional techniques that may be known in the art.
  • the pattern of photo-mask 34 representing a desired and/or pre-determined shape of trenches, may be copied down or transferred to ILD layer 22, as illustrated in FIG. 3, by using techniques such as, for example, a reactive ion etching (RIE) technique.
  • RIE reactive ion etching
  • the etching of trench pattern may stop at a pre-determined depth, which is less deep than that of via openings 23, thus to form one or more trench openings 25 on top of via openings 23.
  • ARC material 32 remaining in via openings 23 may be removed or stripped off, using well-known wet-etching or other techniques, to expose dielectric barrier layer 21 at the bottom of via openings 23 (FIG. 1).
  • Dielectric barrier layer 21 at the bottom of via openings 23 is then removed by one of conventional etching processes, to expose metal element of trenches and/or vias 14 in the prior level of interconnect structure 10.
  • FIG. 5 illustrates that after the formation of liner 30, a conductive metal material 24 is filled in the via and trench openings according to the conventional process.
  • Conductive metal material 24 may be separated or isolated from ILD layer 22 of, for example, porous ULK material by liner 30.
  • a planarizing process such as a CMP process, for example, may follow to produce a flat top surface 26 of interconnect layer or interconnect structure 20.
  • the liner 30 is designed to have a sufficient thickness in order to provide good coverage for the via openings 23.
  • the thickness of liner 30 in the trench openings, deposited during the same process and therefore being dictated by the thickness in the via openings 23, may in general not be suitable or tailored for the trench openings 25.
  • liner 30 at the sidewalls of trench openings 25 may be thicker than required and therefore may result in increase in overall resistance of the trench which includes conductive metal material 24 and liner 30.
  • Liner 30 may be a metal liner.
  • the roughness 32 at trench bottom 25 may cause device performance degradation such as, for example, increased resistance and possible shortage with neighboring active devices. In severe cases, this may cause limitation in the possible depth of trenches that may be formed.
  • a method or process is provided to create an interconnect layer or structure having dual liners of different thickness respectively for the trenches and for the vias.
  • a method or process is provided to create an interconnect structure having via gouging at the bottom of vias but not at the bottom of trenches.
  • FIGS. 6-11 are illustrations of a dual liner interconnect structure and/or interconnect unit and a process of making the same according to one embodiment of the invention.
  • dielectric barrier layer 41 may be formed or deposited on top of a prior level interconnect layer 10.
  • Dielectric barrier layer 41 may include materials such as, for example, SiN, SiNCH or other suitable Si- and/or N-containing materials.
  • FIG. 6 further illustrates the formation of an interconnect structure 40 on top of prior level interconnect layer 10 via dielectric barrier layer 41 by depositing an inter-level dielectric (ILD) layer 42 on top of dielectric barrier layer 41.
  • ILD inter-level dielectric
  • One or more via openings 43 may be subsequently created or formed through for example etching in ILD layer 42.
  • Via openings 43 may be etched down into, and through, dielectric barrier layer 41.
  • dielectric barrier layer 41 may be removed at this stage (in contrary to a conventional process as shown in FIG. 2) without causing reliability and/or damage to the metallic structure 14 of prior level interconnect layer or metal layer 10, as described below in detail with reference to FIG. 7.
  • Prior level of metal layer 10 may include one or more trenches and/or vias 14, made of a metal or metal element such as copper (Cu) or other suitable conductive materials. Trenches and/or vias 14 are embedded in ILD layer 12.
  • FIG. 7 illustrates that after their creation, a layer of lining material or a liner 50 may be deposited onto via openings 43 at the bottom and sidewalls, and on the top of interconnect structure 40.
  • Liner 50 may be a metal liner and may include materials such as Ta, TaN, Ti, TiN, W, WN and Ru.
  • the thickness of liner 50 may range from 1 metallic monolayer to tens of monolayers and preferably between 1 and 5 monolayers. However, the invention is not limited in this respect and other thicknesses may be used depending on factors such as, for example, the material of liner 50. Multiple layers of the aforementioned lining materials may be combined to form a multi-layer composite barrier structure for better performance.
  • the application of metal liner 50 enables the removal of dielectric barrier layer 41 at this stage (FIG. 6) without causing possible reliability and/or damage to metal structure 14 and avoiding resist poisoning in a subsequent process step.
  • via gouging may be performed to mitigate stresses at the bottom of via openings 43 to improve adhesiveness of metal liner 50 to metal element 14 of prior level of interconnect layer 10.
  • via gouging is performed prior to the creation of trench openings 55 (FIG. 9)
  • roughness at the bottom of trenches caused by via gouging as those shown in FIG. 4 may be avoided.
  • metal liner 50 is deposited prior to the filling of via openings 43 with resist material 52 (FIG.
  • metal liner 50 prevents resist material 52 from getting direct contact with dielectric materials (41 and 42) and metal element 14, thus prevents potential negative and/or unfavorable interaction of dielectric materials (41 and 42) and metal element 14 with the resist materials, as that in a conventional process shown in FIG. 2.
  • FIG. 8 illustrates that, after being covered by liner 50, via openings 43 may be subsequently filled with a material 52 suitable for planarization.
  • Material 52 may include, but not limited to, OPL (organic planarizing layer), IPL (inorganic planarizing layer), ARC (anti-reflection coating) or combinations thereof.
  • a top surface of material 52 may then be planarized, and on the planarized top surface of material 52, a photo-mask 54 may be developed using a conventional lithographic technique as may be known in the art.
  • the trench pattern may be copied down into ILD layer 42, as illustrated in FIG. 9, through a process known as line-level etching and using one or more conventional methods such as, for example, a reactive ion etching (RIE) method.
  • RIE reactive ion etching
  • a combination of multiple techniques may be used such as a concerted etching process, which may be non-selective, to open the ARC, metallic liner and ILD materials. Or selective processes which would first open the ARC and followed by a metal etch chemistry to remove the metallic liner in the lithographically defined pattern area may be used.
  • the etching may be fluorine rich to prevent possible metal residues.
  • a separate dielectric etch process which may stops at a pre-determined or desired depth less deep than that of via openings 43, may be employed to form one or more trench openings 55 on top of via openings 43.
  • a combination of selective and non-selective etch processes may be applied to control the extent of recess of ARC material 52 in the via region to ensure metallic liner 50 at the bottom of the via is preserved.
  • Trench openings 55 may be created or formed on top of at least one via opening 43, have a width that may be approximately the same as the diameter of underneath via opening 43, and align vertically, at least on one side, with via opening 43.
  • trench openings 55 may have different widths from via openings 43, and in addition may not be in vertical alignment with via openings 43 as shown in FIG. 9.
  • via openings 43 may have shapes other than those resembling a cylinder.
  • photo-mask 54 remaining at the top surface of ILD layer 42 and ARC material 52 remaining in via openings 43 may be removed by applying techniques, as may be well- known in the art, for example, a wet-etching technique.
  • a second layer of liner 51 may be applied or deposited onto the exposed sidewalls of trench openings 55 and on top of first layer of liner 50 inside via openings 43 as shown in FIG. 10.
  • Liner 51 may be a metal liner and may include materials such as Ta, TaN, Ti, TiN, W, WN and Ru.
  • thickness of liner 51 may be independently adjusted.
  • thickness of liner 51 may be optimized to achieve a relative low, and possibly, minimum resistance.
  • the thickness of liner 51 may range from 1 metallic monolayer to tens of monolayers, and preferably between 1 and 5 monolayers but the invention is not limited in this respect and other thickness may be used depend on factors including, but not limited to, the material of liner 51. Multiple layers of the aforementioned liner materials may be combined to form a multi-layer composite barrier structure for optimal performance.
  • via and trench openings 43 and 55 may be filled with a metal material, such as copper (Cu), gold (Au), silver (Ag), tungsten (W) and alloys and/or compounds, as shown in FIG. 11, thereof suitable for interconnecting active devices.
  • the filling of openings 43 and 55 may be through plating or seeding, forming interconnect metal line 44.
  • a top surface of the metal material filling via and trench openings 43 and 55 may be planarized to be coplanar with the top surface of interconnect structure 40 through, for example, a CMP process.
  • the resulting flat surface 46 may be suitable for subsequent device processing such as the manufacturing of a next level interconnect layer.
  • An additional advantage provided by this invention is that the multiple metallic liner depositions may be tailored to provide a thicker liner in the field.
  • a thicker liner provides a wider process window during Cu CMP as described above. For example, during a two step Cu CMP polish, the process may be designed to stop on the field liner or liner 50 (FIG. 10).
  • the thicker field liner 50 enables more aggressive Cu polishing without compromising integrity of the dielectric material below. Otherwise, a lack of selectivity between the Cu polish step and the liner may contribute to the cause of non-planarity.
  • the thicker liner provided by this invention can lead to improved planarity.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering the trenching openings and at least part of the first liner. An interconnect structure formed by the method is also provided.

Description

INTERCONNECT STRUCTURE AND PROCESS OF MAKING
THE SAME
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application claims the benefit of US patent application serial number 11/461137, entitled "Interconnect Structure and Process of Making the Same", filed July 31, 2006 with the United States Patent and Trademark Office, the content of which is incorporated herein by reference in its entirety.
FIELD OF THE INVENTION
[0002] The current invention relates to the field of semiconductor device manufacturing. In particular, it relates to an interconnect structure having trenches and vias and processes of making the same.
BACKGROUND OF THE INVENTION
[0003] In the field of semiconductor device manufacturing, active semiconductor devices such as, for example, transistors are normally manufactured by well-known front end of line (FEOL) technologies. Following the formation of active devices, interconnects or interconnect structures (as the terms may be used interchangeably throughout this application) may be formed or created using well-known back end of line (BEOL) technologies. An interconnect may include for example trenches and/or vias, made of conductive and/or metal materials, and may be used to selectively connect a set of active devices to achieve a desired function or performance or a combination thereof. In addition, two or more layers of interconnect structures may be formed together, creating an interconnect block, referred to herein as an interconnect unit.
[0004] Conventionally, an interconnect structure or a layer of interconnect structure may be formed by first creating one or more via openings in a layer of ILD materials. The ILD layer may be formed or deposited, such as through a conventional CVD or MOCVD technique as well-known in the art, on a surface of a prior level of interconnect layer or interconnect structure. Subsequently, one or more trench openings may be created in the same ILD layer, in regions or areas where at least one or more of the via openings have been created. The trench openings may therefore overlap at least partially with the via openings. Following the formation of the structure of via and trench openings but before filling of the opening with certain types of conductive materials, a layer of liner, which may be a metal liner, may be deposited onto the bottom and/or to the sidewalls of the opening in the ILD layer. As is well-known in the art, the liner may be deposited to reduce and/or prevent possible diffusion of a conductive material, which fills up the via and trench opening in a follow-up step, into the ILD material for example during the manufacturing of the interconnect structure. Such diffusion of conductive metal materials into the ILD layer may cause device shortage and performance degradation, among others.
[0005] Conventionally, the metal liner may be deposited with a thickness that is sufficient to provide a relatively good coverage for the via openings. However, the metal liner in the trench region, which is deposited at the same time as that in the via region and thus having a thickness being dictated by the thickness of the metal liner deposited in the via region, may be unnecessarily thicker than it needs to be because a trench usually requires less liner coverage, as is known in the art. Consequently, a thicker metal liner in the trench region, coupled with a relatively low conductivity of the liner material, may cause an overall high resistance of the metal line formed later in the trench region.
[0006] In addition to possible high resistance, it is also well-known in the art that the conventional process of forming interconnect structures, as described above, may cause trenches or metal lines to have roughened trench bottoms. The roughness at the bottom of trench is known, as described below in detail, to be caused by performing via gouging before applying the metal liner to the via and trench openings. This roughness becomes particularly severe when a layer of ultra-low dielectric k-constant (ULK) material is used as the ILD layer. A roughened trench bottom may result in device performance degradation such as, for example, increased resistance and possible shortage with neighboring active devices, and in severe cases may force the trench to be formed with less depth.
[0007] Therefore, there exists a need in the art to tailor the thickness of the liner used in the trench region and in the via region during the formation of the interconnect structure and so to achieve better device performance. There is also a need for the mitigation of roughness at the bottom of trenches caused by the above conventional process during formation of the interconnect structure.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The present invention will be understood and appreciated more fully from the following detailed description of the invention, taken in conjunction with the accompanying drawings of which:
[0009] FIGS. 1-5 are illustrations of a conventional process and/or method of forming an interconnect unit and/or an interconnect structure; and
[0010] FIGS. 6-11 are illustrations of a dual liner interconnect structure and/or interconnect unit and a process of making the same according to one embodiment of the invention.
[0011] It will be appreciated that for simplicity and clarity of illustration, elements shown in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for purpose of clarity.
SUMMARY OF THE INVENTION
[0012] Embodiments of the present invention provide a method of forming an interconnect structure in a layer of inter-layer dielectric (ILD) material. One embodiment of the method teaches creating one or more via openings in the layer of ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering at least one of the one or more trenching openings and at least part of the first liner. The method further teaches filling the via openings and trench openings with a conductive material; and planarizing the conductive material to be coplanar with a top surface of the layer of ILD material to form the interconnect structure, wherein the via openings are covered by the first and second liners and the trench openings are covered by the second liner.
[0013] According to one embodiment, the method teaches a step of, before forming the first liner, gouging the via openings to create a gouge at a bottom of the via openings in a conductive area of a prior level interconnect structure, wherein the gouging comprises ion- sputtering the bottom of the via openings to create the gouge suitable for the deposition of the first liner.
[0014] According to another embodiment, forming the first and/or second liner includes depositing a layer of metal lining material onto the via openings. The metal lining material may be selected from the group of Ta, TaN, Ti, TiN, W, WN and Ru. The layer of metal lining material has a thickness ranging from 1 metallic monolayer to tens of monolayers, and preferably between 1 and 5 monolayers.
[0015] According to yet another embodiment, creating the one or more via openings includes forming a photo-mask pattern representing a top view of the via openings and applying wet-etching to copy the pattern into the ILD material to produce the via openings. Similarly, creating the one or more trench openings includes forming a photo-mask pattern representing a top view of the trench openings and applying wet-etching to copy the pattern partially into the ILD material overlapping the via openings to produce the trench openings.
[0016] Embodiments of the present invention also provide an interconnect structure in a semiconductor chip for connecting one or more semiconductor devices. The interconnect structure includes one or more vias; one or more trenches formed on top of at least one of the one or more vias; a first liner lining perimeters of at least one of the one or more vias; and a second liner lining perimeters of the one or more trenches and the first liner. According to one embodiment, the first and/or second liners include Ta, TaN, Ti, TiN, W, WN and Ru materials.
[0017] Embodiments of the present invention further provide an interconnect structure, with tailored liner thicknesses at trench and via, serves to enhance the structural integrity of the via for reliability and reduce the parasitic electrical degradation through a more improved liner coverage, whilst optimizing conductivity performance of the trench.
DETAILED DESCRIPTION OF THE INVENTION
[0018] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the invention. However, it will be understood by those of ordinary skill in the art that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods and procedures have not been described in detail so as not to obscure the embodiments of the invention.
[0019] A conventional BEOL processing may include following well-known operations or steps such as, for example, dielectric barrier ("cap") deposition, ILD deposition, hard-mask or photo-mask deposition, lithography, wet etching or dry etching, and deposition, among others. However, for the interest of not obscuring the presentation of essences of the present invention, processing steps that are well known in the art may be combined together for presentation and/or for illustration, and in some instances may not be described in detail. A person skilled in the art will appreciate that the following descriptions have rather focused on the distinctive features and/or elements of the present invention.
[0020] FIGS. 1-5 are schematic illustrations of a conventional process and/or method of forming an interconnect unit and/or an interconnect structure. For example, FIG. 1 illustrates that an interconnect structure 20 may be formed on top of a prior level of interconnect structure 10. As is shown in FIG. 1, a dielectric barrier layer 21 may be formed or deposited directly on top of interconnect structure 10, upon which a layer of inter-level dielectric (ILD) material 22 may be subsequently formed. Next, one or more via openings 23 may be created or formed, through an etching process for example, in ILD layer 22. Via openings 23 may or may not be etched down into dielectric barrier layer 21. When via openings 23 are etched into dielectric barrier layer 21, they may not be etched through dielectric barrier layer 21 to cause exposure of trenches and/or vias 14 of prior interconnect structure 10. Interconnect structure 10, which may also be referred to as an interconnect layer or metal layer 10, may include one or more metal trenches and/or vias 14 embedded in a prior level of ILD layer 12.
[0021] Dielectric barrier layer 21 may be formed or deposited on top of prior interconnect layer 10 to enable adequate over-etch of ILD layer 22 and provide process tolerance due to variations. According to one conventional process, dielectric barrier layer 21 provides protection for the metal structure, for example Cu structure of prior interconnect layer 10, from destructive device processing environments, such as resist removal, and possible surface diffusion by processing chemicals into the metal structure causing reliability issues of the structure. Therefore, dielectric barrier layer 21 may not be etched through and the etching process may need to be controlled adequately.
[0022] FIG. 2 illustrates that after the creation, via openings 23 may be filled with certain types of planarizing materials such as, for example, an anti-reflection coating (ARC) material 32. ARC material 32 may fill up via openings 23 and may cover the top surface of ILD layer 22. As is well known in the art, resist poisoning may occur at this stage as is common in advanced integration construction. Resist poisoning occurs due to unfavorable interaction between dielectric structures, such as via openings 23, and resist material, such as ARC material 32. Resist poisoning may interfere with proper development of features of resist material 32 and shall be avoid if possible.
[0023] A top surface of ARC material 32 may be planarized either during application or using post-processing techniques. The planarization may include, but not limited to, spin- on program optimization, thermal reflow, or chemical mechanical polishing (CMP). On the planarized top surface of ARC material 32, a photo-mask 34 may subsequently be formed using techniques such as, for example, a lithographic technique or other conventional techniques that may be known in the art. Next to its formation, the pattern of photo-mask 34, representing a desired and/or pre-determined shape of trenches, may be copied down or transferred to ILD layer 22, as illustrated in FIG. 3, by using techniques such as, for example, a reactive ion etching (RIE) technique. The etching of trench pattern may stop at a pre-determined depth, which is less deep than that of via openings 23, thus to form one or more trench openings 25 on top of via openings 23. Following the formation of trench openings 25, ARC material 32 remaining in via openings 23 may be removed or stripped off, using well-known wet-etching or other techniques, to expose dielectric barrier layer 21 at the bottom of via openings 23 (FIG. 1). Dielectric barrier layer 21 at the bottom of via openings 23 is then removed by one of conventional etching processes, to expose metal element of trenches and/or vias 14 in the prior level of interconnect structure 10.
[0024] Conventionally, before depositing a liner 30 onto the exposed surface of trench openings 25 and via openings 23 as illustrated in FIG. 4, via gouging, such as ion sputtering, may be performed to mitigate stresses at the bottom of via openings 23 in order to improve adhesiveness of liner 30 to the metal element of trenches and/or vias 14 in prior interconnect layer 10. However, while it may improve the adhesiveness of liner 30 to the metal element, via gouging may roughen the bottom of trench 25 causing roughness 32. Roughness 32 becomes particularly severe when a porous ultra-low k-constant (ULK) material is used as ILD layer 22. As is well known in the art, porous ULK ILD is often used to reduce parasitic capacitance of interconnect structures and to enhance device performance which is often measured by the operational speed of the device.
[0025] FIG. 5 illustrates that after the formation of liner 30, a conductive metal material 24 is filled in the via and trench openings according to the conventional process. Conductive metal material 24 may be separated or isolated from ILD layer 22 of, for example, porous ULK material by liner 30. Following the deposition or fill-up of conductive metal material 24 in via and trench openings 23 and 25, a planarizing process such as a CMP process, for example, may follow to produce a flat top surface 26 of interconnect layer or interconnect structure 20.
[0026] According to the above conventional process, since the liner 30 is designed to have a sufficient thickness in order to provide good coverage for the via openings 23. The thickness of liner 30 in the trench openings, deposited during the same process and therefore being dictated by the thickness in the via openings 23, may in general not be suitable or tailored for the trench openings 25. For example liner 30 at the sidewalls of trench openings 25 may be thicker than required and therefore may result in increase in overall resistance of the trench which includes conductive metal material 24 and liner 30. Liner 30 may be a metal liner.
[0027] As is also shown in FIG. 5, the roughness 32 at trench bottom 25 may cause device performance degradation such as, for example, increased resistance and possible shortage with neighboring active devices. In severe cases, this may cause limitation in the possible depth of trenches that may be formed.
[0028] According to one embodiment of the invention, a method or process is provided to create an interconnect layer or structure having dual liners of different thickness respectively for the trenches and for the vias. According to another embodiment of the invention, a method or process is provided to create an interconnect structure having via gouging at the bottom of vias but not at the bottom of trenches.
[0029] FIGS. 6-11 are illustrations of a dual liner interconnect structure and/or interconnect unit and a process of making the same according to one embodiment of the invention. In FIG. 6, dielectric barrier layer 41 may be formed or deposited on top of a prior level interconnect layer 10. Dielectric barrier layer 41 may include materials such as, for example, SiN, SiNCH or other suitable Si- and/or N-containing materials. FIG. 6 further illustrates the formation of an interconnect structure 40 on top of prior level interconnect layer 10 via dielectric barrier layer 41 by depositing an inter-level dielectric (ILD) layer 42 on top of dielectric barrier layer 41. One or more via openings 43 may be subsequently created or formed through for example etching in ILD layer 42. Via openings 43 may be etched down into, and through, dielectric barrier layer 41. According to one embodiment of the invention, dielectric barrier layer 41 may be removed at this stage (in contrary to a conventional process as shown in FIG. 2) without causing reliability and/or damage to the metallic structure 14 of prior level interconnect layer or metal layer 10, as described below in detail with reference to FIG. 7. Prior level of metal layer 10 may include one or more trenches and/or vias 14, made of a metal or metal element such as copper (Cu) or other suitable conductive materials. Trenches and/or vias 14 are embedded in ILD layer 12.
[0030] FIG. 7 illustrates that after their creation, a layer of lining material or a liner 50 may be deposited onto via openings 43 at the bottom and sidewalls, and on the top of interconnect structure 40. Liner 50 may be a metal liner and may include materials such as Ta, TaN, Ti, TiN, W, WN and Ru. The thickness of liner 50 may range from 1 metallic monolayer to tens of monolayers and preferably between 1 and 5 monolayers. However, the invention is not limited in this respect and other thicknesses may be used depending on factors such as, for example, the material of liner 50. Multiple layers of the aforementioned lining materials may be combined to form a multi-layer composite barrier structure for better performance. According to one embodiment of the invention, by protecting the metal (e.g., Cu) structure 14 of prior metal layer or interconnect layer 10 and covering dielectric via opening structure 43 of ILD layer 42, the application of metal liner 50 enables the removal of dielectric barrier layer 41 at this stage (FIG. 6) without causing possible reliability and/or damage to metal structure 14 and avoiding resist poisoning in a subsequent process step.
[0031] Before the deposition of metal liner 50, via gouging may be performed to mitigate stresses at the bottom of via openings 43 to improve adhesiveness of metal liner 50 to metal element 14 of prior level of interconnect layer 10. According to one embodiment of the invention, because the via gouging is performed prior to the creation of trench openings 55 (FIG. 9), roughness at the bottom of trenches caused by via gouging as those shown in FIG. 4 may be avoided. According to another embodiment of the invention, because metal liner 50 is deposited prior to the filling of via openings 43 with resist material 52 (FIG. 8), metal liner 50 prevents resist material 52 from getting direct contact with dielectric materials (41 and 42) and metal element 14, thus prevents potential negative and/or unfavorable interaction of dielectric materials (41 and 42) and metal element 14 with the resist materials, as that in a conventional process shown in FIG. 2.
[0032] FIG. 8 illustrates that, after being covered by liner 50, via openings 43 may be subsequently filled with a material 52 suitable for planarization. Material 52 may include, but not limited to, OPL (organic planarizing layer), IPL (inorganic planarizing layer), ARC (anti-reflection coating) or combinations thereof. A top surface of material 52 may then be planarized, and on the planarized top surface of material 52, a photo-mask 54 may be developed using a conventional lithographic technique as may be known in the art.
[0033] Following forming photo-mask 54 representing a desirable and/or pre-determined pattern of trenches to be formed, the trench pattern may be copied down into ILD layer 42, as illustrated in FIG. 9, through a process known as line-level etching and using one or more conventional methods such as, for example, a reactive ion etching (RIE) method. A combination of multiple techniques may be used such as a concerted etching process, which may be non-selective, to open the ARC, metallic liner and ILD materials. Or selective processes which would first open the ARC and followed by a metal etch chemistry to remove the metallic liner in the lithographically defined pattern area may be used. The etching may be fluorine rich to prevent possible metal residues. Then a separate dielectric etch process, which may stops at a pre-determined or desired depth less deep than that of via openings 43, may be employed to form one or more trench openings 55 on top of via openings 43.
[0034] According to one embodiment of the invention, a combination of selective and non-selective etch processes may be applied to control the extent of recess of ARC material 52 in the via region to ensure metallic liner 50 at the bottom of the via is preserved. Trench openings 55 may be created or formed on top of at least one via opening 43, have a width that may be approximately the same as the diameter of underneath via opening 43, and align vertically, at least on one side, with via opening 43. However, a person skilled in the art will appreciate that the invention may not be limited in this respect and trench openings 55 may have different widths from via openings 43, and in addition may not be in vertical alignment with via openings 43 as shown in FIG. 9. Furthermore, via openings 43 may have shapes other than those resembling a cylinder. Following the formation of trench openings, photo-mask 54 remaining at the top surface of ILD layer 42 and ARC material 52 remaining in via openings 43 may be removed by applying techniques, as may be well- known in the art, for example, a wet-etching technique. a. Next, a second layer of liner 51 may be applied or deposited onto the exposed sidewalls of trench openings 55 and on top of first layer of liner 50 inside via openings 43 as shown in FIG. 10. Liner 51 may be a metal liner and may include materials such as Ta, TaN, Ti, TiN, W, WN and Ru. Because this deposition of liner 51 is mainly applied for covering trench openings 55 and therefore not being restricted by the thickness of liner 50 covering via openings 43, thickness of liner 51 may be independently adjusted. For example, thickness of liner 51 may be optimized to achieve a relative low, and possibly, minimum resistance. Typically, the thickness of liner 51 may range from 1 metallic monolayer to tens of monolayers, and preferably between 1 and 5 monolayers but the invention is not limited in this respect and other thickness may be used depend on factors including, but not limited to, the material of liner 51. Multiple layers of the aforementioned liner materials may be combined to form a multi-layer composite barrier structure for optimal performance.
[0035] Following the deposition of second layer of liner 51, via and trench openings 43 and 55 may be filled with a metal material, such as copper (Cu), gold (Au), silver (Ag), tungsten (W) and alloys and/or compounds, as shown in FIG. 11, thereof suitable for interconnecting active devices. The filling of openings 43 and 55 may be through plating or seeding, forming interconnect metal line 44. A top surface of the metal material filling via and trench openings 43 and 55 may be planarized to be coplanar with the top surface of interconnect structure 40 through, for example, a CMP process. The resulting flat surface 46 may be suitable for subsequent device processing such as the manufacturing of a next level interconnect layer.
[0036] An additional advantage provided by this invention is that the multiple metallic liner depositions may be tailored to provide a thicker liner in the field. A thicker liner provides a wider process window during Cu CMP as described above. For example, during a two step Cu CMP polish, the process may be designed to stop on the field liner or liner 50 (FIG. 10). The thicker field liner 50 enables more aggressive Cu polishing without compromising integrity of the dielectric material below. Otherwise, a lack of selectivity between the Cu polish step and the liner may contribute to the cause of non-planarity. The thicker liner provided by this invention can lead to improved planarity.
[0037] While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the spirit of the invention.

Claims

CLAIMSWhat is claimed is:
1. A method of forming an interconnect structure in a layer of inter-layer dielectric (ILD) material, the method comprising: creating one or more via openings (43) in said layer of ILD material (42); forming a first liner (50) covering at least one of said one or more via openings; creating one or more trench openings (55) on top of at least one of said one or more via openings covered by said first liner; and forming a second liner (51) covering at least one of said one or more trenching openings and at least part of said first liner.
2. The method of claim 1, further comprising: filling said via openings (43) and trench openings (55) with a conductive material (44); and planarizing said conductive material to be coplanar (46) with a top surface of said layer of ILD material (42) to form said interconnect structure, wherein said via openings are covered by said first and second liners and said trench openings are covered by said second liner.
3. The method of claim 1, wherein said conductive material is selected from the group of copper (Cu), gold (Au), silver (Ag), tungsten (W), or a combination thereof.
4. The method of claim 1, further comprising, before forming said first liner (50), gouging said via openings (43) to create a gouge at a bottom of said via openings in a conductive area (14) of a prior level interconnect structure (10).
5. The method of claim 4, wherein said gouging comprises ion-sputtering said bottom of said via openings (43) to create said gouge suitable for the deposition of said first liner (50).
6. The method of claim 1, wherein forming said first liner (50) comprises depositing a layer of metal lining material onto said via openings (43), said metal lining material being selected from the group of Ta, TaN, Ti, TiN, W, WN and Ru.
7. The method of claim 6, wherein said layer of metal lining material (50) has a thickness ranging from 1 metallic monolayer to tens of monolayers, and preferably between 1 and 5 monolayers.
8. The method of claim 1, wherein forming said second liner (51) comprises depositing a layer of metal lining material onto said via openings (43) and said trench openings (55), said metal lining material being selected from the group of Ta, TaN, Ti, TiN, W, WN and Ru.
9. The method of claim 8, wherein said layer of metal lining material (51) has a thickness ranging from 1 metallic monolayer to tens of monolayers, and preferably between 1 and 5 monolayers.
10. The method of claim 1, wherein creating said one or more via openings (43) comprises forming a photo-mask pattern representing a top view of said via openings and applying wet-etching to copy said pattern into said ILD material to produce said via openings.
11. The method of claim 1, wherein creating said one or more trench openings (55) comprises forming a photo-mask pattern representing a top view of said trench openings and applying wet-etching to copy said pattern partially into said ILD material overlapping said via openings to produce said trench openings.
12. A method of forming a multi-layer interconnect unit including at least a first (10) and a second (40) layer of interconnect structure, the method comprising: forming a layer of inter-layer dielectric (ILD) material (42) upon said first layer of interconnect structure (10); creating one or more via openings (43) in said layer of ILD material; forming a first liner (50) covering at least one of said one or more via openings; creating one or more trench openings (55) on top of at least one of said one or more via openings covered by said first liner; and forming a second liner (51) covering said trenching openings (55) and at least part of said first liner (51).
13. The method of claim 12, further comprising forming a dielectric barrier layer (41) before forming said layer of ILD material (42).
14. The method of claim 12, further comprising: plating a metal material (44) in said via openings (43) and trench openings (55) created in said layer of ILD material (42); and planarizing said metal material to be coplanar (46) with a top surface of said ILD material to form said second layer of interconnect structure (40), wherein said via openings are covered by said first (50) and second (51) liners and said trench openings (55) are covered by said second liner (51).
15. The method of claim 14, further comprising gouging said via openings (43) to expose a metal interconnect element (14) of said first interconnect layer of said interconnect (10) before forming said first liner (50).
16. The method of claim 15, wherein said gouging comprises ion-sputtering a bottom of said via openings (43) to prepare a gouge for the deposition of said first liner (50).
17. The method of claim 12, wherein forming said first liner comprises depositing a layer of metal lining material (50) onto said via openings (43), said metal lining material being selected from the group of Ta, TaN, Ti, TiN, W, WN and Ru.
18. The method of claim 17, wherein said layer of metal lining material (50) has a thickness ranging from 1 metallic monolayer to tens of monolayers, and preferably between 1 and 5 monolayers.
19. A method of forming an interconnect unit, the method comprising: forming a dielectric barrier layer (41) direct upon a first interconnect layer (10); forming a layer of inter-layer dielectric (ILD) material (42) on said dielectric barrier layer; creating one or more via openings (43) in said layer of ILD material; forming a first metallic liner (50) covering at least one of said one or more via openings; creating one or more trench openings (55) on top of at least one of said one or more via openings covered by said first metallic liner; and forming a second metallic liner (51) covering said trenching openings (55) and at least part of said first metallic liner (50).
20. The method of claim 19, further comprising: plating a metal material (44) in said via openings (43) and trench openings (55) created in said layer of ILD material (42); and planarizing a top surface of said ILD material plated with said metal material to form said second interconnect layer (40), wherein said via openings (43) are covered by said first (50) and second (51) liners and said trench openings (55) are covered by said second liner (51).
21. The method of claim 20, wherein said planarizing said top surface of said ILD material (42) comprises applying a chemical-mecanical-polish (CMP) process to made flat of said top surface (46).
22. The method of claim 19, further comprising gouging said via openings (43) to expose a metal interconnect element (14) of said first interconnect layer (10) of said interconnect before forming said first liner (50).
23. The method of claim 22, wherein said gouging comprises ion-sputtering a bottom of said via openings (43) to prepare a gouge for the deposition of said first liner (50).
24. The method of claim 19, wherein forming said first liner comprises depositing a layer of metal lining material (50) onto said via openings, said metal lining material being selected from the group of Ta, TaN, Ti, TiN, W, WN and Ru.
25. The method of claim 24, wherein said layer of metal lining material (50) has a thickness ranging from 1 metallic monolayer to tens of monolayers, and preferably between 1 and 5 monolayers.
26. An interconnect structure in a semiconductor chip for connecting one or more semiconductor devices, the interconnect structure comprising: one or more vias (43) formed in an inter-layer dielectric (ILD) material (42); one or more trenches (55) formed on top of at least one of said one or more vias; a first liner (50) lining perimeters of at least one of said one or more vias; and a second liner (51) lining perimeters of said one or more trenches and said first liner.
27. The interconnect structure of claim 26, further comprising a layer of dielectric barrier layer (41) between said ILD material (42) and a prior level interconnect structure (10).
28. The interconnect structure of claim 26, wherein said first liner (50) comprises Ta, TaN, Ti, TiN, W, WN and Ru materials.
29. The interconnect structure of claim 26, wherein said second liner (51) comprises Ta, TaN, Ti, TiN, W, WN and Ru material.
30. The interconnect structure of claim 26, wherein said one or more vias (43) have gouges formed into a conductive area (14) of an interconnect structure of a prior level (10).
PCT/US2007/069219 2006-07-31 2007-05-18 Interconnect structure and process of making the same WO2008016740A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2007800268526A CN101490827B (en) 2006-07-31 2007-05-18 Interconnect structure and process of making the same
KR1020097001301A KR101130557B1 (en) 2006-07-31 2007-05-18 Interconnect structure and process of making the same
EP07783916.5A EP2047506B1 (en) 2006-07-31 2007-05-18 Process for making an interconnect structure
JP2009522906A JP2009545889A (en) 2006-07-31 2007-05-18 Interconnect structure and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/461,137 US7488679B2 (en) 2006-07-31 2006-07-31 Interconnect structure and process of making the same
US11/461,137 2006-07-31

Publications (2)

Publication Number Publication Date
WO2008016740A2 true WO2008016740A2 (en) 2008-02-07
WO2008016740A3 WO2008016740A3 (en) 2008-06-26

Family

ID=38986848

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/069219 WO2008016740A2 (en) 2006-07-31 2007-05-18 Interconnect structure and process of making the same

Country Status (7)

Country Link
US (1) US7488679B2 (en)
EP (1) EP2047506B1 (en)
JP (1) JP2009545889A (en)
KR (1) KR101130557B1 (en)
CN (1) CN101490827B (en)
TW (1) TWI402937B (en)
WO (1) WO2008016740A2 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7955971B2 (en) * 2009-06-11 2011-06-07 International Business Machines Corporation Hybrid metallic wire and methods of fabricating same
US8232196B2 (en) * 2009-10-29 2012-07-31 International Business Machines Corporation Interconnect structure having a via with a via gouging feature and dielectric liner sidewalls for BEOL integration
US20110204517A1 (en) * 2010-02-23 2011-08-25 Qualcomm Incorporated Semiconductor Device with Vias Having More Than One Material
US8609534B2 (en) 2010-09-27 2013-12-17 International Business Machines Corporation Electrical fuse structure and method of fabricating same
US10199232B2 (en) 2011-02-24 2019-02-05 United Microelectronics Corporation Conductor line structure
US9418886B1 (en) * 2015-07-24 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming conductive features
US9373543B1 (en) * 2015-10-06 2016-06-21 Globalfoundries Inc. Forming interconnect features with reduced sidewall tapering
US10541204B2 (en) 2015-10-20 2020-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnection structure and method of forming the same
US9653345B1 (en) * 2016-01-07 2017-05-16 United Microelectronics Corp. Method of fabricating semiconductor structure with improved critical dimension control
US9953865B1 (en) 2016-10-26 2018-04-24 International Business Machines Corporation Structure and method to improve FAV RIE process margin and electromigration
US11264325B2 (en) * 2017-09-28 2022-03-01 Intel Corporation Interconnects having a portion without a liner material and related structures, devices, and methods
US11069562B1 (en) * 2020-01-15 2021-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. Passivation layer for integrated circuit structure and forming the same
US11876047B2 (en) * 2021-09-14 2024-01-16 International Business Machines Corporation Decoupled interconnect structures

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050112864A1 (en) 2003-11-21 2005-05-26 International Business Machines Corporation Back End Interconnect With a Shaped Interface
US20050245068A1 (en) 2003-06-23 2005-11-03 International Business Machines Corporation Dual damascene interconnect structures having different materials for line and via conductors

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001077195A (en) * 1999-09-07 2001-03-23 Sony Corp Semiconductor device
US6429119B1 (en) * 1999-09-27 2002-08-06 Taiwan Semiconductor Manufacturing Company Dual damascene process to reduce etch barrier thickness
JP2004023030A (en) * 2002-06-20 2004-01-22 Matsushita Electric Ind Co Ltd Method of manufacturing semiconductor device
JP2004342702A (en) * 2003-05-13 2004-12-02 Nec Electronics Corp Semiconductor device and method of manufacturing the same
JP4278481B2 (en) * 2003-10-23 2009-06-17 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
US20050263891A1 (en) * 2004-05-28 2005-12-01 Bih-Huey Lee Diffusion barrier for damascene structures
US7332428B2 (en) * 2005-02-28 2008-02-19 Infineon Technologies Ag Metal interconnect structure and method
US7727888B2 (en) * 2005-08-31 2010-06-01 International Business Machines Corporation Interconnect structure and method for forming the same
US20070202689A1 (en) * 2006-02-27 2007-08-30 Samsung Electronics Co., Ltd. Methods of forming copper vias with argon sputtering etching in dual damascene processes

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050245068A1 (en) 2003-06-23 2005-11-03 International Business Machines Corporation Dual damascene interconnect structures having different materials for line and via conductors
US20050112864A1 (en) 2003-11-21 2005-05-26 International Business Machines Corporation Back End Interconnect With a Shaped Interface

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2047506A4

Also Published As

Publication number Publication date
TWI402937B (en) 2013-07-21
WO2008016740A3 (en) 2008-06-26
EP2047506A2 (en) 2009-04-15
CN101490827A (en) 2009-07-22
CN101490827B (en) 2012-06-13
EP2047506A4 (en) 2012-04-25
EP2047506B1 (en) 2015-07-08
JP2009545889A (en) 2009-12-24
TW200822283A (en) 2008-05-16
KR101130557B1 (en) 2012-04-12
US7488679B2 (en) 2009-02-10
KR20090045198A (en) 2009-05-07
US20080026568A1 (en) 2008-01-31

Similar Documents

Publication Publication Date Title
US7488679B2 (en) Interconnect structure and process of making the same
US9269621B2 (en) Dual damascene dual alignment interconnect scheme
KR100640662B1 (en) Semiconductor device having a barrier metal spacer and method of fabricating the same
JP3887282B2 (en) Metal-insulator-metal capacitor and method for manufacturing semiconductor device having damascene wiring structure
US7544601B2 (en) Semiconductor device and a method for manufacturing the same
US20170110369A1 (en) Electronic device and method for producing same
US20020030280A1 (en) Semiconductor device having dual damascene line structure and method for fabricating the same
JP4231055B2 (en) Semiconductor device and manufacturing method thereof
KR100621630B1 (en) Damascene processs using metals of two kinds
US20090294921A1 (en) Semiconductor device comprising metal lines with a selectively formed dielectric cap layer
US6194307B1 (en) Elimination of copper line damages for damascene process
CN109887880B (en) Semiconductor connection structure and manufacturing method thereof
JP4110829B2 (en) Manufacturing method of semiconductor device
US6977216B2 (en) Method for forming metal wire in semiconductor device
KR100590205B1 (en) Interconnection Structure For Semiconductor Device And Method Of Forming The Same
US7662711B2 (en) Method of forming dual damascene pattern
JP2007081284A (en) Semiconductor device and its manufacturing method
KR100834283B1 (en) The making method of metal line
JP2000195951A (en) Manufacture of double damask structure in integrated circuit having multiple level mutually connected structures
US8048799B2 (en) Method for forming copper wiring in semiconductor device
KR100539221B1 (en) Method of manufacturing electrical interconnection for semiconductor device
KR100226786B1 (en) Method for forming metal interconnection layer of semiconductor device
KR100548527B1 (en) Method for forming interconnection
KR20070055910A (en) Method of forming a via contact structure using a dual damascene technique
JPH10242272A (en) Method of forming interconnection structure in semiconductor device

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200780026852.6

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07783916

Country of ref document: EP

Kind code of ref document: A2

WWE Wipo information: entry into national phase

Ref document number: 1020097001301

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2009522906

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 2007783916

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE

NENP Non-entry into the national phase

Ref country code: RU