WO2008010302A1

WO2008010302A1 - Plasma display apparatus and plasma display panel driving method

Info

Publication number: WO2008010302A1
Application number: PCT/JP2006/314937
Authority: WO
Inventors: Toyoshi Kawada; Takatoshi Akagi
Original assignee: Hitachi Plasma Display Limited
Priority date: 2006-07-21
Filing date: 2006-07-21
Publication date: 2008-01-24
Also published as: JPWO2008010302A1

Abstract

There is described a PDP apparatus wherein a PDP apparatus driving circuit, which uses a new driving mode in which both the address-driving and the sustain-driving are executed at the same time, can be configured as an IC. The plasma display apparatus comprises a plasma display panel of three-electrode AC surface discharge system; a first driver circuit that drives a plurality of first electrodes; a three-electrode driver circuit; and a control circuit that controls the driver circuits. The control circuit performs an address driving operation, while sequentially applying scan pulses to the plurality of first electrodes and to a second electrode by turns, and further executes both the address-driving operation and the sustain-driving operation at the same time for at least a part of the display lines.

Description

Technical field of driving a fine plasma display device and a plasma display panel

In particular, the present invention is a flat display device that has been widely used in recent years as a display device, and in particular, a driving circuit and a driving method for a plasma display device (PDP device) whose display is greatly enlarged. The new drive system that can improve various display performance and the plasma display device to which this is applied, especially the sub-frame system of the 3-electrode AC surface discharge plasma display panel (PDP). The present invention relates to a plasma display device and a driving method. Background art

Flat display devices using flat display panels are being replaced by conventional cathode ray tubes and are being put to practical use in a wide range from small to large. Especially in large fields, PDPs are being commercialized as the mainstream of diffusion by taking advantage of the characteristics of the principle composition.

In order to promote further widespread use in the future, it is desired to further improve display performance and other functions in addition to lowering the price of the device itself.

Furthermore, there is an increasing demand for reducing the impact on various environmental loads, including EMI, and further reduction is necessary for widespread use in general households in the future. Figure 1 shows a schematic cross-sectional view of a three-electrode AC surface discharge PDP panel, which has become widespread as a large-screen display device.

A three-electrode AC surface discharge PDP panel is composed of two glass substrates, a HIJ glass 15 and a back glass 11 前面 The front glass substrate 15 has a BUS electrode 1 as a sustain electrode. 7 and the transparent electrode 1 6 are equipped with a common sustain electrode (X electrode: X 1, X 2 X n) and scanning electrode (Y electrode: Y 1 Y 2 Y n). The electrode and Y electrode are arranged alternately.Bus electrode with body ϋ 18 formed on X electrode and Y electrode, and protective film 19 such as M 〇 is formed on dielectric layer 1 8 1 7 Yes has conductivity and functions to supplement the conductivity of the transparent electrode 16 6. The dielectric layer 8 functions to maintain discharge due to wall charges and is made of low melting point glass.

In addition, the back glass substrate has an electrode electrode (A 1 A 2 A m) 1 2 that is the father of the X electrode and the Y electrode. A dielectric layer 1 3 is placed on the electrode electrode 1 2. Formed,

A partition 14 is formed on the body 1 3 at a position corresponding to the gap of the airless electrode 1 2.

A phosphor layer RGB is formed between the spaces 14 so as to cover the dielectric layer 13 and the partition wall. This phosphor layer RGB corresponds to the three colors red. When the PDP is driven, ultraviolet light is generated by the discharge between the X and Y electrodes, and the phosphor layer RG

When the light is excited and emitted by ultraviolet rays, an image is displayed.

A discharge gas such as a mixed gas of neon and xenon is filled between the front glass 15 provided with the X electrode and the Y electrode and the rear glass provided with the address electrode. The space where the X electrode and Y electrode intersect with the address electrode constitutes one discharge cell (pixel). Figure 2 shows the overall configuration of this three-electrode AC surface discharge PDP device. In particular, it is a block diagram showing the main part of the drive circuit for the PDP panel 1 0 0. The drive circuit shown in FIG. 2 includes an address driver circuit 1 1 1, a scan driver circuit 1 1 2, a Y common driver circuit 1 1 3, an X common driver circuit 1 1 4, and a control circuit 1 1 5. The control circuit 1 15 includes a display data control unit 1 16, a scan driver control unit 1 1 7, and a common driver control unit 1 1 8. Further, the display data control unit 1 1 6 includes a frame memory 1 1 9.

The control circuit 1 1 5 generates a control signal for controlling panel driving in accordance with an externally input clock signal C L K, display data D, vertical synchronization signal V S Y N C, horizontal synchronization signal H S Y N C, and the like. Specifically, the display data control unit 1 1 6 receives the display data D and stores it in the frame memory 1 1 9, and an address corresponding to the display data D of the frame memory 1 1 9 in synchronization with the clock CLK. Generate a control signal. The address control signal is supplied to the address driver circuit 1 1 1. Further, the scan driver control unit 1 17 generates a scan driver control signal for controlling the scan driver circuit 1 1 2 in synchronization with the vertical synchronization signal V S Y N C and the horizontal synchronization signal H S Y N C. The common driver control unit 1 1 8 drives the Y common driver circuit 1 1 3 and the X common driver circuit 1 1 4 in synchronization with the vertical synchronization signal V S Y N C and the horizontal synchronization signal H S Y N C.

The address driver circuit 1 1 1 operates according to the address control signal from the display data control unit 1 1 6 and applies an address pulse corresponding to the display data to each address electrode A 1 to Am. To do. The scan driver circuit 1 1 2 operates according to the scan driver control signal from the scan driver control unit 1 1 7 and drives each of the scan electrodes (Y electrodes) Y 1 to Y n independently. The scan driver circuit 1 1 2 synchronizes with each scan electrode (Y electrode) Y 1 to Y n in sequence as the scan pulse is applied, The bus circuit 1 1 1 applies an address pulse to each of the address electrodes A 1 to Am to select a cell to be displayed and display each cell (pixel) 1 0 3 (lit) · Control hidden (not lit) (not selected)

The Y common driver circuit 1 1 3 applies a sustain pulse to Y electrodes Y 1 to Y n, and the X common H driver circuit 1 1 4 applies a sustain pulse to X electrodes X 1 to X n. By applying the sustain pulse, a sustain discharge is generated between the X electrode and the Y electrode in the cell selected as the display cell.

The address driver circuit 1 1 1 is composed of an address driver IC, and the scan driver circuit 1 1 2 is composed of a scan driver IC.

Figure 3 shows the basic drive waveforms applied to each electrode for image display as the operation of the drive circuit in Figure 2. The PDP drive period is the reset period, Each display pixel is initialized in the reset period, the pixel to be displayed (lighted) is selected in the next address period, and is selected in the last sustain period. By illuminating these pixels, a display with a predetermined brightness is performed.

First, during the reset period, the state of all display cells is determined by applying a reset pulse as shown to the Y electrodes Y1 to Yn and the common X electrodes X1 to Xn, which are scanning electrodes. Set all functions to the initial state. In other words, the cells that are displayed once or not displayed are initialized to the same state.

During the address period, the Y electrodes Y 1 to Y n are sequentially scanned one by one by sequentially applying one V y level scan pulse to the Y electrodes Y 1 to Y n as the scan electrodes. In synchronization with the application of the scanning pulse to the electrodes, the V a level key is applied to each of the address electrodes A 1 to Am. Select a pixel on each scan line by applying a dress pulse.

In the next sustain period, the common V s level (V s y, V s) is applied to all the scan electrodes Y 1 to Y n and the common X electrodes X 1 to X n.

By alternately applying a sustain pulse (sustain voltage pulse) of X), the pixel selected in the previous address period is caused to emit light, and display is performed at a predetermined luminance by continuous application of the sustain pulse.

It is also possible to display grayscale gradation by controlling the number of flashes by combining these basic operations of a series of drive waveforms.

Fig. 4 shows the gradation display power formula using the sub-frame method, which is currently used in the wide <.

Fig. 4 shows the case of displaying 10 to 24 shades of gray with 10 subframes. Each subframe has a reset period, an address period, and a sustain period as described above. It is made up of. In each subframe, for the reset period and address period, the number of sustain pulses for each subframe is changed for each subframe for the sustain period in which substantially the same drive is performed. Arbitrary gradation display is performed by combining sub-frames. There are various methods for assigning the number of sustain pulses for each of the 10 subframes of the, but in general, it corresponds to the power of a binary number, 2 0 = 1, 2 ¹ = 2, 2 ² = 4, ···, 2 ⁹ = δ 1 2 The number is selected so that a maximum of 10 to 24 gradations can be displayed by any combination of these.

As described above, in the conventional gradation display method using the subframe method,

In each subframe, the reset period and address period are time

,

By controlling the number of sustain pulses in a separate sustain period, any gray scale display is possible. In addition, although control is performed in time series with a clearly divided drive evening of address period and sustain period, it has a feature that it is relatively easy to control, but on the other hand, a series of time series drive There is a drawback that it is necessary to secure each time for each subframe, and the time of each subframe becomes long.

A series of subframe combinations is called a frame. One frame must be repeated at 60 Hz or more to prevent flickering of the display, so the time allowed for one frame is 1 6 Within 7 ms

. Due to such time constraints, if the subframe time is prolonged, the number of subframes is reduced, and there is a problem that a sufficient number of gradations cannot be obtained.

On the other hand, if priority is given to securing the number of subframes in order to secure the number of gradations, the time allotted for driving in the reset period, address period, and sustain period is not sufficient. As a result, there arises a problem that problems such as erroneous display are likely to occur due to poor operation margin and drive stability.

In addition, as described above, it is clearly divided into a plurality of drive periods, and different drive operations are performed in different drive periods, so that the required drive current amount varies greatly from drive period to drive period. This causes the problem that the amount of current required in the sustain period becomes extremely large compared to the amount of current required in the other periods, resulting in large fluctuations in current consumption.

If the current fluctuation component (ripple current) of the power supply is large, it is necessary to provide a control circuit such as a stabilization circuit that satisfies the maximum value (peak current) of the fluctuation component and a circuit material with a large capacity wiring system. Complicated, expensive and costly. Furthermore, since the peak current component increases, noise signal radiation from the drive circuit system increases, and circuit control is increased. There is also a problem that the malfunction is likely to occur and the influence of the electromagnetic energy on the surrounding environment is likely to increase.

In order to solve the above problems, the applicant has filed a Japanese patent application.

2 0 0 5 — 3 6 5 0 9 8 proposes a new gradation drive method that improves gradation display performance and panel drive characteristics.

5 to 7 are diagrams for explaining the basic principle configuration of the new method described in the above-mentioned prior application. Here, the case where the display line is 10 display lines from L1 to L10, and 1 frame is composed of 10 subframes as gradation display drive. As an example, Fig. 5 schematically illustrates the frame configuration, Fig. 6 schematically illustrates sub-frames SF1 to SF3, and Fig. 7 schematically illustrates drive evening in subframes SF9 and SF10. Show.

As shown in the frame configuration in Fig. 5, subframes S F 1 to S F 1 are allocated evenly to 1 frame 1 6 6 7 ms.

0 (1.66 7 m s) is provided.

As shown in Figs. 6 and 7, each subframe consists of three types of drive: R: reset drive, A: address drive, and S: sustain drive. Each subframe has its own drive type. Time controlled by mining T0 to T11.

First, the drive starts from the first subframe S F 1.

As shown in (A), R: Reset drive is performed for all display lines at the leading evening T 0, so that all display cells are in the initial state all at once. Set to, and continue to SF 2

The same applies to S F 1 0, and reset driving is performed at the same T O.

After reset driving, each display line is sequentially addressed.

(Scan) Opens the address and sustain period for the operation and sustain operation. Start.

In the address sustain period of S F 1, first, address driving is performed on L 1 at T 1, and then L 2 at T 2,

〜, T 10 advances the address drive at the same time as evening imaging progresses like L 10.

At this time, the feature of the operation of this new method is that at L 2, the L 2 add / less drive is performed, and at the same time, the sustain drive is performed in parallel with the L 1 which has been address driven first. There is. Similarly, at T 3,

L 3 Address drive is performed, and address drive is performed first.

This operation is repeated until exactly 1 0 by performing sustain drive in parallel with 1 and L 2.

At the last T 1 1, after the sustain drive is performed for all display lines including L 1 0 where the address drive was performed before this time, the add-less sustain period ends. To do.

With the end of the address-sustain period for SF 1 above, 10 sustain drives for L 1, 9 sustain drives for L 2, and 1 for L 1 0 This means that the sustain drive is performed a number of times, and the gradation drive is performed by a different number of sustain drives for each display line.

After the above S F 1, the process proceeds to the next S F 2, and a reset period and an address / sustain period are performed as shown in FIG. And, according to the feature in the operation of this new method, in this SF 2, the display line that starts address driving at the first timing T 1 is set to a display line different from SF 1. In the figure, address drive is started from L 2 adjacent to L 1.

Similarly, after the end of SF 2, the display line that has finished address driving is operated in parallel with the sustain driving. In this case, the number of times of free driving for each display line is different from that of SF 1, and different gradation display is possible.

In addition, as shown in (C) of Fig. 6, (A) and (B) of Fig. 6,

For each of the display lines after the end of one subframe, the display lines for address driving are sequentially changed for the subsequent SF 3,..., SF 0 in the same manner. This makes it possible to evenly distribute the number of sustain driving times of 0.

Also, by summing up all the number of maintenance driving times Ό (1 + 2 + 3 +

• ·-+ 1 0), it is possible to evenly distribute the number of maintenance driving from the minimum 1 to the maximum 5 5 to all the display lines. Enable gradation display

In SF 1 to SF 10 shown above, each timing is set to T 1 1, but by further increasing this, it is possible to increase the number of maintenance drives as appropriate. In that sense, it has a large degree of freedom for gradation expression.

In any case, with the new driving method described in the above-mentioned prior application, the sustain period can be substantially lengthened to increase the number of times of driving and the luminance can be increased. Since the time required is distributed, the drive circuit and electromagnetic radiation can be reduced.

Patent Document 1: Japanese Patent Laid-Open No. 2 0 3-3 2 9 2

The above prior application describes the configuration of the output stage of the scan driver circuit and the X electrode driver circuit as shown in FIG. 8 in order to realize the above driving method. It is necessary to independently apply the scan pulse V d and sustain pulse (sustain voltage pulse) GND and V s to the Y electrode, which is the scan electrode. As shown in Fig. 8, GND, one V d, G ND And V s It is necessary to provide a dry circuit consisting of 4 switches 2 2 1 2 2 4 for each Y electrode. In the configuration of Fig. 8, the Y electrode common reset voltage waveform generation circuit 2 0 A diode 2 2 7 for applying the voltage from 3 is provided.

In addition, the X electrode must be able to apply the sustain pulse GND and V s independently, and consists of two switches 2 2 5 and 2 2 6 that apply GND and V s as shown in Figure 8. It is necessary to provide a driver circuit for each X electrode. In the configuration of FIG. 8, a diode 2 2 8 for applying a voltage of X 5 electrode common reset voltage waveform generation circuit 205 is provided.

In the conventional PDP device shown in Fig. 2, the voltage applied to all Y electrodes simultaneously during the reset period, address period, and sustain period is

Since there are two types, the IC supplied driver circuit was used to switch the voltage supplied to the I C power terminal. In other words, the running driver circuit 1 1 2 was realized by a driver IC in which an output circuit is configured by two generally used push-pull type switches. Since the X electrode driver circuit shown in Fig. 8 only needs to apply two types of voltages at the same time, the driver I

Supply to C (Achievable by switching ¾ pressure.

However, in the Y electrode dry circuit shown in Fig. 8, it is necessary to apply three or more types of voltages to any one of the Y electrodes at the same time, and the general-purpose driver IC is used to supply the driver IC as described above. This cannot be achieved by switching the voltage. Therefore, for each Y electrode,

The driver circuit shown in Fig. 8 must be provided separately, and there is a problem that the circuit scale is very large and the cost is high.

The present invention solves the following problems, and the operation circuit of the new drive system PDP device described in the above-mentioned prior application is widely used. The purpose is to realize a structure that can be realized by dryino and IC.

In order to achieve the above object, the plasma display device of the present invention executes the address drive operation and the sustain drive operation in parallel, as in the above-mentioned prior application, and performs a scan pulse with the first electrode. Address-less drive operation is performed while alternately applying to the second electrode.

Here, the application of the scan pulse to the first electrode and the application of the sustain pulse to the second electrode are synchronized, and the application of the scan pulse to the second electrode and the application of the sustain pulse to the first electrode Since the two electrodes are only applied to the first and second electrodes at the same time, the driver circuit that drives the first and second electrodes is a general-purpose type. This can be realized by switching the voltage supplied to the high-potential side power supply terminal and low-potential side power supply terminal of the integrated driver circuit. Brief Description of Drawings

Figure 1 is a diagram showing the structure of a three-electrode surface AC surface discharge type PDP panel.

FIG. 2 is a diagram showing the overall configuration of the plasma display device. Figure 3 is a drive waveform diagram of the plasma display device.

FIG. 4 is a diagram showing a conventional ¾ example frame configuration and subframe configuration.

Figure o is a diagram for explaining the frame structure of the new drive system described in the previous application.

Fig. 6 is a diagram for explaining the subframe configuration of the new drive system described in the previous application.

Fig. 7 is a diagram for explaining the subframe configuration of the new drive system described in the previous application. Fig. 8 is a diagram showing the configuration of the drive circuit in the new drive system described in the previous application.

FIG. 9 is a diagram showing a configuration of the PDP device according to the first embodiment of the present invention. FIG. 10 is a diagram showing a configuration of the X and Y electrode dryino IC of the PDP device according to the first embodiment.

FIG. 11 is a diagram showing basic drive waveforms of the PDP apparatus of the first embodiment.

FIG. 12 is a diagram showing the configuration of the display frame of the PDP apparatus according to the first embodiment.

FIGS. 13A and 13B are diagrams showing drive waveforms of the subframe SF 1 of the PDP apparatus of the first embodiment.

FIGS. 14A and 14B are diagrams showing drive waveforms of the subframe SF 2 of the PDP apparatus according to the first embodiment.

FIGS. 15A and 15B are diagrams showing drive waveforms of subframe SF 10 of the PDP apparatus according to the first embodiment.

FIG. 16 is a diagram showing the configuration of the display frame of the PDP apparatus according to the second embodiment.

FIGS. 17A and 17B are diagrams showing drive waveforms of subframe SF1 of the PDP apparatus of the second embodiment.

FIG. 18 is a diagram showing the structure of the display frame of the PDP apparatus according to the third embodiment.

FIG. 19A and FIG. 19B are diagrams showing drive waveforms of the subframe SF 1 of the PDP apparatus of the third embodiment.

FIG. 20 is a diagram showing the configuration of the subframe SF 1 of the PDP apparatus according to the fourth embodiment.

Figure 21 shows the configuration of subframe SF 2 of the PDP device in the fourth embodiment. FIG.

FIG. 22 is a diagram showing basic drive waveforms of the PDP apparatus of the fifth embodiment.

FIGS. 23A and 23B are diagrams showing drive waveforms of subframe SF1 of the PDP apparatus of the fifth embodiment.

FIG. 24 is a diagram showing the configuration of the PDP apparatus according to the sixth embodiment. BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 9 is a diagram showing the overall configuration of the plasma display apparatus (PDP apparatus) of the first embodiment of the present invention. The plasma display panel (P D P) 100 used in the P D P apparatus of the first embodiment has the same configuration as the conventional panel shown in FIG.

As shown in Fig. 9, the PDP device consists of PDP 1 0 0, an address drain that applies a drive voltage to the address electrode (third electrode) of PDP 1 0 0, IC 1 1 1 and PDP Y electrode driver IC 3 0 1 for applying drive voltage to 1 0 0 Y electrode (second electrode), high potential side power supply terminal 3 0 2 and low potential side power supply terminal of Y electrode driver IC 3 0 1 Y 0 side drive voltage supply circuit 3 1 1 for supplying drive voltage to 3 0 3 and PDP 1

0 X electrode driver that applies drive voltage to the 0 electrode (first electrode)

1 C 3 2 1 and X electrode side drive voltage supply circuit 3 3 1 to supply drive voltage to high potential side power supply terminal 3 2 2 and low potential side power supply terminal 3 2 3 of X electrode dryino IC 3 2 1 Have

An address dryino IC 1 1 1 is a circuit in which a plurality of circuits for applying an address pulse to each address electrode are integrated, and may be composed of a plurality of ICs. Y electrode dry IC 3 0 1 and X electrode drain 'IC 3 2 1 are circuits for applying a scan pulse or sustain pulse for each electrode to the Y and X electrodes that are the scan and sustain electrodes. May be composed of a plurality of I c.

Y electrode side drive voltage supply circuit 3 1 1 is controlled by built-in switch elements S WY 1 and S WY 3 Ό Y electrode dryno, I C 3 0

The voltage supplied to the high potential side power supply terminal 30 0 2 is switched between the ground (G N D) and the sustain voltage V s, and the switch elements S WY 2 and S W

Y electrode driver I C 3 0 1 low potential side power supply pin controlled by Y 4

Switching the voltage supplied to 3 0 3 between the scan voltage of V d and GND

. The Y electrode side drive voltage supply circuit 3 1 1 has a Y electrode side reset voltage waveform generation circuit 3 1 2 that generates a reset voltage that rises like a ramp to be applied to the Y electrode during the reset period. Y electrode side reset 卜 Denso waveform generator circuit 3 1 2 The voltage generated in 2 through the low potential side power supply terminal 3 0 3

The connection position of the Y electrode reset voltage waveform generator circuit 3 1 2 supplied to the Y electrode dry IC 3 0 1 can also be the high potential side power supply terminal 3 0 2 as described later.

Similarly, the X electrode side drive voltage supply circuit 3 3 1 is controlled by the built-in switch elements S W X 1 and S WX 3.

The voltage supplied to the high potential side power supply terminal 3 2 2 of I C 3 2 1

GND) and the sustain voltage V s, and the voltage supplied to the low-potential-side power supply terminal 3 2 3 of the X electrode driver IC 3 2 1 is controlled by the switch elements S WX 2 and SWX 4 as the scan voltage ― Switch between V d and GND. The X electrode side drive voltage supply circuit 3 3 1 has a Y electrode side reset voltage waveform generation circuit 3 3 2 that generates a reset voltage that rises in a ramp shape to be applied to the Y electrode during the reset period. , X electrode side reset Voltage waveform generation circuit 3 3 2 The voltage generated by the low potential side power supply terminal 3 2 3 is supplied to the X electrode driver IC 3 2 1. Similarly, the connection position of the X electrode side reset voltage waveform generation circuit 3 3 2 can also be the high potential side power supply terminal 3 2 2. Y electrode dry IC, IC 3 0 1 and X electrode dry IC 3 2 1 have the same configuration, Y electrode side drive voltage supply circuit 3 11 and X electrode side drive voltage supply circuit 3 2 1 have the same configuration Have

The Y electrode dryino I C 3 0 1 and the X electrode driver I C 3 2 1 are composed of a dryino and I C as shown in FIG. As shown in the figure, this dry IC 3 51 is provided with a high-side switch element HSW and a mouth-side switch element LSW for each output circuit. The power supply terminals of the low-side switch elements LSW are connected in common and connected to the low-potential side power supply terminal. 3 5 3 pulled out.

Before each output circuit, a logic circuit that controls them includes a shift register 3 5 4, a latch circuit 3 5 5, a gate circuit 3 5 6 and a gate circuit 3 5 6 and a high-side switch. Between the H element 卜 SW, a level shift チ circuit 3 δ 7 is provided.

Fig. 11 shows an example of basic drive waveforms based on the above basic drive circuit configuration. Y H V and Y L V are the Υ electrode side driver I

The voltage applied to the high-potential side power supply terminal 3 0 2 and low-potential side power supply terminal 3 0 3 of C 3 0 1 is the X H V and X L V are the X electrode side driver, I C

The voltage applied to the 3 2 1 high side power supply terminal 3 2 2 and the low potential side power supply terminal 3 2 3 is shown. Note that here: reset voltage, scan

(Scan) Pulse, address pulse, and sustain (sustain) pulse are all ground potential (GND), and the voltage from GND indicates the intensity of the pulse, but the base voltage is set to GND. It is not limited and may vary from pulse to pulse. The reference voltage for each pulse is called the base voltage, and the base reset voltage, base scan voltage, base address voltage, and base voltage, respectively. This is called one sustain voltage.

First, in the first half of the first reset period, the Y electrode side reset voltage waveform generation circuit 3 1 2 is operated, and the low potential side power supply terminal 3 0 3 of the Y electrode side driver IC 3 0 1 is connected to the Y electrode side U Set voltage waveform V wy is applied. (At this time, Y electrode side drain) I C 3 0 1 high potential side power supply terminal

SW 0 and SWY 3 are turned off as soon as 3 0 2 becomes floating, and the high potential side power supply terminal 3 2 2 and low potential side power supply terminal 3 2 2 of the X electrode side driver IC 3 2 1 are grounded SWX to supply

1 and S W X 4 are turned on. Y electrode side reset voltage waveform V wy applies a reset voltage pulse that rises in a ramp and reaches the peak voltage to all Y electrodes via a low-side switch element and a diode built in SW At this time, SWY 2 and SWY 4 are naturally set to the off state.

Subsequently, the diode built in the low-side switch element LSW of the X-electrode side dry IC 3 2 1 is similarly operated by operating the X-electrode-side reset voltage waveform generating circuit 3 3 2 for the X-electrode side. Via

X electrode side reset voltage waveform rising to a ramp voltage and reaching peak voltage

Apply V w x to all X electrodes.

In FIG. 9, the reset voltage waveform generation circuit is

Although the configuration for connecting to the low potential side power supply terminals 3 0 3 and 3 2 3 side of the IC has been described, the present invention is not limited to this. Good. In this case, however, the high-side switch element HSW is turned on and the reset voltage waveform is applied to the panel via the high-side switch element HSW instead of via the built-in diode. Acts in the same way (not shown) Enters the address / sustain period and drives each electrode In the force diagram for applying the pulse, the vicinity of the timing T i is magnified. Address' Sustain period, YHV, YL

V, X H V and X L V force G N D, one V d, V s, G N D

, V s, GND, GND, and one V d can be switched for each timing T i.

For the display line L i, address drive is performed at the timing T i. S WX 2 is turned on to supply low potential side power supply terminal 3 2 3 with scan voltage of 1 V d, and S WX 1 is turned on and high potential side power supply terminal 3 2 2 is supplied with GND potential Then, turn on the low-side switch element LSW connected to the Xi electrode of the X electrode side dryno XIC 3 2 1. This makes the scan (scan) pulse (

— V d level) is applied.

Simultaneously with the application of this scan pulse (-V d level), an address pulse (V a level) is applied to the address electrode of the display cell that is selected (lit) on the display line to which the scan pulse is applied. As a result, an address discharge is generated in the selected display cell on the display electrode Li, and a wall charge is formed on the Y electrode of the display cell and the dielectric surface of the Y electrode. End driving.

Next, the force to shift the formed wall charge to the sustain emission state that inverts one after another. For this purpose, first, a sustain (sustain) pulse is applied to the X i electrode at the timing T i +1. .

In this operation, the SWX 3 of the X electrode side drive voltage supply circuit 3 3 1 is turned on and the sustain voltage (V s level) is applied to the high potential side power supply terminal 3 2 2 at the same time. By turning on the eight-side switch element HSW connected to the Xi electrode of 2 1 and turning on SWX4 and supplying the GND potential to the low potential side power supply terminal, X i Apply a sustain pulse (V s level) to the electrode. Then Y 1 at the next timing τ + 2

Apply a pulse (V s level), but

Rhino X I C + High-side switch and drive

It is possible to apply more.

The above operation is performed for each subsequent timing, and sustain pulses (V s level) are alternately applied between the Y i and X i electrodes, and the wall charges formed are maintained by reversing one after another. Continue to emit light. Next, for the display line L i +1, the force to drive the address drive at the timing Τ ί + 1, at this time, the display line that has been address-driven first. For L i, since the sustain pulse V s is applied to the X i electrode, the X electrode fr driver IC 3 2 1 and the X electrode side drive voltage supply circuit 3 3 1 have already been It is supposed to be used Side NYV tsu 1

> Scan pulse cannot be applied from the X electrode side

Therefore, a scanning pulse is applied from the electrode side at this timing T i +1. Therefore, Y electrode driver I C 3

0 1 Turn on the low-side switch element LSW and simultaneously turn on SW Υ 2 of the Y electrode side drive voltage supply circuit 31 to apply d to the low potential side power supply terminal 30 3 When SWY 1 is turned on and the GD potential is supplied to the high potential side power supply terminal, a running pulse (1 V d level) is applied to the selected Υ i + 1 pole.

In the same way, the address pulse is applied to the selected address electrode.

By applying (V a level), a wall charge is formed in the selected display cell on the display electrode L i +1, and the address driving is finished. In the same manner, a transition is made to a sustain emission state that inverts the formed wall charges. However, at the timing T i + 2, the previous display line L i For this reason, the Y electrode driver IC 3 0 1 and the Y electrode side drive voltage supply circuit 3 1 1 are in a state where a sustain pulse can be output. Thus, it is possible to apply a sustain pulse to the Y i +1 electrode by the same control at the same timing.

Hereinafter, at the timing T 1 +3, it is possible to apply a sustain pulse to the X 1 + 1 electrode as well as the X i electrode by the same control.

Thereafter, the switching control is performed in the same manner at each subsequent timing, so that a sustain pulse (V s level) is alternately applied between the Y i + 1 / X i + 1 electrodes, and the formed wall charges are reduced. Sustained light emission is continued by inverting it continuously.

In the PDP apparatus of the first embodiment, the display line L i + 1 is address-driven at the timing T i + 1 and, similarly, in the subsequent timing, Y i + 1 / X The sustain drive is alternately performed between the i + 1 electrodes. At this time, the address pulse (V a level) applied to the address electrode for L i + 1 is the sustain drive for the previously driven L i. Output at the same timing as the impulse (V s level), which may affect the previous L i sustain drive operation. Therefore, in the first embodiment, by setting both V a and V s to the same polarity (positive polarity), the addition of the electric field is avoided and the V a level is set higher than the V s level. To reduce the influence on the wall charge for sustain driving in the cell by reducing the electric field strength of the V a level in the cell by lowering it relatively (eg V a <l Z 3 V s). I have to.

FIG. 12 is a diagram showing the overall configuration of the display frame in the PDP device of the first embodiment. In the first embodiment, the 9 6 3 gradation table has a 10 sub-divided 10 sub-frame configuration for a 50 0 display line panel. It has a frame structure and a subframe structure that realize the above. FIGS. 13A and 13B together constitute one waveform diagram, and show the drive waveform in the first subframe SF 1 in the first embodiment. FIG. 14A and FIG. 14B together constitute one waveform diagram, and show the drive waveform in the first subframe SF 2 in the first embodiment. FIG. 15A and FIG. 15B together constitute one waveform diagram, and shows the drive waveform in the first subframe SF 10 in the first embodiment.

The 5 0 0 display line is also divided into 10 according to the number of subframes. In the first embodiment, all display lines are divided into 50 lines in common from the top as common drive lines, and the number of times of maintenance drive is the same for each common drive line. .

Thus, 1 frame time must be set to 16.667 m, and 1 subframe time is 1.667 m. This one sub-frame time is distributed to the reset period and address / sustain period, and the address / sustain period is the address drive for the O 0 0 display line and finally the address. The drive is distributed to the timing of τ 1 to T 5001 for one sustain drive for the display line that has been dressed.

In the first subframe SF 1, the first block to perform address drive is L 1 to L 50, and after L 5 0 address drive is performed at T 50, Sustain drive is performed for 50, but this time is up to T 50 1, so the maximum number of sustain drives is 4 5 1.

Next, address driving is performed. The block is L 5 1 L 1 0 0, and T

A force that can maintain up to 4 0 1 times after L 1 0 0 address drive at 1 0 0 is possible. Here, it is a multiple of a binary number that is relatively easy to control. There are 2 5 6 times selected

Even for subsequent blocks, the number of sustain drive times is a binary number It is shown for the case where the number is selected, 1 2 8, 6 4,.

After the above S F 1 is completed, the driving of S F 2 is started. In S F 2, after the reset driving, address driving is started from the second block L 5 1.

Therefore, the number of times of sustain drive is assigned to the second block 4 5 1 times, the third block force s' 2 5 6 times, ..., the first block force 1 time.

The following blocks are driven in the same manner, and the driving of one frame is completed at the last subframe SF10.

As described above, the force S of which the brightness of each SF is different for each group of 50 display lines, and each group has SF of the first brightness (the number of sustain pulses 4 5 1) SF with the number of luminances (number of sustain pulses 2 5 6), SF with the third luminance (number of sustain pulses 1 2 8), SF with the fourth luminance (number of sustain pulses 6 4), ■, 10th Can be combined up to SF (number of sustain pulses: 1), and 96 3 gray levels can be displayed.

In the PDP device of the first embodiment, the main drive circuit on the sustain electrode (YZX electrode) side has been conventionally used for general purposes by the drive circuit configuration described above and the control method of address drive and sustain drive. The push-pull output type simple driver IC can be configured, and this reduces the cost of the entire drive circuit.

In the configuration of the first embodiment, the withstand voltage required for the output circuit of the driver IC is the absolute value of the difference in potential level applied simultaneously to the high potential power supply terminal and the low potential power supply terminal. Since there are only two combinations of potential level and potential level applied at the same time, GND level and V d or V s level and GND level, This can be realized if there is a withstand voltage that guarantees the higher voltage level of the inspection voltage IV d I or the sustain voltage IV s I, and this also makes it possible to reduce the cost of the driving circuit. When the reset voltage waveform is applied, the driver IC is used in the floating state, so there is no problem with the withstand voltage, and there is no need to consider it.

Fig. 16 shows the overall configuration of the display frame in the PDP apparatus of the second embodiment of the present invention, and Fig. 17A and Fig. 17B together constitute one waveform diagram. The drive waveform in the first subframe SF1 in the example is shown. The PDP apparatus of the second embodiment has the same configuration as that of the first embodiment except for the configuration of the display frame and the subframe. In the second embodiment, the same 500 0 display line as the first embodiment is used. For the panel, a 10 sub-frame configuration with 10 divisions is used, but a frame configuration and sub-frame configuration capable of expressing 10 24 gradations.

The drive division configuration is the same as in the first embodiment, but the number of sustain drives for the first address drive is increased to 5 1 2 compared to 4 5 1 in the first embodiment. Is different.

In order to increase the number of sustain drives to 5 1 2 in this way, after the address drive for all display lines has been completed, the necessary number of timings are provided and the sustain drive is continued. Perform the action. Therefore, the number of timings in this case is 5 6 2 and up to T 5 6 2. Since the rest of the configuration is the same as that of the first embodiment, a description thereof will be omitted.

Fig. 18 shows the overall configuration of the display frame in the PDP device of the third embodiment of the present invention, and Fig. 19A and Fig. 19B together constitute one waveform diagram. The drive waveform in the first subframe SF 1 in the example is shown. The PDP apparatus of the third embodiment has the same configuration as that of the first and second embodiments except for the configuration of the display frame and subframe. Have a success.

In the third embodiment, a panel of 51.2 display lines is displayed in a 16-divided 16 subframe configuration with a 2048 gradation display.

The drive division configuration is divided into 16 for every 3 2 display lines in order from the top. Of these, 2 5 6 times of sustain drive from the first block to the 6th block, for the next 3 blocks 1 2 8 times of sustain drive, and the remaining 7 blocks are set to 6 4 to 1 as the number of sustain drives, which is a multiple of the binary number sequentially.

FIGS. 20 and 21 show the configurations of the subframes S F 1 and S F 2 of the PDP apparatus according to the fourth embodiment of the present invention, the resetting operation, the scanning operation, and the timing of the sustaining operation. The PDP apparatus of the fourth embodiment has the same configuration as that of the first embodiment except for the subframe configuration.

In the fourth embodiment, similar to the first embodiment, a 96-scale display is realized with a 10-divided 10 sub-frame configuration for a 50-00 display line panel. This is a case of a division configuration in which addressing is performed by skipping every 10 display lines, instead of dividing the drive division method into continuous block units.

Therefore, the first block driven by SF 1 is L 1, L 1 1, L 2 1,..., L 4 9 1, and the next block has advanced one line. L 2, L 1 2, L 2 2,..., L 4 9 2.

As described above, the fourth embodiment differs from the first embodiment only in the block configuration of the subframe, and the drive waveforms are the same.

Fig. 22 shows an example of the basic drive waveform of the PDP device of the fifth embodiment of the present invention. Fig. 23 A and Fig. 23 B together constitute one waveform diagram. The drive waveform in the first subframe SF 1 in the example is shown. The PDP apparatus of the fifth embodiment has the same configuration as that of the first embodiment except for the drive waveform. Therefore, in the fifth embodiment, the width of the sustain pulse is widened so that the phases of the Y electrode sustain pulse and the X electrode sustain pulse overlap each other. As a result, the sustain voltage is always applied between the Y and X electrodes during the sustain period, and the formed wall charge can be drawn to the Y or X electrode side. The effect of voltage application from the address electrode side can be made almost negligible.

FIG. 24 is a diagram showing the overall configuration of the PDP apparatus according to the sixth embodiment of the present invention. The PDP apparatus of the sixth embodiment is different from the first embodiment in that the arrangement of the Y electrode and X electrode of the panel 400 is arranged in the order of Y, X, X, Y, Y, X. The rest is the same as the first embodiment.

In the PDP devices of the first to fifth embodiments, the phase of the sustain pulse to be applied is different between the Xi electrode and the Y1 + 1 electrode between the adjacent display lines L i and 1 + 1, The charge / discharge power during that time is wasted. Therefore, in the sixth embodiment, the electrode arrangement of the panel 400 is changed so that the adjacent sustain electrodes are in the same phase so that the power consumption is reduced.

As described above, according to the present invention, as the driving circuit, driving method and driving apparatus of the plasma display panel, the address driving and the sustain driving can be performed at the same timing by a simple and low-cost driving circuit configuration. This makes it possible to perform in parallel, ensuring sufficient address drive and sustain periods, and improving gradation display performance, resulting in brighter, brighter and smoother images. Display is possible.

Claims

A plurality of first electrodes extending in a first direction, a plurality of second electrodes extending in the first direction and disposed adjacent to the first electrode, and the first direction A plurality of third electrodes extending in a second direction substantially perpendicular to the first electrode, and a plurality of display lines are formed by the plurality of first electrodes and the plurality of second electrodes of RIJ, Each display line is formed by the adjacent first electrode and the second electrode, and a display cell is formed corresponding to each intersection of the plurality of display lines and the plurality of third electrodes. A plasma display panel,

A first driver circuit for driving the plurality of first negative electrodes;

Surrounding

A second driver circuit for driving the plurality of second electrodes; a third driver circuit for driving the plurality of third electrodes; and an electrode connected to the third electrode for selecting the display cell. In order to maintain the discharge of the display cell, the force S is not applied to perform the address driving operation in which a dress pulse is applied and a scanning pulse is sequentially applied to the plurality of first or second electrodes. And a control circuit for controlling the first to third driver circuits so as to execute a sustain driving operation in which a sustain pulse is alternately applied to the first electrode and the second electrode adjacent to each other. Plasma display device

The control circuit performs an address driving operation while sequentially applying a scan pulse to the plurality of first electrodes and the second electrode alternately, and the address driving is performed on at least a part of the display lines. The plasma display is characterized in that the first to third driver circuits are controlled to execute the operation and the sustain drive operation in parallel.

2. The application of the scan pulse to the first electrode and the application of the sustain pulse to the second electrode are synchronized, and the application to the second electrode The plasma τ display device according to claim 1, wherein the application of the scanning pulse and the application of the sustain pulse to the first electrode are synchronized.

3. In the previous cidressless drive operation, the third electrode of the previous number

,

A display in which an address voltage corresponding to the address pulse is selectively applied to a cell to be displayed with an address voltage applied, and scanning is performed with a base scan voltage applied to the plurality of second electrodes. In the sustain drive operation, a sustain voltage corresponding to the sustain pulse is applied to one of the first or second electrodes by applying a scan pressure corresponding to the scan pulse to the first or second electrode of the line. And a base sustain voltage to the other

When a HU ed address voltage is applied to the third electrode and a HU gd scanning pressure is applied to the second electrode, a discharge is generated and a wall charge is formed,

In the display cell in which the wall charges are formed, when the sustain voltage is applied to one of the first and second electrodes of the Huel and the base sustain voltage is applied to the other, a discharge occurs,

,

Hi] address voltage and BU base address voltage are applied to the third electrode, and the sustain voltage is applied to one of the first and second electrodes.

,

2. The plasma display device according to claim 1, wherein each voltage is set such that no discharge occurs even when a base voltage is applied to the other and a base sustain voltage is applied to the other.

4. Each of the first and second driver circuits includes an eight-sided switch element connected between the first or second electrode and a high-potential side power supply terminal, and the first or second driver circuit. A multi-sided switch element connected between the first electrode and the low potential side power supply terminal, and a plurality of switch circuits,

A drive voltage supply circuit for supplying a predetermined drive voltage to the high potential side power supply terminal and the low potential side power supply terminal, respectively. The plasma display device according to claim 1.

o "

5. The plasma display device according to claim 4, wherein the plurality of switch circuits are ICs.

6. The first driver circuit and the second driver circuit selected by the drive voltage supply circuit supply the scan voltage corresponding to the scan pulse to the low-potential-side power supply terminal. 5. The plasma display device according to claim 4, wherein the scanning pulse is applied to the first and second electrodes selected by turning on a P-side switch element connected to the first and second electrodes.

7. The HIJ first and second driver circuits are configured to supply the selected first and second driver circuits with the drive voltage supply circuit supplying a sustain pulse voltage corresponding to the sustain pulse to the high potential side power supply terminal.

5. The plasma display apparatus according to claim 4, wherein the sustain pulse is applied to the first and second electrodes selected by turning on a high-side switch element connected to the second electrode.

8. The drive voltage supply circuit includes a reset voltage waveform generation circuit that generates a reset voltage waveform in which the voltage increases in a ramp shape, and the high-potential-side power supply terminal of the first and second driver circuits or the 5. The plasma display device m according to claim 4, wherein a reset voltage waveform is applied to the first and second electrodes by supplying the reset voltage waveform to a low potential side power supply terminal.

9.1 Display frame is composed of multiple subframes, and gradation display is performed by combining subframes that are lit.

HIJ's display line is divided into several groups.

In each sub-field, the order of a plurality of groups is determined, and a scanning pulse for selecting cells to be lit on the plurality of display lines in each dull loop selected according to the order is First and second Applied sequentially to the electrodes, at least in some groups, other

The application of the sustain pulse for lighting the selected cell to the first and second electrodes is performed while the scan pulse is applied in one group.

The plasma display apparatus according to claim 1, wherein the order of the plurality of groups is changed for each subframe within the one display frame.

A plurality of first electrodes extending in a first direction, and the first direction;

,

And a plurality of second electrodes arranged adjacent to the first electrode and fiU

A plurality of third electrodes extending in a second direction substantially perpendicular to the first direction, and a plurality of display lines are formed by the plurality of first electrodes and the plurality of second electrodes. And each display line is adjacent to the first line.

A method for driving a plasma display panel, wherein a display cell is formed by one electrode and the second electrode, and a display cell is formed corresponding to each intersection of the plurality of display lines and the plurality of third electrodes. Atsute

1 Display frame consists of multiple subframes, and gradation display is performed by combining subframes that are lit.

j Multiple display lines are divided into multiple groups.

In each subframe, the order of the plurality of groups is determined, and scanning pulses for selecting cells to be lit and lit are sequentially applied to the plurality of display lines in each group selected according to the order, and the number is small. In some groups, the application of the previous ΛΙ inspection pulse in other groups

,

A sustain pulse is applied to the first and second electrodes to light the selected cell while

Within the Hij d 1 display frame, change the order of multiple groups in iu for each subframe.

The scan pulse is alternately applied to the first electrode and the second electrode. For driving a plasma display panel