WO2008006279A1 - Serveur temporel et procédé destiné à améliorer la précision d'entrée du serveur temporel - Google Patents

Serveur temporel et procédé destiné à améliorer la précision d'entrée du serveur temporel Download PDF

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Publication number
WO2008006279A1
WO2008006279A1 PCT/CN2007/001779 CN2007001779W WO2008006279A1 WO 2008006279 A1 WO2008006279 A1 WO 2008006279A1 CN 2007001779 W CN2007001779 W CN 2007001779W WO 2008006279 A1 WO2008006279 A1 WO 2008006279A1
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WO
WIPO (PCT)
Prior art keywords
time
signal
server
time signal
delay
Prior art date
Application number
PCT/CN2007/001779
Other languages
English (en)
Chinese (zh)
Inventor
Qing Zhang
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Publication of WO2008006279A1 publication Critical patent/WO2008006279A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines

Definitions

  • the present invention relates to the field of time synchronization technologies, and in particular, to a time server and a method for improving the output accuracy of a time server.
  • the charging system used in the communication network can reduce the error of the charging information and provide the basis for inter-network settlement between different operators.
  • the final time source for time synchronization is the global satellite positioning system (such as GPS, Global Positioning System). After obtaining the standard time from the time source, the time information needs to be sent to various devices requiring time synchronization through the inter-office/intra-office time allocation link. on.
  • time signal formats commonly used: time code format and Network Time Protocol (NTP) format.
  • the time code format is further divided into a range time group B format (Inter Range Instrumentation Group-B, IRIG-B), a DC level shift code format (DC Level Shift, DCLS), and a serial port ASCII (American Standard Code for Information). Interchange, American Standard Code for Information Interchange), and other string formats.
  • range time group B format Inter Range Instrumentation Group-B, IRIG-B
  • DC level shift code format DC Level Shift, DCLS
  • ASCII American Standard Code for Information
  • Serial communication ports such as RS232/RS422 (hereinafter referred to as serial ports), through which the time signal is encoded in ASCII code string, the baud rate is generally 9600bps.
  • serial ports RS232/RS422
  • the RS232/RS422 serial communication port has been widely used in various devices, so it is especially important to ensure the output precision of the time server serial port ASCII string.
  • FIG. 1 is a schematic structural diagram of an existing time server.
  • the time receiver 11 of the time server receives the satellite information or the IRIG time information and outputs the time signal after processing, and the controller 12 (such as the CPU) writes the time signal acquired from the time receiver 11 to the serial port chip 13 to form a TTL battery.
  • the flat time string is finally converted to a ASCII time string in RS232 or RS422 format by level shifter 14.
  • level shifter 14 level shifter 14.
  • the time signal obtained needs to be written into the serial port chip 13 by the controller 12, so that it takes a certain time for the controller 12 to process the time signal, and the time delay for the controller 12 to write the serial port chip 13 is not fixed.
  • the embodiment of the invention provides a time server and a method for improving the output precision of the time server, which can improve the output precision of the time server.
  • An embodiment of the present invention provides a time server, including: a time receiver, configured to receive time information of a time source, and output an absolute time signal and a time code after processing; a delay controller, configured to perform a predicted transmission delay Performing delay compensation on the absolute time signal from the time receiver to form a third time signal; a time generator for using the time code from the time receiver and the third time from the delay controller The signal synthesis is converted to a fourth time signal of the specified time output format and transmitted out.
  • the embodiment of the invention further provides a method for improving the output precision of a time server, comprising: receiving time information of a time source, and outputting an absolute time signal and a time code after processing; and pairing the absolute time signal according to a predicted transmission delay Performing delay compensation, outputting a third time signal; synthesizing the time code and the third time signal into a fourth time signal of a specified time output format, and transmitting to the receiver of the time signal output by the time server.
  • the time server first performs delay compensation on the absolute time signal output by the time server according to the predicted transmission delay before outputting the time signal, and then time code and compensation.
  • the subsequent absolute time signal synthesis is converted to a time signal of the specified output format for output. Therefore, although the time server has a transmission delay in the process of transmitting its output time signal to the receiver, since the time server has already performed delay compensation based on this before the time signal is output, when the time signal arrives at the receiver Basically equivalent to no delay. It can be seen that with the time server solution of the embodiment of the present invention, the time precision of the time signal output by the time server is greatly improved.
  • FIG. 1 is a schematic structural diagram of a time server in the prior art
  • FIG. 2 is a schematic structural diagram of an embodiment of a time server according to the present invention.
  • FIG. 3 is a flow chart of an embodiment of a method for improving output accuracy of a time server according to the present invention
  • FIG. 4 is a code flow diagram formed by time information of a time server serial port in the embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of an embodiment of a time server according to the present invention.
  • the time server of the embodiment of the present invention includes a time receiver 21, a delay controller 22, a serial port time generator 23 (a type of time generator), and a level shifter 24.
  • the time receiver, the delay controller and the serial port time generator are implemented in a logic device, and the logic device can adopt a programmable logic device (EPLD, Erasable).
  • EPLD programmable logic device
  • the logic device logically uses the 1PPS (pulse per second) signal input by the satellite or the 1PPS signal decoded by the IRIG-B to trigger the transmission time.
  • 1PPS pulse per second
  • the delay of the logic device is within 10ns, and the accuracy of the addition of the two is only 110ns. Therefore, the serial port time signal processed by the logic device can improve the serial port time of the device. The accuracy of the signal.
  • the time receiver 21 is responsible for receiving the time information of the time source (satellite positioning system or IRIG-B), and processing the absolute time signal 1PPS (1 pulse per second) and the serial port time code (one of the time codes). 1PPS pulse time and Universal Coordinated Time (Universal Coordinated Time,
  • the second synchronization error does not exceed ⁇ . ⁇ , and the time information included in the serial port time code is used to indicate the UCT time (year, month, day, hour, minute, second) corresponding to the 1PPS pulse time.
  • the delay controller 22 is responsible for delay compensation of the input absolute time signal 1PPS.
  • the serial port time signal output by the time server 22 is generally transmitted through the transmission cable to the device due to the transmission cable.
  • the existence of the time signal has a certain delay to the device, and different cables have different delays when transmitting signals of different rates. Since the transmission delay of a fixed cable at a serial port baud rate is proportional to the length of the transmission cable, different output delays can be compensated differently.
  • the input of the delay controller is the absolute time signal 1PPS, and the output is the 1PPS signal generated after the compensation. The difference between the two before and after compensation is:
  • the compensated 1PPS signal advances before the rising edge of the 1PPS signal before compensation, and the distance moved forward The transmission delay for compensation.
  • the serial time generator 23 is responsible for generating the serial time signal.
  • the serial port time generator 23 synthesizes the received high-accuracy 1PPS signal compensated by the delay controller 22 and the accurate specific time information time code acquired from the time receiver 21 into a time code stream having a serial port format. Guarantee the accuracy of the time of transmission.
  • the serial port format includes: the baud rate of the serial port, the number of bits of the data bits, the presence or absence of parity, and the number of stop bits.
  • the level shifter 24 is responsible for converting the serial time signal received from the serial time generator 23 to generate a standard serial time signal.
  • the level shifter uses a TTL (Transistor-Transistor Logic) or LVTTL (Low Voltage TTL) to RS232 level conversion device, since a common logic device output has a common level of 3.3V (LVTTL logic).
  • the level defined operating voltage range is 3.0 - 3.6V) or 5V (the TTL logic level is 5V), and the different serial port signals are 12V serial level signals, so sometimes conversion is required, ie 3.3V or 5V
  • the TTL level is converted to the standard serial port level of RS232.
  • the time receiver, the delay controller, the serial port time generator and the level shifter in the above time server can also be implemented in an ASIC (Application Specific Integrated Circuit), the specific implementation principle and in the logic device. The implementation is the same, so I won't go into details here.
  • ASIC Application Specific Integrated Circuit
  • serial port time generator 23 in the time server of the foregoing embodiment may be replaced by other types of time generators according to actual needs, and the implementation principle is basically the same, and only the output of the converted time signal is synthesized.
  • the format has changed.
  • the output time signal format is the serial port format; if other types of time generators are used, the output time signal format can be other types of formats, such as IRIG- B format.
  • the significance of the level shifter 24 is that: the time signal of the specified output format (such as the serial port format) output by the time generator is converted into a time signal of the standard specified output format so that the subsequent transmission requirements can be met. Therefore, if the time generator 23 outputs the time of the specified output format The signal can already meet the subsequent transmission requirements, that is, it is not necessary to convert to the standard mode, and the time converter 24 can also be disposed in the time server, and the specified output format time signal generated by the time generator 23 can be directly transmitted.
  • the time signal of the specified output format such as the serial port format
  • the transmission line between the time server and the time signal receiver (such as the device that needs time synchronization) outputted by the time server may be a transmission cable (ie, a wired transmission method), and may also be a wireless transmission line (ie, a wireless transmission method),
  • the embodiment of the present invention is also applicable to the wireless transmission mode.
  • the delay controller 22 performs the delay compensation based on the length of the wireless transmission line.
  • Step 310 The time server (specifically, the time receiver 21) receives the time source signal, and obtains a standard absolute time signal 1PPS (t0) and a serial port time code (t-code) after processing.
  • t0 a standard absolute time signal
  • t-code serial port time code
  • Step 320 The time server (specifically, the delay controller 22) compensates the 1PPS signal (t0) according to the predicted transmission delay, and outputs the compensated 1PPS signal (tl) (the third time signal).
  • Step 330 The time server (specifically, the serial port time generator 23) converts the compensated 1PPS signal (tl) and the time code (t-code) to generate a serial port time signal (t2) (fourth time signal).
  • Step 340 The time server (specifically, the level shifter 24) passes the serial port time signal (t2) to level-convert to generate a standard serial port time signal (tout), and then outputs the signal to the receiver (if time synchronization is required) Device), the serial port time signal (tout) is tm in the figure when it is transmitted to the receiving device through the transmission cable. Since the transmission line has a certain delay, but the time delay of the time server before the output time signal is compensated, the time signal (tout) output by the time server reaches the absolute time of the time signal (tm) after the device and the standard 1PPS signal (t0) The rising edge of the ) is aligned.
  • the time server before the time server outputs the time signal, the time server first performs delay compensation on the absolute time signal output by the time receiver according to the predicted transmission delay, and then the time code and the compensated The absolute time signal synthesis is converted to a time signal of the specified output format for output. Therefore, although the time server has a transmission delay in the process of transmitting its output time signal to the receiver, since the time server has already performed delay compensation based on this before the time signal is output, when the time signal arrives at the receiver Basically, there is no delay. It can be seen that the time precision of the time signal output by the time server is greatly improved.
  • each device in the time server is implemented by using a logic device or an ASIC device, the processing delay is small, and the output precision of the time server is further improved.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

L'invention concerne un serveur temporel et un procédé destiné à améliorer la précision d'entrée du serveur temporel. Le serveur temporel comprend: un récepteur temporel (21), utilisé pour recevoir des informations temporelles provenant d'une source temporelle, et la sortie du signal d'un moment absolu et le code temporel après traitement; un dispositif de commande (22) de retard temporel, utilisé pour compenser le retard temporel pour le signal du moment absolu à partir du récepteur temporel selon le retard temporel de transmission prévisionnel, de manière à former un troisième signal temporel; un générateur temporel utilisé pour associer le code temporel à partir du récepteur temporel et le troisième signal temporel à partir du dispositif de commande de retard temporel; et leur conversion en un quatrième signal temporel dans un format de sortie temporel désigné, puis leur retransmission.
PCT/CN2007/001779 2006-07-03 2007-06-05 Serveur temporel et procédé destiné à améliorer la précision d'entrée du serveur temporel WO2008006279A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN2006100614846A CN1913422B (zh) 2006-07-03 2006-07-03 时间服务器以及提高时间服务器输出精度的方法
CN200610061484.6 2006-07-03

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WO2008006279A1 true WO2008006279A1 (fr) 2008-01-17

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WO (1) WO2008006279A1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8752579B2 (en) * 2007-05-22 2014-06-17 Rjc Products Llc Check valve for fluid injector
US9813173B2 (en) * 2014-10-06 2017-11-07 Schweitzer Engineering Laboratories, Inc. Time signal verification and distribution
CN104954092A (zh) * 2015-06-29 2015-09-30 中国人民解放军63698部队 自适应时延补偿终端

Citations (4)

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Publication number Priority date Publication date Assignee Title
CN1283924A (zh) * 1993-05-13 2001-02-14 Rca.汤姆森许可公司 用于对压缩的视频信号接受系统进行同步的装置和方法
US20010033602A1 (en) * 2000-04-10 2001-10-25 Seiji Okubo Delay lock loop, receiver, and spectrum spreading communication system
JP2006166257A (ja) * 2004-12-09 2006-06-22 Nippon Telegr & Teleph Corp <Ntt> タイミング同期回路
CN1794655A (zh) * 2005-12-22 2006-06-28 中山大学 一种数字家庭网络的时间同步装置及同步方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2684241Y (zh) * 2003-09-17 2005-03-09 中国科学院寒区旱区环境与工程研究所 全球定位系统同步亚微秒高精度时钟

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1283924A (zh) * 1993-05-13 2001-02-14 Rca.汤姆森许可公司 用于对压缩的视频信号接受系统进行同步的装置和方法
US20010033602A1 (en) * 2000-04-10 2001-10-25 Seiji Okubo Delay lock loop, receiver, and spectrum spreading communication system
JP2006166257A (ja) * 2004-12-09 2006-06-22 Nippon Telegr & Teleph Corp <Ntt> タイミング同期回路
CN1794655A (zh) * 2005-12-22 2006-06-28 中山大学 一种数字家庭网络的时间同步装置及同步方法

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CN1913422B (zh) 2011-03-30

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