WO2008004271A1

WO2008004271A1 - Plasma display device

Info

Publication number: WO2008004271A1
Application number: PCT/JP2006/313232
Authority: WO
Inventors: Yoshikazu Kanazawa; Shigetoshi Tomio; Ken Kumakura
Original assignee: Hitachi Plasma Display Limited
Priority date: 2006-07-03
Filing date: 2006-07-03
Publication date: 2008-01-10
Also published as: JPWO2008004271A1

Abstract

A subject technology is to realize cost reduction or the like by taking measures for a tendency to increase address electrodes and address drivers in a PDP device. The PDP (10) in this PDP device is provided with three kinds of address electrodes (13r, 13g, 13b) corresponding to roles for selection of three kind of RGB colors, wherein the address electrodes (13r, 13b) for two kinds of colors (R and B, for example) are connected with first address drivers (132) for individual driving and address electrodes (13g) for one color (G, for example) are connected with a second address driver (140) for common driving.

Description

Specification

Plasma display device

Technical field

TECHNICAL FIELD [0001] The present invention relates to a method for driving a plasma display panel (PDP) and a display device (plasma display device: PDP device).

A PDP device is expected as a display device that can realize full-color and large-screen display from advantages such as display area, display capacity, and response. Currently, as a direct-view display device, a large screen of 40 to 60 inches or more, which cannot be realized by other devices, has been realized.

[0003] In a conventional PDP device, the ON / OFF state of a cell can be controlled by individually applying a pulse (address pulse) to the address electrode (address drive circuit) force PDP address electrode group. The address operation to be selected is performed. In a full-color (RGB) format PDP device in which a pixel is composed of a set of R (red), G (green), and B (blue) cells, the address driver has three times the number of addresses for the pixel. A circuit is needed. Disclosure of the invention

Problems to be solved by the invention

[0004] In recent years, display devices including a PDP device have become increasingly high definition, and a so-called HD compatible display device having a horizontal number of 1920 and a vertical direction of 1080 has appeared. In this case, in the full color (RGB) PDP device, the number of address electrodes is three times that of 1920 in the horizontal direction (5760), and an address driver corresponding to that is required. In addition, when the number of lines in the vertical direction is 1080, a system in which the address electrodes are simultaneously driven in a configuration in which the upper and lower addresses are divided is used. In that case, the number of required address drivers is further doubled. Thus, the increase in the number of address electrodes and address drivers is a major factor in increasing the cost of the PDP device.

[0005] The present invention has been made in view of the above problems, and the object of the present invention is to a PDP device. Oh! Thus, it is an object of the present invention to provide a technology capable of coping with the increasing trend of address electrodes and address drivers and realizing cost reduction.

Means for solving the problem

[0006] Outline of representative ones of the inventions disclosed in the present application will be briefly described as follows. In order to achieve the above object, the present invention is a technique of a PDP device including a PDP and a circuit unit for driving and controlling the PDP, and includes the following technical means.

[0007] First, the PDP includes, for example, a sustain electrode (first electrode), a scan electrode (second electrode), and an address electrode (third electrode). The circuit unit has, for example, a drive circuit corresponding to the above-described various electrode (first to third electrodes) groups. PDP is a format in which a pixel is composed of a set of cells of three different colors (first color, second color, and third color), and a group (group) of third electrodes of the type corresponding to each color. Have That is, as the third electrode, the first type, second type, and third type electrodes corresponding to the cells of each color are provided. For example, PDP is a format in which a pixel is composed of a set of cells of three kinds of colors R (red), G (green), and B (blue), and a group of address electrodes corresponding to each color ( As a group, there are R, G, B address electrodes (Ar, Ag, Ab) corresponding to cells of each color (R cell, G cell, B cell).

Conventionally, individual drive circuits are required for all address electrodes of the PDP. In this PDP device, among the address drivers, the individual address electrode drive circuit (first drive circuit) is the same as the conventional one of the three types of electrodes (R, G, B address electrodes) according to the color. Provided only for two types of electrodes (type 1 and type 2). The remaining one type of electrode (third type electrode) is connected to the common drive circuit (common address driver) of the electrode group, and thereby drives a plurality of third type electrodes in common. The configuration is as follows. That is, the circuit section includes first and second type drive circuits (first address drivers) and third type electrode groups that individually drive the first and second type electrode groups. A common driving circuit (second address driver). The individual driving of the first and second type electrode groups can be combined into one driver as in the conventional case. As in the past, one type of address driver is divided into a plurality of substrates and ICs (semiconductor integrated circuit devices). The PDP driving method is as follows, for example, in the drive control of the display area and period of the PDP. In the multiple third electrodes (address electrodes), the first and second type electrodes (eg, R and B address electrodes) are placed next to the third type electrode (eg, G address electrode). In this configuration, by controlling the voltage applied to the first and second type electrodes on both sides, the address operation for the third type electrode between them is realized. The SF period has a period and operation such as reset, address, and sustain.

[0010] In the address period, first, in the first period, the operation of address discharge for the cells corresponding to the individual first and second type electrodes (first and second type cells) Implement. That is, a data memory for selecting ON / OFF states of cell lighting by applying an address pulse to the third electrode (first type and second type electrode) and applying a scan pulse to the second electrode (scan electrode). Perform the operation. Subsequently, in the second period, an address discharge operation is performed on the cells (third type cells) corresponding to the common third type electrodes. At that time, the first and second type cells (electrodes) adjacent to both sides of the third type cell (electrode) to be turned ON are simultaneously turned ON (predetermined voltage is applied). As a result, the electric field in the third type cell to be turned ON between the first type and second type cells (electrodes) adjacent to each other is turned on, and the address in the third type cell is changed. Discharge occurs.

The invention's effect

[0011] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. According to the present invention, in the PDP device, it is possible to realize cost reduction or the like by coping with the increasing trend of address electrodes and address drivers. In particular, the number or scale of necessary address drivers can be reduced to about two-thirds of the conventional one, which can greatly contribute to the cost reduction of the device.

Brief Description of Drawings

FIG. 1 is a diagram showing an overall configuration of a PDP device in an embodiment of the present invention.

FIG. 2 is a diagram showing an example of the structure of a PDP in the PDP device according to one embodiment of the present invention.

FIG. 3 shows the connection between the PDP electrode and the drive circuit in the PDP device according to the embodiment of the present invention. It is a figure which shows the example of a structure of a continuation.

FIG. 4 is a diagram showing a configuration example of connection between an address electrode and an address drive circuit in the PDP device according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a state relating to a discharge in a cell in a first address period in the PDP device according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a state related to discharge in a cell in a second address period in the PDP device according to the first embodiment of the present invention.

FIG. 7 is a diagram showing a configuration example of a drive sequence for PDP display control in the PDP device according to the first embodiment of the present invention.

FIG. 8 is a diagram showing a configuration example of a PDP drive waveform in the PDP device according to the first embodiment of the present invention.

FIG. 9 is a diagram showing a PDP structure (first example) in the PDP device according to the second embodiment of the present invention.

FIG. 10 shows a PDP structure (second example) in the PDP device according to the second embodiment of the present invention.

FIG. 11 is a diagram showing a configuration example of a drive sequence for PDP display control in the PDP device according to the third embodiment of the present invention.

FIG. 12 is a diagram showing a configuration example of connection between a PDP electrode and a drive circuit in the PDP device according to the fourth embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

[0014] (Embodiment 1)

The PDP device according to the first embodiment will be described with reference to FIGS. In Embodiment 1, the address electrode group corresponding to G in RGB is connected to a common address driver and driven in common, and voltage application to the R and B address electrodes and cells on both sides is controlled. In the meantime, address operation of G address electrode and cell is realized. [0015] <PDP device>

First, the basic configuration of the PDP apparatus of this embodiment will be described. In FIG. 1, the present PDP device (PDP module) 100 mainly includes a PDP 10 and a chassis 190 that holds the PDP 10 and includes a circuit unit and the like. The circuit portion mainly includes various drive circuits, a control circuit 191, a signal processing circuit 192, a power supply circuit 193, and the like. The drive circuit includes an X drive circuit (X sustain driver) 111 for driving the X electrode (sustain electrode) 11, a Y drive circuit (Y sustain drive) 121 for driving the Y electrode (sustain scan electrode) 12, and a scan drive. A circuit (scan driver) 122 and an address drive circuit (address driver) 132 for driving the address electrode 13 are provided. The control circuit 191 controls the whole including each drive circuit. The signal processing circuit 191 performs signal processing on data information input to the control circuit. The power circuit 193 supplies power to each part.

[0016] Further, an X relay board 112 is connected to the X drive circuit 111, and the X electrode 11 passes from the X relay board 112 through a connecting portion such as an FPCB (flexible printed circuit board Z flexible cable) 113. Connected to a group. Further, a scan driver 122 is connected to the Y drive circuit 121, and is connected to the Y electrode 11 group from the scan driver 122 through a connection portion such as an FPCB 123. The plurality of address drivers 132 are connected to the original address relay board 131, and are connected from the address driver 132 to the group of address electrodes 13 through a connecting portion such as an FPCB. Circuits such as each driver are mounted on an IC board.

[0017] <PDP>

Next, referring to FIG. 2, a configuration example of the PDP 10 (AC type, surface discharge, (X, Υ, A) three electrodes, XY row sequential arrangement, and striped rib configuration) will be described. The PDP 10 is configured by combining a front part 201 that is mainly a structure on the front substrate 1 side made of glass and a back part 202 that is a structure on the rear substrate 2 side. In a three-electrode structure, the PDP 10 has an X electrode (sustain electrode) 11 as a first electrode, a Y electrode (scan electrode) 12 as a second electrode, and an address electrode 13 as a third electrode.

[0018] In the front part 201, a plurality of X electrodes 11 and Y electrodes 12, which are electrodes (display electrodes) for performing repeated display discharge, are arranged on the front substrate 1 in a first direction (predetermined intervals). Sideways Extending in parallel with the second direction (vertical direction). These display electrode groups (11, 12) are covered with the first dielectric layer 16, and the surface facing the discharge space of the first dielectric layer 16 is covered with a protective layer 17 such as MgO. It has been broken. The display electrodes (11, 12) are each composed of, for example, a linear metal bus electrode and a transparent electrode that is electrically connected to the bus electrode and forms a discharge gap between adjacent electrodes.

[0019] In the back surface 201, a plurality of metal address electrodes 13 {13r, 13g, 13b} are extended on the back substrate 2 in parallel to a second direction substantially orthogonal to the display electrodes (11, 12). Are arranged. The address electrodes 13r, 13g, 13b correspond to the respective colors (R, G, B). Further, the group of address electrodes 13 is covered with a second dielectric layer 18. On the second dielectric layer 18 and on both sides of the address electrode 13, partition walls (vertical ribs) 14 extending in the second direction are arranged to divide cells in the column direction of the display area. Furthermore, the top surface of the second dielectric layer 18 on the address electrode 13 and the side surface of the partition wall 14 are excited by ultraviolet rays to generate red (R), green (G), and blue (B) visible light. The bodies 15 {15r, 15g, 15b} are applied separately for each row.

[0020] The front part 201 and the rear part 202 are bonded together so that the protective layer 17 and the upper surface of the partition wall 14 are in contact with each other, and a mixed gas such as Ne—Xe for discharge is sealed in the discharge space between them. PDP10 force S is composed. In this structure, the driver side force also generates a discharge by applying a voltage higher than the discharge start voltage between the electrodes (11, 12, 13), and the phosphors of each color 15 {15r, 15g , 15b} are excited and emitted to display.

A row (display line) is formed by a set of the X electrode 11 and the Y electrode 12, and a cell (display cell) is formed corresponding to a region intersected with the address electrode 13 and separated by the partition wall 14. X—This is a normal configuration in which rows by Y are arranged in sequence. A pixel consists of a set of R, G, and B cells.

[0022] There are various types of structures of the PDP 10 according to the force drive method indicating the normal configuration in this example, and various types are applicable as long as the conditions regarding the address electrode 13 and the like as shown in the present embodiment are satisfied. Applicable.

[0023] <Electrode and driver> Next, referring to FIG. 3, the connection configuration between various electrode groups of the PDP 10 and each driver will be described. The X drive circuit 111 connects and drives the X electrodes 11 of the PDP 10 in common. The Y drive circuit (Y sustain driver) 121 and the scan driver (scan drive circuit) 122 connect and drive the Y electrode 12 group. The Y drive circuit 121 maintains and drives the Y electrode 12 group in common via the scan driver 122. The scan driver 122 scans the Y electrodes 12 individually. The driver of the X electrode 11 and the Y electrode 12 has the same configuration as before.

In the address electrode 13 group, the R and B address electrodes 13 r and 13 b are connected to a first address driver (individual address dryer) 132 having a function of individually driving the electrode group. The G address electrode 13g is connected to a second address driver (common address dry module) 140 having a function of driving the electrode group in common.

In the PDP 10, the sealing portion 3 is a frame portion that seals the discharge gas between the front and rear substrate structures. The side force of one side of the PDP 10 is also drawn and connected to the X drive circuit 111 side from the X electrode 11 group, and the Y electrode 12 group is bowed out from the other side to scan driver 122 Wired and connected to the side. In addition, the R and B address electrodes 13r and 13b are pulled out from one side of the upper and lower sides of the PDP 10 (the lower side in FIG. 3) and wired and connected to the first address driver 132 side. From the other side (upper side in FIG. 3), the G address electrode 13g group is drawn out and connected to the second address driver 135 side.

In FIG. 4, the connection configuration of the address electrode 13 and the address driver (132, 140) of the first embodiment will be described. In the first embodiment, among the cells of each color corresponding to (R, G, B) (R cell: CR, G cell: CG, B cell: CB), the address of G corresponding to the G cell (CG) A group of electrodes (Ag) 13g is collectively driven by a common second address driver 140 (Ag dry type) 140. The R and B address electrodes (Ar, Ab) 13r and 13b corresponding to the remaining R cell (CR) and B cell (CB) are the first addresses having the function that can be individually turned ON / OFF as before. It is driven by a driver (Dryno for Ar and Ab) 132. The G electrode (Ag) 13g corresponds to the third type electrode, and the R and B address electrodes (Ar, Ab) 13r and 13b correspond to the first and second type electrodes. [0027] The plurality of address electrodes 13 (Al to Am) of the PDP 10 have {Al, A4, A7, ...} = {Arl, Ar2, Ar3, ...} as the R address electrodes (Ar) 13r . In addition, G address electrode (Ag) 13g has {A2, A5, A8, ...} = {Agl, Ag2, Ag3, ...}. B address electrodes (Ab) 13b have {A3, A6, A9,...} = {Abl, Ab2, Ab3,.

The first address driver 132 located on the lower side includes, for example, a plurality of ICs 135 mounted on the address driver board 134. The IC 135 has the power shown as the drive circuit unit for the single address electrode 13. The plurality of circuit units may be configured as a single IC. The first IC (D1) 135 is connected to the first address electrode (A1), that is, the first R address electrode (Arl) 13r. The second IC (D2) 135 is connected to the third address electrode (A3), that is, the first B address electrode (Abl) 13b. The other R and B address electrodes 13r and 13b are similarly configured repeatedly.

The second address driver 140 located on the upper side is mounted and configured as an address voltage clamp circuit that is commonly connected to a group of G address electrodes (Ag) 13 g through a common wiring 141. The voltage clamp circuit itself is a known technique. The second address driver 140 generates V, a ground voltage (GND) and a predetermined address voltage (Vac) and applies them to the G address electrode 13g.

[0030] <Field drive>

Next, the basics of drive control of the PDP 10 in the first embodiment will be described with reference to FIG. The configuration of the field (or frame) 20 that is a video display unit corresponding to the display area (screen) of the PDP 10 will be described.

[0031] One field (field period) 20 constituting the video is displayed in 1Z60 seconds, for example. One field 20 includes a plurality of SFs 30 that are temporally divided for gradation expression. For example, one field 20 includes SF30 from the first “# 1” to the nth “#n”. Each SF 30 has a reset period (TR) 31, a next address period (TA) 32, and a next sustain period (TS) 33. Each SF30 in field 20 is weighted by the length of sustain period (TS) 33 (number of sustain discharges). The gradation is expressed by the combination of lighting on Z off of SF30.

[0032] Basically, in the reset period 31, a discharge (reset discharge) operation (reset operation) for setting all cells to the initial state, in other words, charge writing for preparing for the next address period 32 And the adjustment operation is performed. In the next address period 32, an operation (address operation) for selecting a lighted (ON) Z non-lighted (OFF) cell in the SF30 cell group is performed. In other words, in response to the selection of the lighting ON target cell based on the display data, the wall charges are formed in the selected cell by applying a scan pulse to the Y electrode 12 and an address pulse to the address electrode 13 (data Discharge (address discharge) for memory. This address operation is executed sequentially across all display lines of the screen (SF30) to determine the ONZOFF status of all cells in the screen. In the next sustain period 33, in the selected cell (ON state) in which the address discharge was performed in the previous address period 32, the sustain discharge is performed by applying the sustain pulse to the display electrodes (11, 12), and the display is performed. Perform the operation (sustain operation).

In the present embodiment, the address period 32 is divided into a first period (321) and a second period (322). In the first address period (321) of the first half, address operation is performed for R and B cells. That is, address discharge of the R cell and B cell driven by the individual first address driver 132 is sequentially executed. In the second address period (322) in the latter half, the address operation for the G cell is performed. That is, the G cell address discharge driven by the common second address driver 140 is performed.

It should be noted that as the address method, power that can be applied regardless of either the write address method or the erase address method, the former method is used in this example.

[0035] <Address period drive>

Next, in FIGS. 6 and 7, corresponding to the above-described configuration, the concept and driving method of the address discharge operation for selecting individual cells in the address period 32 of SF30 in the drive control of field 20 are described. Explain etc. A partial cross section of an RGB cell (CR, CG, CB) of PDP10 is shown schematically.

FIG. 6 shows a first stage operation state of the address period 32, that is, a state corresponding to the first period (321). In the first address period (321), first, R cell (CR) and B cell In the case of turning ON the light source (CB) by selecting the lighting target cell, a predetermined voltage (from the individual first address driver 132 side to the target R and B address electrodes 13r and 13b ( Apply an address pulse with Va (for example, 60V), and apply a scan pulse with a predetermined voltage (-Vyl: for example, -100V) to the corresponding Y electrode 12. This generates an address discharge (discharge 602) in the discharge space 601 of the R cell (CR) and B cell (CB). On the other hand, at this timing, for the address electrode 13g corresponding to the G cell (CG) between the R cell (CR) and the B cell (CB), the second address driver 140 causes a predetermined voltage different from Va. Maintain the clamped state (OV (GND): 1st clamp voltage) and do not perform any address discharge in the G cell.

Next, FIG. 7 shows a second stage operation state of the address period 32, that is, a state corresponding to the second period (322). In the second address period (322) following the state of FIG. 6, the address discharge is performed to turn on the G cell (CG). When address discharge of the G cell (CG) is performed, the R and B address electrodes 13r and 13b in the R cell (CR) and B cell (CB) adjacent to the G cell (CG) are connected to the G cell (CG). By simultaneously turning ON with a predetermined voltage (Va), the potential of the G cell (CG) during that time also rises to a predetermined voltage (Vac: second clamp voltage), and an address discharge (discharge 602) is generated. Can be made. The second address driver 140 maintains the clamped state at a predetermined voltage (Vac) in the G cell. Further, a scan pulse with a predetermined voltage (one Vy2: for example −40 V) different from the scan pulse applied in the first address period (321) is applied to the corresponding Y electrode 12.

[0038] <Drive waveform>

Next, referring to FIG. 8, a specific configuration example of the SF30 drive waveform in the first embodiment will be described. From the top, (a) PAr is the drive waveform for the R cell address electrode (Ar) 13r, (b) PAb is the waveform for the B cell address electrode (Ab) 13b, and (c) PAg is the G cell address. (D) PX shows the waveform for the X electrode 11 and (e) PY shows the waveform for the Y electrode 12! /.

[0039] In the first address period (321), the address electrode 13g of the G cell is always fixed at 0V (first clamp voltage), and the scan pulse (501) is sequentially applied to the Y electrode 12, and R, B Cell add An address pulse (601) based on an address voltage (Va) is applied to the less electrodes 13r and 13b to perform address discharge. Also in the second address period (322), the scan pulse (502) is sequentially applied to the Y electrode 12. In order to turn on the G cell, address discharge is performed by applying an address pulse (602) based on the address voltage (Va) to the address electrodes 13r and 13b of the adjacent R and B cells on both sides of the G cell. .

[0040] The detailed driving waveform is as follows, for example. First, in the reset period 31, in (d) PX, (e) PY, the waveform (41, 51) for charge writing is first applied to the display electrodes (11, 12) in the first period. Waveform 52 of PY has an ultimate potential of Vw. Next, during the second period, waveforms (42, 52) for charge adjustment are applied. The waveform 42 of PX is a predetermined voltage (Vxl). As a result, reset discharge occurs.

[0041] On the other hand, in (c) PAg, a predetermined voltage (Vac: second clamp voltage) 61 is applied to the address electrode 13g in the first period and 0V (first voltage is applied to the second period). Apply 62 (clamp voltage).

[0042] Next, in the first address period (321), in (a) PAr, (b) PAb, the address electrodes (Va) are applied to the address electrodes 13r, 13b corresponding to the R cell and B cell according to the display data. ) Apply the address pulse (601). (C) With PAg, the voltage 63 of the address electrode 13 g corresponding to the G cell is continuously fixed at 0 V (first clamp voltage). Further, (d) a predetermined voltage (Vxl) 43 is applied to the X electrode 11 by PX, and a scan pulse (501) is sequentially applied to the Y electrode 12 by (e) PY. In this case, the reference voltage 53 of the Y electrode 12 is set to, for example, −60V (—Va), and the voltage (one Vyl) of the scan pulse (501) is set to, for example, 100V (the magnitude of the scan pulse from the reference voltage). Is 40V). As a result, as shown in FIG. 6, address discharge is performed in the R cell and the B cell.

[0043] In the subsequent second address period (322), in (a) PAr, (b) PAb, the address electrodes 13r, 13b corresponding to the R cell and the B cell adjacent to the G cell are addressed according to the display data. An address pulse (602) with a voltage (Va) is applied. (C) The voltage 64 of the address electrode 13g corresponding to the G cell is always fixed to the predetermined voltage Vac (second clamp voltage) with PAg. Further, (d) PX applies a predetermined voltage (Vx2) 44 higher than the predetermined voltage (Vxl) 43 in the first address period (321) to the X electrode 11, and (e) PY Y electrode 12 mm, sequentially, scan pal A scan pulse (502) having a voltage higher than that of the source (501) is applied. At this time, as the reference voltage 54 of the Y electrode 12, a predetermined voltage (0V) 54 higher than the predetermined voltage (one 60V) 53 in the first address period (321) is applied. The voltage (−Vy2) of the scan pulse (502) is, for example, −40V.

[0044] In the subsequent sustain period 33, (c) while maintaining Vac (second clamp voltage) as voltage 65 at PAg, (d) PX, (e) PY, with the same predetermined voltage (Vs, — By applying repeated sustain pulses (45, 55) according to Vs), the cells in the ON state are turned on.

[0045] What is important for performing the above operation is the potential of the address period 32 of each electrode. First, in the first address period (321), since the address electrode 13g of the G cell is 0V (first clamp voltage) 63, even if the adjacent address electrodes 13r and 13b are in the ON state, the G cell There is no discharge. The configuration of the second address period (322) is particularly important. In the second address period (322), in order to discharge the G cell, the address electrodes 13r and 13b of the adjacent R cell and B cell are turned on. In this case, it is necessary to prevent discharge from occurring in the R cell or B cell in which the address discharge is not performed in the first address period (321), that is, in the OFF state. For this reason, the voltage (one Vy2) of the scan pulse (502) in the second address period (322) is set to the voltage Va, compared to the voltage (one Vyl) of the scan pulse (501) in the first address period (321). It is configured to be higher. That is,-Vy2 = — Vyl + Va. The difference voltage (Va) may be Vac or a voltage close thereto.

[0046] Specifically, in this example, —Vyl is set to —100V, Va is set to 60V, and —Vy2 is set to —40V. 60V)). With this configuration, address discharge is not erroneously performed in the R cell and B cell. In the second address period (322), the potential difference between the X electrode 11 and the scan pulse (502) requires the same voltage as in the first address period (321). Similarly, the voltage Vx2 (44) is higher than the voltage Vxl (43) by the voltage Va !, and the voltage is applied! /, (Vx2 = Vxl + V a) ₀

[0047] Further, the applied voltage is applied to the address electrode 13g of the G cell in the second address period (322). The force that makes the voltage 64 a Vac (second clamp voltage) higher than the first address period (321), for example, may be the same value as the voltage Va (Vac = Va, Vac ≠ Va is possible) is there).

[0048] In the second address period (322), the address pulse (602) is applied to the R and B address electrodes 13r and 13b adjacent to the G cell in the second address period (322) in the voltage state as described above. As a result, an address discharge can be generated in the G cell as shown in FIG. Note that the design of voltages such as Vxl, Vx2, -Vyl, Vy2, Va, Vac, etc. may be adjusted according to the electrode structure and drive system of 1S PDP10 as described above.

As described above, according to the first embodiment, a specific type of address electrode (Ag) 13g among the three types of address electrodes 13 corresponding to each color is commonly driven, so that a necessary address is particularly obtained. The number or scale of drivers can be reduced to about two-thirds of the conventional size, which can greatly contribute to the cost reduction of the device.

[0050] (Embodiment 2)

Next, the structure of the PDP 10 in the PDP device according to the second embodiment of the present invention will be described with reference to FIGS. The second embodiment is the same as the first embodiment in terms of the drive waveform and the circuit configuration, but is a configuration in which the arrangement and shape of the address electrodes 13 are devised. As described above, when addressing a G cell, an address pulse is applied to the address electrodes 13r and 13b of the R cell and B cell adjacent to the G cell, and the G cell is turned on by the electric field. is there. Therefore, the second embodiment has a configuration in which the address electrodes 13r and 13b of the R cell and the B cell are arranged closer to the G cell as shown in FIG. 9 in order to further increase the influence of the electric field. Furthermore, the width of the address electrode 13g of the G cell is made narrower than the width of the address electrodes 13r and 13b of the R cell and B cell. As a result, a more stable operation may be performed in connection with the address discharge.

[0051] Contrary to the above, as shown in FIG. 10, the G cell address electrode 13g may be wider than the R cell and B cell address electrodes 13r and 13b. Similarly, there are cases where more stable operation can be performed in connection with the address discharge.

[0052] (Embodiment 3)

Next, in FIG. 11, the drive sequence in the PDP device according to the third embodiment of the present invention Will be explained. In the third embodiment, the basic configuration is the same as that of the previous embodiment. As a different feature, in the drive control of the field 20, in some SF30 among the plurality of SF30, the second address period (322) is not implemented. For example, as shown in FIG. 11, the first minimum luminance SF30 (# 1) has only the first address period (TA1) 321 as the address period 32. That is, in SF30 (# 1), the address operation of the R and B cells is performed in the first address period (TA1) 321 and the address operation of the G cell in the second address period (322) is omitted.

[0053] In each embodiment, the address period 32 is composed of two stages (321, 322), and the required period is approximately doubled. : For applications where there is no problem even if the number of gradations is reduced only for G) (when such display is performed), as described in Embodiment 3, it corresponds to the specific color (G). The drive display can be performed without performing the operation in the second address period (322). The drive period is shortened by omitting the second address period (322).

[0054] Further, for example, in each embodiment, in addition to the force when G of RGB is a common electrode drive target (third type), blue (B) having a low luminance is set as a common electrode drive target. Similarly to the above, it is also effective to configure the B cell so that it does not operate with the first SF30 (# 1).

[Embodiment 4]

Next, referring to FIG. 12, the configuration of the electrode and driver connection of the PDP device according to the fourth embodiment of the present invention will be described. The configuration of the fourth embodiment shown in FIG. 12 differs from the configuration of the first embodiment in FIG. 3 and the like in the mounting configuration of the wiring 141 of the G address electrode 13g and the second address driver.

[0056] The address electrode 13g connected to the common second address driver 140 is output to the opposite side (upper side in FIG. 12) of the address electrodes 13r and 13b connected to the individual first address driver 132. The PDP10 glass substrate (back substrate 2) can be connected together. In the configuration of FIG. 12, a common connection is made like a wiring 141 in a region outside the sealing portion 3 on the upper side of the PDP 10.

[0057] The second address driver 140 that drives the common address electrode 13g is smaller in scale, and therefore, the X drive circuit 111 side or the Y drive circuit 121 side than the configuration of the separate substrate. To be mounted on the substrate. In the configuration of FIG. 12, the second address driver 140 is mounted on the substrate of the X drive circuit 111. This configuration has advantages such as mounting size and cost.

[0058] In addition, in the connection between the address electrode 13g and the second address line 140, the FPCB (flexible printed circuit board Z flexible cable) or the like that connects the X electrode 11 and the Y electrode 12 to the drive circuit is used. You may connect using a connection part. In the configuration of FIG. 12, when the wiring 141 of the address electrode 13g on the upper side of the PDP 10 is connected to the second address driver 140 on the X drive circuit 111, one connection on the FPCB 113 connected to the X relay board 112 is performed. Partial wiring is used.

[0059] While the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say, there is.

Industrial applicability

The present invention can be used in a plasma display device using address electrodes.

Claims

The scope of the claims

[1] A plasma including a plasma display panel in which cells of three kinds of colors are arranged in a matrix and having electrodes for addressing the cells, and a circuit unit for driving and controlling the electrode group of the plasma display panel In the display device, the electrode for the address operation is a first type corresponding to the role of selecting the first color, the second color, and the third color cell in the three colors and performing the address operation. Is composed of a group of three types of electrodes, type 2 and type 3,

The first type and second type electrodes corresponding to two types of first color and second color among the three types of colors are connected to a first drive circuit that individually drives the electrode group,

The plasma display apparatus, wherein the third type electrode corresponding to one type of the third color among the three types of colors is connected to a second drive circuit that drives the electrode group in common. .

[2] The plasma display device according to claim 1, wherein

The plasma display panel includes phosphors corresponding to three colors of red, green, and blue, includes first and second electrodes for display driving on the front substrate side, and the address on the rear substrate side. A plasma display device comprising a third electrode for operation, and comprising the cells of the three kinds of colors and the pixels thereof.

[3] The plasma display device according to claim 1, wherein

Among the electrodes for the address operation,

The first-type and second-type electrodes are connected to the first drive circuit by pulling one of the upper and lower electrodes of the plasma display panel.

The third type electrode is connected to the second drive circuit by being pulled out of the other side of the plasma display panel from which the first and second types of electrodes are pulled out. Plasma display device.

[4] The plasma display device according to claim 1, wherein

The driving period of the display area of the plasma display panel has a first period and a second period in an address period for performing an address operation for selecting an ONZOFF state of the cell according to display data, In the first period, address discharge in the selected cell is performed on the first type and second type cells corresponding to the first type and second type electrodes from the first drive circuit. In the second period to be performed, address discharge in the selected cell is performed on the third type cell corresponding to the third type electrode from the second drive circuit. Yes Plasma display device.

[5] The plasma display device according to claim 4, wherein

In the operation of address discharge from the second drive circuit to the third type cell corresponding to the third type electrode in the second period,

When the third type cell is turned on, the first type and second type cells corresponding to the first type and second type electrodes adjacent to both sides of the third type cell The plasma display device is characterized in that the first type and second type electrodes are turned on by applying a voltage, thereby performing address discharge in the third type cell and turning it on.

[6] The plasma display device according to claim 4, wherein

The plasma display panel has scan electrodes for scan driving in the address period,

In the first period, an address pulse is applied to the first type electrode and the second type electrode, a first scan pulse is applied to the scan electrode,

In the second period, an address pulse is applied to the first and second types of electrodes, a second scan pulse is applied to the scan electrodes,

The voltage of the second scan pulse applied to the scan electrode in the second period is higher than the voltage of the first scan pulse applied to the scan electrode in the first period by a predetermined voltage, A plasma display device.

[7] The plasma display device according to claim 4, wherein

In the first period, an address pulse is applied to the first and second types of electrodes, and a first voltage is applied to the third type of electrodes,

In the second period, an address pulse is applied to the first-type and second-type electrodes. And applying a second voltage to the third type electrode,

The second voltage applied to the third type electrode in the second period is higher by a predetermined voltage than the first voltage applied to the third type electrode in the first period. A driving method of a plasma display panel characterized by the above.

[8] The plasma display device according to claim 1, wherein

The first and second types of electrodes adjacent to the third type of electrode have a third type corresponding to the third type electrode rather than the center of the corresponding first and second type cells. A plasma display device, characterized in that the plasma display device is arranged at a position close to the cell side of the cell.

[9] The plasma display device according to claim 8, wherein

The plasma display apparatus according to claim 3, wherein the third type electrode has a narrower width than the first type and second type electrodes.

[10] In the plasma display device according to claim 8,

The plasma display device according to claim 3, wherein the third type electrode has a wider shape than the first type and second type electrodes.

[11] The plasma display device according to claim 1,

In the drive control of the plasma display panel, the address discharge operation for the third type electrode from the second drive circuit is omitted in at least one subfield among a plurality of subfields constituting the field. Plasma display device characterized by

[12] The plasma display device according to claim 1, wherein

The plasma display panel includes first and second electrodes for display driving, and a third electrode for the address operation,

A drive circuit for the first electrode and a drive circuit for the second electrode;

The plasma display apparatus, wherein the second driving circuit is mounted on a substrate of the driving circuit for the first electrode or the driving circuit for the second electrode.

[13] In the plasma display device according to claim 12,

The group of the third type electrodes are commonly connected in the side area of the plasma display panel, The wiring for connecting the common connection wiring of the group of the third type electrode and the second driving circuit constitutes the wiring of the driving circuit for the first electrode or the driving circuit for the second electrode. A plasma display device comprising a part of a flexible module.