JP2000231882A - Alternating-current surface discharge type plasma display panel, driving method of alternating-current surface discharge type plasma display panel, plasma display device, and manufacture of alternating-current surface discharge type plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of ICs for address electrode driving, high-density electrode wiring, high-density packaging at terminals, and the instability of writing discharge, involved in the heightened definition of an AC surface discharge type plasma display panel(PDP). SOLUTION: A first substrate 51Rd is equipped with address auxiliary electrodes 47T, 47B disposed on a surface 9S of a backing glass substrate 9 so as to cover adjoining lane areas ARLm-2, ARLm-1, adjoining lane areas ARLm, ARLm+1, etc., respectively, and common address electrodes 46 disposed on a surface 15S of an insulating layer 15 so as to cover the adjoining lane areas ARLm-2, ARLm-1, the adjoining lane areas ARLm, ARLm+1, etc., respectively, and impressed with voltage based on image data. In a PDP equipped with the substrate 51Rd, writing discharge takes place only in a discharge cell to which both an electrode 46 and the electrode 47T or 47B belong, these being impressed with a voltage of the same polarity. During the first half (or the latter half) of an address period, the electrode 46 and the electrode 47T (or 47B) are each impressed with a voltage having the above-mentioned relation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AC surface discharge type plasma display panel (hereinafter, also referred to as "AC type PDP" or simply "PDP") which is most suitable for high definition.
The present invention relates to a structure and a driving method of a DP, and more particularly to a reduction in the number of address electrode driving ICs, a reduction in a pattern density of an address electrode, and a speeding up of a writing operation.

[0002]

2. Description of the Related Art FIG. 31 shows a general conventional AC type PDP.
FIG. 2 is an exploded perspective view showing the structure of FIG.

As shown in FIG. 31, a conventional AC type PDP is
51P (hereinafter simply referred to as “PDP51P”)
Front panel 51FP and rear panel 51RP are arranged such that cathode film 4P and the top of barrier rib 7P are in contact with each other to form discharge gas space or discharge space 51SP. The front panel 51FP and the rear panel 51RP are sealed at a peripheral portion (not shown), and a discharge gas such as a Ne-Xe mixed gas or a He-Xe mixed gas is sealed in the discharge space 51SP.

In the front panel 51FP, 2N strip-shaped transparent electrodes 1P are formed on the surface of the front glass substrate 5P forming the display surface on the side of the discharge space 51SP in parallel with the surface.
They are formed parallel to each other along the direction D2. Furthermore,
A strip-shaped bus electrode 2P made of a metal material for supplementing the conductivity of the transparent electrode 1P and supplying a voltage to the electrode 1P is provided on the surface of the transparent electrode 1P on the discharge space 51SP side.
It is formed along P. The (plural) electrodes having a structure composed of the transparent electrode 1P and the bus electrode 2P are paired with each other every two adjacent electrodes, and one pair of the electrodes forms one scanning line or display line. I have. At this time,
As shown in FIG. 31, the n-th (1 ≦ n ≦ N) scanning line S
Ln is constituted by two electrodes Xn and Yn that form a pair with each other. Each of the bus electrodes 2P of the electrodes Xn and Yn is a part of the surface of the transparent electrode 1P on the side of the scanning lines SLn-1 and SLn + 1 adjacent to the scanning line SLn, that is, the scanning line Sn.
It is formed at a position farthest from the central axis of Ln. In addition, a region between the opposing edges of the electrode pair Xn and Yn (each transparent electrode 1P thereof) (including a three-dimensional region in the third direction D3 perpendicular to the surface of the front glass substrate 5P) is referred to as “ This is referred to as "internal gap G".

A dielectric 3P is formed over the entire surface of the front glass substrate 5P so as to cover the transparent electrode 1P and the bus electrode 2P.
An MgO vapor-deposited film or a cathode film 4P functioning as a cathode at the time of discharge is formed on the surface of the discharge space 51SP.

On the other hand, in the rear panel 51RP, a first direction D1 orthogonal to the second and third directions D2 and D3 is provided on the surface of the rear glass substrate 9P on the side of the discharge space 51SP.
That is, in the direction orthogonal to the electrodes Xn and Yn, M write electrodes 6P or address electrodes Am (1 ≦ m ≦ M) each having the same width are formed to extend, and the address electrodes 6P are A glaze layer or an overglaze layer 10P made of a dielectric is formed over the entire surface of the rear glass substrate 9P so as to cover the same. A barrier rib 7P is formed on the surface of the overglaze layer 10P on the discharge space 51SP side located in the region between the adjacent address electrodes 6P. Further, on the side walls of the adjacent barrier ribs 7P facing each other and on the above-mentioned surface of the overglaze layer 10P sandwiched between the adjacent barrier ribs 7P, a phosphor or a fluorescent material that emits a red, green, or blue fluorescent color, respectively. Body layer 8RP, 8GP, 8B
P (these are also collectively referred to as “phosphor (layer) 8P”)
Are formed.

In the PDP 51P, the structure at each point where the scanning line formed by the electrode pair and the address electrode 6P three-dimensionally intersect forms one discharge cell or light emitting cell as one pixel in the display panel. A large number of the discharge cells are arranged in a matrix to form a screen or a display area of the PDP 51P. In the following description, the scanning line SLn (accordingly, the electrode pair Xn, Yn)
A discharge cell or a light emitting cell at a position where an address and an address electrode Am intersect three-dimensionally is referred to as "a discharge cell or a light emitting cell at an address (n, m)". Then, each electrode Xn, Y
By applying a predetermined voltage to n and Am, a discharge is generated in the discharge space 51SP of the discharge cell at the address (n, m).

As an example of a PDP driving method, for example, 1
There is a method of driving by dividing the video display time for a screen into a plurality of subfields each having an erasing period, an address period, and a sustaining period. In such a driving method, first,
The display history of the immediately preceding subfield is deleted during the deletion period. In the subsequent address period, based on the input image data, information as to whether or not to generate a sustain discharge in a subsequent sustain period is given to each discharge cell. At this time, the electrode Yn as a scanning electrode (in contrast, the electrode Xn is referred to as a “sustain electrode X”
n)), and applying the predetermined voltage Von or Voff based on the input image data to the address electrode Am, thereby applying the above information to all the discharge cells. Write. For details, ON
The address electrode Am to which the voltage Von based on the image data of the state is applied and the scan electrode Yn to which the voltage (-Vy) is applied
And a write-facing discharge is generated between them. The counter discharge is used as a trigger to generate a writing surface discharge between the pair of electrodes Xn and Yn, thereby accumulating wall charges as the information on each surface of the cathode film 4P located above the electrodes Xn and Yn. (At this time, the voltage Vx is applied to the sustain electrode Xn.) Then, in the subsequent sustain period, a PDP image is displayed by causing a sustain discharge for display light emission in the discharge cells in which the information is written.

[0009]

In the conventional AC surface discharge type PDP, one discharge cell is formed at a portion where the address electrode 6P and the scanning line or the display line three-dimensionally intersect. . The plurality of address electrodes 6P are electrically independent of each other, and the conventional plasma display device includes address drivers having output bits or output terminals as many as the number of the address electrodes 6P. This address driver is generally composed of one or more address electrode drive ICs. At this time, if a high-definition display such as a full-spec high-definition display is constituted by a plasma display device, a driving IC for address electrodes having a total of 5760 output bits is required. There is a problem that the ratio of the address electrode driving IC occupying is very large.

Further, when the size of (the display area of) the PDP is the same, the address electrodes 6 are increased with the increase in the definition of the PDP.
Since the pattern density of P becomes high, it is difficult to form the pattern accurately. In addition, the wiring from the terminal of the address electrode 6P to the output terminal of the drive IC for the address electrode also has a high density, so that a higher-density mounting technology for such a wiring is required. In addition, in each terminal formed in a fine pattern, ion migration of a terminal electrode material may be caused when a high voltage is applied between adjacent terminals under a high load.

Further, the high definition of the PDP causes the following problems with respect to the driving method. First, in the address operation period or the address period, in order to stably perform the address discharge or the address discharge in the selected predetermined scanning line, the pulse application time of the voltage Von or Voff applied to the address electrode Am, or The pulse application time of the voltage (voltage value (-Vy)) applied to the sustain discharge electrode forming the selected scanning line needs to be increased as the definition becomes higher. This is because the voltage Von and the predetermined voltage (−V) are applied to the address electrode Am and the scan electrode Yn, respectively.
y), the address electrodes A
This is because the delay time until the address opposite discharge occurs between m and the scanning electrode Yn becomes longer. The following (a) and (b) are presumed as causes of the increase in the delay time.

(A) In the case where the size of the PDP (display area) is the same, high definition is generally achieved by the line width or width (in the second direction D) of the address electrode 6P (see FIG. 31).
(Length along 2). At this time, even if the same potential difference is given (that is, even if the number of equipotential lines is the same), the narrower the width of the address electrode Am is,
The distribution of equipotential lines in the discharge space between the address electrode Am and the scan electrode Yn becomes denser on the address electrode Am side. In particular, the electric field intensity in the vicinity of the discharge space in contact with the cathode film 4P above the scanning electrode Yn becomes smaller, and the range of the electric field having the intensity necessary for starting the opposing discharge between the electrodes Am and Yn becomes narrower. That is, in the vicinity of the discharge space in contact with the cathode film 4P, the influence of the voltage applied to the address electrode Am on the electric field formation decreases (at this time, the influence of the voltage applied to the scan electrode Yn relatively increases). The electric field intensity in the vicinity of the discharge space in contact with the cathode film 4P, which plays an important role in initiating the opposing discharge between the electrodes Am and Yn, is remarkably reduced.

(B) Further, while a voltage Von is applied to the address electrode Am based on, for example, input image data, the address electrodes Am-1 and Am adjacent to both sides of the voltage Von are applied.
When the voltage Voff is applied to both + 1s, it becomes more difficult for address discharge to occur in the discharge cells to which the address electrodes Am belong. This is because the electric field is formed in the discharge space between the address electrode Am to which the voltage Von is applied and the scan electrode Yn of the selected scan line, and is applied to the address electrode Am-1 and the address electrode Am + 1. This is because the electric field due to the applied voltage Voff becomes a hindrance factor. This inhibiting factor is caused by the above address electrodes Am-1, Am,
The smaller the pitch between adjacent electrodes of Am + 1 or the interval between the electrodes, the larger it becomes.

As one method for eliminating the causes of the above (a) and (b), the address electrodes 6 have
Even when the pattern density of P is increased, the width of the space region, which is the region between the electrode patterns of the adjacent address electrodes 6P, is reduced, so that the address electrodes 6
A method of suppressing the narrowing of the line width of P can be considered.

However, from the viewpoint of the manufacturing process, the address electrodes 6 are disposed on the large-area rear glass substrate 9P.
When patterning P at high density, one of the line width of the address electrode 6P and the space width or the width (the length of the same area in the second direction D2) which is the width of the space area is used. But it is very difficult to make it much smaller. For example, one with a size of about 116 cm diagonal
In the case of full-spec HDTV having a display area of 6: 9, the area allocated as the line width and the space width for one address electrode 6P is 176 μm.
It is. Even if this is equally distributed, the width dimension given to the line width and the space width is 88 μm each.
m. When a band-shaped address electrode is patterned on a glass substrate having a large area of about 116 cm diagonal with such a width, it is difficult to secure a sufficient forming process margin. In other words, even in such dimensions, it is very difficult to further reduce the space width in a situation where the formation of the address electrode and the space region itself is difficult.

As another method for eliminating the causes of the above (a) and (b), the voltage value Vy and the voltage value Von
It is conceivable to increase the applied voltage (Von + Vy) between the electrodes Am and Yn by increasing.

However, if the voltage value Vy is increased, the voltage (Voff + Vy) increases, so that an erroneous address discharge (hereinafter, “address erroneous discharge” or “erroneous address discharge”) occurs in a discharge cell in which the image data is OFF. Call). If the voltage value Voff is reduced to cope with this, the switching voltage width (Von-Voff) when driving the address electrode drive IC increases, so that the load on the drive IC further increases. In addition, the electric field due to the voltage applied to the address electrodes Am-1 and Am + 1 described in (b) above is generated by the address electrode A.
The influence of m on the formation of the electric field in the discharge cell to which it belongs is increased.

On the other hand, when the voltage value Von is increased, the switching voltage width (Von-Voff) increases, so that the load on the address electrode drive IC increases.
When the voltage value Voff is increased in order to reduce such a load, the voltage (Voff + Vy) becomes large, which causes a problem that the above-described erroneous write discharge is likely to occur. When the voltage value Von is increased, for example, when there is a discharge cell on which image data in the ON state is written on both sides of the discharge cell in which image data in the OFF state is written, each address of the discharge cell on the both sides is written. The voltage Von applied to the electrode 6P forms a stronger electric field in the discharge cell therebetween. As a result, even when the voltage value Von is increased, the above-described erroneous write discharge easily occurs.

As described above, as the definition becomes higher, the degree of reciprocity between the elements of reducing the load on the address electrode drive IC, facilitating the rise of the regular address discharge, and suppressing the erroneous address discharge increases. Become. For this reason,
In order to satisfy all such factors, the voltage value Von
Alternatively, a method of compensating for an increase in the stochastic delay time of the occurrence of the (regular) address discharge by increasing the application time of these pulses without changing the Voff or the voltage value Vy. That is, the pulse application time is set longer than the delay time.

However, in view of the fact that the number of scanning lines increases with higher definition, if the writing time per scanning line becomes longer, the time occupancy of the address period in the subfield increases. At this time,
When the number of subfields is set to be the same as that of the conventional driving method in order to avoid a reduction in the number of gradations, it is necessary to reduce the time allocated as the sustain period. Further, when the number of sustain pulses in the sustain period is set to be the same as that of the conventional driving method in order to avoid a decrease in display luminance, it is necessary to shorten the period of the sustain pulses applied to the electrodes Xn and Yn. is there. However, in such a case, there arises a problem that the sustain discharge becomes unstable.

On the other hand, a driving method is conceivable in which the number of gradations is reduced by reducing the number of field divisions for one screen as compared with the conventional driving method. According to such a driving method, it is possible to provide a sufficient time for the address discharge or the sustain discharge. However, as the number of gradations is reduced, the excellent image quality inherent in the high definition PDP cannot be sufficiently exhibited.

As described above, it can be said that it is very difficult to satisfy all of the above-mentioned various elements in the high definition AC surface discharge type PDP or the plasma display device having the same. Under such circumstances, the current PDP uses the conventional PDP to achieve high-quality display image quality.
In many cases, a driving method in which the voltage Von is increased and the voltage Voff is decreased compared to the DP is adopted. In other words, the priority order for reducing the load on the address electrode drive IC is set slightly lower. Therefore, the drive I for the address electrode
C that can withstand a high load is frequently used as C, and the ratio of the driving IC in the cost or price of the plasma display device is very large.

Accordingly, the present invention solves the above-mentioned problems, and provides an AC surface discharge type plasma display panel suitable for high definition, a method of driving the panel, a method of manufacturing the panel, and a plasma to which the method of driving is applied. The main purpose is to provide a display device. And in order to achieve such a main object, the present invention has the following more detailed objects.

First, an AC surface discharge type plasma display panel having a structure capable of reducing the number of address electrode drive circuits (drive ICs) in a conventional PDP is provided, and is applied to the AC surface discharge type plasma display panel. A first object is to provide a driving method.

It is a second object of the present invention to provide an AC surface discharge type plasma display panel and a method of driving the same capable of realizing the first object and further increasing the speed of the writing operation.

Further, there is provided an AC surface discharge type plasma display panel which can realize the first object, and which has a structure in which a pattern density related to an address electrode in a conventional PDP is reduced. And a third purpose.

[0027]

According to a first aspect of the present invention, there is provided an AC surface discharge type plasma display panel according to the first aspect of the present invention, wherein a substrate and one of the surfaces of the substrate are arranged in parallel at least in a display area. A plurality of band-shaped common address electrodes, each of which is classified into a group consisting of first to s-th (s is an integer of 2 or more) common address electrodes, and a group consisting of first to s-th address auxiliary electrodes, respectively. A first substrate including a plurality of band-shaped address auxiliary electrodes to be classified, and band-shaped scan electrodes each arranged in parallel with each other and arranged in a direction crossing the common address electrode and the address auxiliary electrode three-dimensionally; A second substrate comprising a plurality of electrode pairs, comprising a sustain electrode, and a dielectric disposed so as to cover the plurality of electrode pairs; A space between the second substrate and the second substrate is disposed along a longitudinal direction of the common address electrode and the address auxiliary electrode via barrier ribs for partitioning the space into a plurality of discharge spaces filled with a discharge gas. A plurality of discharge cells, each formed by a lane region defined as a region between centers in the longitudinal direction of each of the two barrier ribs and each of the electrode pairs, includes a plurality of discharge cells; In the j-th (1 ≦ j ≦ s) lane area, at least a part of the j-th common address electrode and at least a part of the j-th address auxiliary electrode are both disposed. Characterized by being classified into groups consisting of:

(2) The AC surface discharge type plasma display panel according to the second aspect of the present invention is the AC surface discharge type plasma display panel according to the first aspect,
The first to s-th common address electrodes are commonly connected in a unit of the group, and the j-th address auxiliary electrodes belonging to each of the plurality of groups are commonly connected between the plurality of groups. And

(3) The AC surface-discharge type plasma display panel according to the invention described in claim 3 is the first or second invention.
Wherein the plurality of common address electrodes and the plurality of address auxiliary electrodes are arranged on separate planes via an insulating layer in the display area. Features.

(4) An AC surface-discharge type plasma display panel according to a third aspect of the present invention is the AC surface-discharge type plasma display panel according to the third aspect,
The plurality of common address electrodes and the plurality of address auxiliary electrodes do not have overlapping portions in the display area when the first substrate is viewed from a direction perpendicular to the surface of the substrate. And

(5) An AC surface discharge type plasma display panel according to claim 5 is the AC surface discharge type plasma display panel according to claim 4, wherein
When the first substrate is viewed from a direction perpendicular to the surface of the substrate, the display area is completely filled with the common address electrodes and the address auxiliary electrodes without gaps.

(6) The AC surface discharge type plasma display panel according to the invention described in claim 6 is the first or second aspect.
5. The plasma display panel according to claim 1, wherein the common address electrode and the address auxiliary electrode are arranged on the same plane in the display area.

(7) An AC surface-discharge type plasma display panel according to the invention described in claim 7 is provided in claims 1 to 6
5. The AC surface discharge type plasma display panel according to claim 1, wherein the lane adjacent to the lane region to which at least a part of one of the plurality of j-th address auxiliary electrodes belongs. At least a part of the other j-th address auxiliary electrode among the plurality of j-th address auxiliary electrodes is not arranged in the region.

(8) An AC surface discharge type plasma display panel according to claim 8 is the AC surface discharge type plasma display panel according to claim 7,
The plurality of address auxiliary electrodes are arranged at a predetermined pitch based on the width of the lane area in the arrangement direction, and are classified into first and second address auxiliary electrodes alternately arranged. It is characterized by the following.

(9) The AC surface-discharge type plasma display panel according to the ninth aspect of the present invention is characterized in that:
5. The AC surface discharge type plasma display panel according to any one of claims 1 to 3, wherein at least a part of one of said plurality of j-th address auxiliary electrodes adjacent to said lane region to which at least a part of said j-th address auxiliary electrode belongs. At least one of the j-th address auxiliary electrodes of the plurality of j-th address auxiliary electrodes is arranged in at least one of the lane areas in the lane area.

(10) An AC surface discharge type plasma display panel according to the invention according to claim 10 is the AC surface discharge type plasma display panel according to claim 9, wherein each of the plurality of address auxiliary electrodes is Are arranged at a predetermined pitch based on the width of the lane area in the arrangement direction, and are classified into first and second address auxiliary electrodes alternately arranged in two units of the same type of electrode. It is characterized by being performed.

(11) An AC surface-discharge type plasma display panel according to the invention of claim 11 is the AC surface-discharge type plasma display panel according to any one of claims 1 to 10, wherein Each time, the entirety of the common address electrode is arranged.

(12) An AC surface discharge type plasma display panel according to claim 12 is the AC surface discharge type plasma display panel according to any one of claims 1 to 10, wherein the common address electrode is provided. At least one of the address auxiliary electrodes has a pattern shape extending over two adjacent lane regions.

(13) An AC surface discharge type plasma display panel according to the invention of claim 13 is the AC surface discharge type plasma display panel according to claim 1 or 2, wherein the plurality of address auxiliary electrodes are , And first and second address auxiliary electrodes, wherein the first address auxiliary electrode is formed to extend to one side in the longitudinal direction along the longitudinal direction in the display area, and the first address auxiliary electrode is formed in the display area. The display device further includes a wiring portion extending to a terminal for the first address auxiliary electrode disposed outside, and the second address auxiliary electrode is provided on the other side in the longitudinal direction along the longitudinal direction in the display area. And a wiring portion extending to the terminal for the second address auxiliary electrode disposed outside the display area.

(14) An AC surface-discharge type plasma display panel according to claim 14 is the AC surface-discharge type plasma display panel according to claim 1 or 2, wherein the plurality of common address electrodes and Each of the plurality of address auxiliary electrodes further includes a wiring portion from one end of each of the electrodes to a terminal for each of the electrodes provided outside the display area, and each of the wiring portions is It is characterized by being electrically separated from each other by an insulating layer arranged outside the display area.

(15) According to a fifteenth aspect of the present invention, there is provided a plasma display device including the AC surface discharge type plasma display panel according to any one of the first to fourteenth aspects.

(16) A method for driving an AC surface discharge type plasma display panel according to the invention of claim 16 is as follows.
The method for driving the AC surface discharge type plasma display panel according to claim 1 or 2, wherein an image display time for one screen is divided into a plurality of subfields, and each of the plurality of subfields is divided into a plurality of subfields. At least, in synchronization with the selective scanning of the scan electrode, an address period in which an address discharge based on image data is generated in the predetermined discharge cell, and a predetermined number of sustain discharges in the discharge cell in which the address discharge has occurred. And a sustaining period for generating, in the address period, a voltage of one of the first voltage and the second voltage based on the image data of the discharge cells belonging to the j-th lane region of each group. , When the voltage is applied in common to the first to s-th common address electrodes belonging to the group in the group unit, And applies a third voltage to the address auxiliary electrode, the auxiliary address electrodes other than the first j auxiliary address electrodes and wherein applying a fourth voltage having a different voltage value and the third voltage.

(17) A method for driving an AC surface discharge type plasma display panel according to the invention described in claim 17 is as follows.
17. The method of driving an AC surface discharge type plasma display panel according to claim 16, wherein both the common address electrode to which the first voltage is applied and the address auxiliary electrode to which the third voltage is applied belong. The first to fourth voltages are set so that the address discharge can be generated only in the discharge cells belonging to the lane region.

(18) A method of driving an AC surface discharge type plasma display panel according to the invention described in claim 18 is as follows.
18. The method for driving an AC surface discharge type plasma display panel according to claim 16, wherein the driving method for the j-th lane area is performed for each of the first to s-th lane areas. Features.

(19) A method for driving an AC surface discharge type plasma display panel according to the invention described in claim 19 is as follows.
17. The method of driving an AC surface discharge type plasma display panel according to claim 16, wherein at least one of the plurality of sub-fields forming an image display time for the one screen.
In the address period in one of the subfields, the address discharge is performed only in the discharge cells belonging to predetermined t (t is an integer of 1 or more and less than s) lane areas in the first to sth lane areas. It is characterized by generating.

(20) A method for driving an AC surface discharge type plasma display panel according to the invention described in claim 20 is as follows.
The method for driving the AC surface discharge type plasma display panel according to claim 1 or 2, wherein an image display time for one screen is divided into a plurality of subfields, and each of the plurality of subfields is divided into a plurality of subfields. At least, in synchronism with the selective scanning of the scan electrode, an address period for generating an address discharge based on image data in a predetermined discharge cell, and a predetermined number of sustain discharges in the discharge cell in which the address discharge has occurred. When a sustain period is provided, the same voltage is applied to both the common address electrode and the address auxiliary electrode during the sustain period.

(21) According to a twenty-first aspect of the present invention, a plasma display apparatus is driven by applying the method of driving an AC surface discharge type plasma display panel according to any one of the sixteenth to twentieth aspects. Features.

(22) A method for manufacturing an AC surface discharge type plasma display panel according to the invention described in claim 22 is as follows.
6. The method of manufacturing the AC surface discharge type plasma display panel according to claim 5, wherein the manufacturing method of the first substrate includes: (a) one of the common address electrode and the address auxiliary electrode; A step of preparing the light-transmitting substrate, in which an electrode and the light-transmitting insulating layer disposed to cover the one electrode are disposed on the one surface side; b) arranging a photosensitive material on the surface where the insulating layer is exposed, and (c) irradiating light from the other surface side of the substrate using the one electrode as a mask, Exposing the conductive material to light.

[0049]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the embodiments of the present invention, the prerequisite technology will be described.

(Base Technology) As a base technology, an AC type PD
An example of a method of driving P will be described. The driving method according to the base technology is proposed in Japanese Patent Application No. 9-173962.

In the driving method of the AC type PDP according to the base technology, a video display time for one screen is divided into a plurality of fields as a driving method for displaying a color image. Here, as shown in FIG. 1, a case where a color image of 256 gradations is obtained by dividing a video display time for one screen into eight subfields SF1 to SF8 will be described.

Each of the subfields SF1 to SF8 further includes an erasing operation period or erasing period RA or RB for erasing the light emission history in the immediately preceding subfield, and the light emission / emission of the light emitting cells in the subfield.
A write operation period or address period AD for selecting non-light emission and a sustain operation period or sustain period S for executing discharge / non-discharge a predetermined number of times according to the state selected in the immediately preceding address period AD. Has been split.
At this time, the sustain periods S of the subfields SF1 to SF8 are ranked for each of the subfields SF1 to SF8. For example, the time of the sustain period S in the subfield SF2 is the time of the sustain period S in the subfield SF1. Is set almost twice as large as That is, the duration of the sustain period S of the subfield SF (N + 1) is set to be approximately twice that of the subfield SFN (N: 1).
~ 7).

In the light emitting cells or the discharge cells selected in the address period AD of each subfield, the sustain pulses applied during the sustain period S generate the same number of sustain discharges as the number of the sustain pulses. Visible light emission generated by the sustain discharge becomes display light emission of the light emitting cell. As described above, since the number of the sustain pulses is set so as to be substantially proportional to the time of the sustain period S of each of the subfields SF1 to SF8, the light emission luminance of the light emitting cell selected by the write operation in the address period AD. Almost doubles as the subfield number advances by one. Therefore, by controlling the combination of lighting / non-lighting (ON state / OFF state of the light emitting cell) in the sustain period S in each subfield, two light emitting cells in one light emitting cell are controlled.
⁸ = 256 levels of light emission luminance, that is, display light emission of 256 gradations can be obtained.

Next, a more specific driving method in one subfield will be described with reference to the timing charts of FIGS. Here, the conventional AC shown in FIG.
The case where the type PDP 51P is used will be described. 2 and 3
(A) shows the address electrodes Am (1) corresponding to the predetermined address electrodes 6P of the M lines in FIG.
≦ m ≦ M), and (b) shows N sustain electrodes X connected in common and applied with a single voltage.
6 is a timing chart of 1 to XN (also referred to collectively as “sustain electrodes X”), where (c) to (e) are timings of predetermined scan electrodes Yn (1 ≦ n ≦ N) out of N lines It is a chart. Each of the subfields shown in FIGS. 2 and 3 has an erasing period RA or an erasing period RB, respectively.

In each address period AD of FIGS. 2 and 3,
By sequentially applying a voltage (-Vy) to the scanning electrodes Yn, an n-th scanning line SLn composed of an electrode pair Xn and Yn is applied.
(See FIG. 31).
At this time, a voltage Von / voltage Voff based on the ON state / OFF state of the image data is applied to the address electrode Am in synchronization with the application of the voltage (−Vy). Further, a predetermined voltage Vx is applied to sustain electrode X. In the discharge cell in which the voltage Von is applied to the address electrode Am, an address discharge occurs, and the image data is written into the light emitting cell (as wall charge). On the other hand, the address discharge does not occur in the light emitting cell in which the voltage Voff is applied to the address electrode Am.

In the subsequent sustain period S, an AC sustain pulse or a sustain voltage Vs is applied between the sustain electrode Xn and the scan electrode Yn. At this time, in the discharge cells in which the address discharge has occurred in the above-described address period AD, a sustain discharge is generated corresponding to the timing when the above-described sustain pulse Vs is applied.

Here, with reference to FIG. 4 and FIG. 5, a description will be given of a mechanism of generating the address discharge in the address period AD. When a voltage Vx and a voltage (−Vy) are applied to each of the electrodes Xn and Yn, an upper discharge space 51SP between the electrode pair Xn and Yn is applied.
Generates an electric field. However, with such an electric field alone, the electrode pair X
It does not have the electric field strength necessary to generate a surface discharge between n and Yn. In such a state, the address electrode Am
Is applied with a voltage Von based on image data in the ON state, a strong electric field is generated between the address electrode Am and the scanning electrode Yn, and as shown in FIG. An opposite discharge DC1 is generated. Then, the charged particles generated by the counter discharge DC1 serve as a trigger to generate a (writing) surface discharge DC2 between the electrode pair Xn and Yn, as shown in FIG.

The negative or positive charged particles generated by the surface discharge DC2 are attracted to the electrodes Xn and Yn having polarities opposite to the polarities of the same particles, respectively, and the cathode film 4P above the electrodes Xn and Yn. It is stored as wall charges on the surface 4SP. At this time, the electric field formed in the discharge space 51SP by the wall charges is gradually attracted to the surface 4SP because the voltage applied between the pair of electrodes Xn and Yn acts in a direction to cancel the electric field formed in the discharge space 51SP. The amount of charged particles used is reduced. When the accumulated amount of wall charges reaches a certain amount, the address discharge surface discharge DC between the pair of electrodes Xn and Yn.
2 ends. At this time, even after the voltage supply to the electrodes Xn and Yn is stopped, the wall charges accumulated on the surface 4SP of the cathode film 4P remain without being eliminated. In the sustain period S following the address period AD, the electrode pair X
It plays a role of applying an electric field necessary for generating a sustain discharge (surface discharge) between n and Yn to the discharge space 51SP. Due to the action of the wall charges, the discharge cells to which the voltage Von is applied emit light during the sustain period S.

On the other hand, in the discharge cell in which the voltage Voff based on the OFF image data signal is applied to the address electrode Am in the address period AD, the address electrode Am
A sufficient electric field is not generated between the pixel and Yn to generate the write facing discharge DC1. Therefore, the address electrode A
No address facing discharge DC1 is generated between m and the scanning electrode Yn, and therefore, the writing surface discharge DC2 between the electrode pair Xn and Yn is not generated.
Also does not occur. As a result, the discharge cell to which the voltage Voff is applied shifts to the sustain period S while the above-described wall charges are not formed, so that no sustain discharge occurs in the sustain period S. That is, the discharge cell does not emit light.

In the sustain period S, a positive voltage Va is supplied to all the address electrodes Am as shown in FIG. 2A and FIG. 3A. As described above, in the address period AD, wall charges are formed on the surface 4SP of the cathode film 4P. At this time, the overglaze layer 10P and the phosphor layer 8P are also slightly negatively charged. Therefore, the overglaze layer 1 of the phosphor layer 8P is caused by the applied voltage Va.
The potential of the space near the portion in contact with 0P is determined by the internal gap G
Is controlled at the same level as the average potential (approximately voltage (Vs / 2) + potential exerted by the positive and negative wall charges) in the space above the central axis of. The voltage Va applied to the address electrode Am
Supplies an electric field intensity distribution having spatial symmetry with respect to the center axis of the internal gap G in the discharge space near the internal gap G, regardless of whether the voltage Vs is applied to either of the electrodes Xn and Yn. be able to. As a result, according to the driving method of FIGS. 2 and 3, the electrode pair Xn, Yn
The voltage for starting discharge applied in the middle can be reduced, and the efficiency of sustain discharge can be improved. The voltage Va is set such that the discharge intensity per sustain discharge (surface discharge) between the electrodes Xn and Yn is maximized.

An embodiment of the present invention will be described below.

Embodiment 1 (Structure of AC PDP According to Embodiment 1) FIG. 6 shows an AC surface discharge type plasma display panel (hereinafter simply referred to as “(AC type) PDP”) according to Embodiment 1. FIG. 2 is a vertical cross-sectional view schematically showing the structure of FIG. FIG. 6 corresponds to a diagram when the conventional AC PDP 51P of FIG. 31 is viewed from the first direction D1.

As shown in FIG. 6, P according to the first embodiment
In the DP, the first substrate 51Ra and the second substrate 51F are partitioned by barrier ribs 7 described later along a first direction D1, which is a longitudinal direction without a direction of extension of a common address electrode 16 described later (a plurality of the same). ) Disposed via the discharge space 51S. The first substrate 51Ra and the second substrate 51F are sealed at a peripheral portion (not shown), and a discharge gas such as a Ne-Xe mixed gas or a He-Xe mixed gas is sealed in the discharge space 51S.

First, the structure of the second substrate 51F will be described with reference to FIG. In this PDP, since the front panel 51FP of the conventional PDP 51P can be used as the second substrate 51F, the structure of the second substrate 51F will be described with reference to FIG. 31 which is a perspective view of the conventional PDP 51P. .

As shown in FIG. 6, on the surface 5S of the front glass substrate 5 on the side of the discharge space 51S on the second substrate 51F, a strip-shaped transparent electrode 1 equivalent to the transparent electrode 1P of FIG.
(2N pieces) are formed in a stripe shape along a second direction D2 perpendicular to the third direction D3 perpendicular to the surface 5S. In FIG. 6, only one transparent electrode 1 (and a bus electrode 2 described later) is shown because of the direction shown. At this time, a total of 2N transparent electrodes 1 as a whole of the present PDP form a pair with each other every two adjacent electrodes. A bus electrode 2 equivalent to the bus electrode 2P in FIG. 31 is formed at a predetermined position on the surface 1S of the transparent electrode 1 opposite to the surface 5S. More specifically, the bus electrode 2 is formed in a band shape along the edge near the edge opposite to the transparent electrode 1 that forms a pair with the transparent electrode 1 in the surface 1S of the transparent electrode 1. In the following description, electrodes composed of the transparent electrode 1 and the bus electrode 2 and forming a pair are referred to as “(sustain) electrode Xn (1 ≦ n ≦ N)” and “(scanning) electrode Yn (1 ≦ n ≦ N), respectively. Also called. At this time, similarly to the conventional PDP 51P of FIG. 31, the n-th (or n-th) scanning line or display line SLn in the present PDP is constituted by the electrode pair Xn, Yn.

Then, a dielectric or a dielectric layer 3 equivalent to the conventional dielectric (layer) 3P of FIG. I have. On the surface 3S of the dielectric layer 3 on the discharge space 51S side, a cathode film 4 made of a high secondary electron emission material such as magnesium oxide (MgO) (the cathode film 4 in FIG. 31).
P). Note that the dielectric layer 3 and the cathode film 4 are viewed from their material side and are referred to as “dielectric layer 3”.
A ". At this time, “dielectric layer 3
The “surface 3SA of A” refers to the discharge space 51S of the cathode film 4.
Side surface 4S.

On the other hand, the first substrate 51Ra, which is a feature of the PDP according to the first embodiment, has the following configuration. In the following description, in addition to FIG. 6, FIG. 7 which is a schematic plan view for describing an arrangement form of each electrode when the first substrate 51Ra is viewed from the discharge space 51S side will be used. explain. In FIG. 7, a common address electrode 16 described later is used.
(Or its central axis) is schematically illustrated by a thick solid line. In the following description, for convenience of explanation, “up” and “down” along the first direction D1 (perpendicular to both the second and third directions D2 and D3) of the first substrate 51Ra are described. "Corresponds to the upper or lower part of the display screen when using the PDP. Even in such a case, it is clear that generality is not lost.

As shown in FIGS. 6 and 7, the first substrate 51
Ra denotes the back glass substrate 9 and the first address auxiliary electrode 1
7T and the second address auxiliary electrode 17B (also collectively referred to as “address auxiliary electrode 17”) and the common address electrode 1
6, an insulating layer 15, and an overglaze layer 10. Specifically, in a display area AR1 in which discharge cells described later are arranged in a matrix, a plurality of strip-shaped first address auxiliary electrodes 17T and second address auxiliary electrodes extending parallel to each other along the first direction D1. 17B are alternately arranged on the surface 9S on the discharge space side of the back glass substrate 9 in the second direction D2 which is the arrangement direction. Here, the display area AR1 is the back glass substrate 9
Not only a planar area in the surface 9S, but also a three-dimensional area extending in the third direction D3 perpendicular to the surface 9S. This point is based on an upper drawer area AR21 and a lower drawer area A described later.
The same applies to R22, the terminal area AR3, and the area AR4.

M / 2 first address auxiliary electrodes 17T
Is formed on the side of the upper lead-out area AR21 provided on the upper side in the first direction D1 following the display area AR1, and extends along the second direction D2 in the area AR21 and on the rear glass substrate. 9 is connected to the (first) common electrode portion (wiring portion) 17T2 for the first address auxiliary electrode, which extends to the vicinity of both ends in the same direction D2. The common electrode portion 17T2 is provided in a region AR4 near the end on the right and left sides of the rear glass substrate 9 in the second direction D2, from both ends of the portion extending along the second direction D2 in the same direction D2. Both further have a portion extending along the first direction D1. The portion extending along the first direction D1 reaches the terminal portion region AR3 provided at the end opposite to the upper lead portion region AR21, and is the same region as the portion extending along the first direction D1. The first common electrode portion 17 is formed at the end in AR3.
A terminal for T2, that is, a terminal 17T3 for the first address auxiliary electrode 17T is formed.

On the other hand, M / 2 second address auxiliary electrodes 1
7B is a lower lead portion area AR22 provided on the lower side in the first direction D1 following the display area AR1.
In the same area AR22,
The first common electrode portion 17 extends along the direction D2.
It is connected to a (second) common electrode portion (wiring portion) 17B2 for the second address auxiliary electrode 17B, which does not contact T2. The common electrode portion 17B2 is moved from a predetermined position to the first position.
It extends in the direction D1 and is formed in the lower lead portion area AR2.
2 and a terminal area A provided in the first direction D1.
It further has a portion leading to R3. The common electrode portion 17 is formed by the end of the portion extending along the first direction D1.
A terminal for B2, that is, a terminal 17B3 for the second address auxiliary electrode 17B is formed.

Then, a uniform interlayer insulating layer 15 made of a dielectric is arranged in a predetermined area of the surface 9S so as to cover the address auxiliary electrode 17. As shown in FIG. 7, the interlayer insulating layer 15 is disposed so as to cover the display area AR1, the upper lead-out area AR21, the lower lead-out area AR22, and the area AR4 in the front surface 9S of the rear glass substrate 9. .

Further, on a surface 15S of the interlayer insulating layer 15 opposite to the surface 9S, M strip-shaped two-lane common address electrodes (hereinafter, also simply referred to as "common address electrodes") 16 are arranged in the first direction. They are arranged in stripes along D1. Specifically, in the display area AR1, the central axis of the common address electrode 16 in the first direction D1 and the central axis of the address auxiliary electrode 17 in the same direction D1 are arranged to coincide. At this time, the width of the common address electrode 16 along the second direction D2 is set smaller than the width of the address auxiliary electrode 17 along the same direction D2.

As shown in FIG. 7, the M common address electrodes 16 are commonly connected to each other adjacent to each other in the lower lead-out area AR22. That is, the first common address electrode 16T facing the first address auxiliary electrode 17T and the second common address electrode 16B facing the second address auxiliary electrode 17B are connected to each other. For this reason, each of the two (or a pair of) commonly connected common address electrodes is also referred to as “common address electrode PAk (k: 1 to M / 2)”. The common connection portion is further extended to the terminal area AR3, and a terminal for the two common address electrodes 16 at the end of the terminal area AR3, that is, the terminal area AR3.
3, a terminal 163 for a common common address electrode is formed. The terminal 163 for the common address electrode 16
Is connected to, for example, an FPC (Flexible Pr
The above-described address auxiliary electrodes 17T and 17T are arranged in a blank area generated between adjacent blocks BL by arranging the memory cells in blocks corresponding to the wiring pitch of an integrated circuit.
An arrangement area for the terminals 17T3 and 17B3 of B can be provided. Accordingly, as shown in FIG. 7, the terminals 163 and 17T of the common address electrode 16 and the address auxiliary electrode 17 are provided.
There is an advantage that 3, 17B3 can be integrated at one end or below the rear glass substrate 9.

It is to be noted that the above-described lower lead portion area AR22
The first and second common address electrodes 16T and 16B, which are commonly connected to each other, are electrically integrated in a wiring path from the outside of the display area AR1 to the output bit or output terminal of the address electrode drive IC. Just do it.

Then, an overglaze layer or a glaze layer 10 made of a dielectric is arranged so as to cover the common address electrode 16. Overglaze layer 10
Are formed at least in the display area AR1.
At this time, the same layer 10 may be formed in a range equivalent to the formation range of the interlayer insulating layer 15.

Further, as shown in FIG. 6, the first substrate 51R
a on the surface of the overglaze layer 10 on the side of the discharge space 51S or the surface 10S opposite to the surface 15S,
(M + 1) barrier ribs or partition walls 7 equivalent to the barrier ribs 7P in FIG. 31 are arranged. Specifically, strip-shaped barrier ribs 7 having a predetermined height along the third direction D3 and extending along the first direction D1 are arranged on the surface 10S in parallel with each other. At this time, the center axis of the barrier rib 7 in the first direction D1 and the adjacent first address auxiliary electrode 17T and second address auxiliary electrode 17
B and the central axis in the same direction D1 of the region between
The barrier ribs 7 are arranged so as to match in the direction D3.

Here, each of the (M + 1) barrier ribs 7 is also referred to as a “barrier rib Bi (i: 1 to M + 1)”, and the side wall surfaces of the barrier ribs Bm and Bm + 1 and the surface 10S are defined as follows. The lane 35 configured as described above is also referred to as “lane Lm”. Furthermore, it includes the central axis of the arbitrary one of the barrier ribs in the first direction D1, and
A three-dimensional area defined by a plane perpendicular to the second direction D2 and the same plane with respect to another barrier rib adjacent to any one of the barrier ribs is referred to as a “lane area”. At this time, the “lane area defined by the barrier rib Bm and the barrier rib Bm + 1” is referred to as a “lane area ARL”.
m ". In such a case, the (plural) first address auxiliary electrodes 17T in FIG.
m-1, ARLm + 1, ARLm + 3, ARLm + 5,
Similarly, the second address auxiliary electrode (s) 17B belong to the lane areas ARLm-2, ARLm, ARLm + 2, ARLm + 4. At this time, the address auxiliary electrodes 17 are arranged at the same pitch as the width or pitch in the arrangement direction of the lane areas. Also, in view of the relationship between the widths described above, the address auxiliary electrode 17 is provided in the first
Portion 1 covered by common address electrode 16 when substrate 51Ra is viewed from discharge space 51S side
Each lane region has 7TA, 17BA and portions 17TB, 17BB not covered by the electrode 16.

Then, the inner surface 35S of the U-shaped groove or lane 35 formed by the both side walls of the adjacent barrier ribs 7 facing each other and the surface of the overglaze layer 10.
A phosphor or phosphor layer 8 is disposed thereon. At this time, similarly to the phosphors 8PR, 8PG, and 8PB in FIG. 31, the phosphors for red light emission, green light emission, and blue light emission are arranged in units of lanes 35.

The first substrate 51Ra and the second substrate 51F having such a structure are formed in a discharge space 51 filled with a discharge gas.
It is arranged via S. At this time, a discharge cell or a light emitting cell is constituted by each component near a portion where the common address electrode 16 (and the address auxiliary electrode 17) and the scanning line cross three-dimensionally. At this time, the discharge cell to which the first common address electrode 16T and the first address auxiliary electrode 17T belong is also referred to as “(first) discharge cell CT” and the second discharge cell CT.
Common address electrode 16B and second address auxiliary electrode 17
The discharge cell to which B belongs is also referred to as “(second) discharge cell CB”.

(Method of Driving AC PDP According to First Embodiment) Next, a method of driving the AC PDP by the subfield gray scale method will be described with reference to FIG. FIG.
4 is a timing chart showing waveforms of voltages applied to respective electrodes in a writing operation period or an address period (see FIGS. 1 to 3) AD0 in the driving method. 8A to 8C respectively show the first address auxiliary electrode 17.
T, the second address auxiliary electrode 17B and the voltages VT, VB, VAk (k: 1 to 1) applied to the common address electrode PAk.
(M / 2) is a timing chart. (D) in FIG. 8 shows a voltage VX0 commonly applied to all sustain electrodes X1 to XN (which may be collectively referred to as "sustain electrodes X"), and (e) to (e) in FIG. g) is the scanning electrode Y
1, the voltages VY1, VY2, VYN applied to YN, YN are shown.

As shown in FIG. 8, the address period AD0 in the present driving method includes a first period AD1 and a second period AD2.
They are roughly divided into In the following description, for example, the voltage V
1, V2, V3, and V4, when there is a relationship of (voltage V1)> (voltage V2) and (voltage V3)> (voltage V4), “voltage V1 and voltage V3 (or voltage V2 and voltage V2)
4) are on the same side (polarity) "and" the voltage V1 and the voltage V4 (or the voltage V2 and the voltage V3) are on the opposite side (polarity) ". .

First, in the first period AD1 which is the first half of the address period AD0, as shown in FIGS. 8A and 8B, the first address auxiliary electrode 17T is set to the voltage VT and the image in the ON state. Voltage based on data (first voltage)
A voltage (third voltage) Vh having the same polarity as Von is applied, and a voltage V is applied to the second address auxiliary electrode 17B.
B, a voltage based on the OFF-state image data (second
A voltage (fourth voltage) Vl (<Vh) having the same polarity as the voltage (Voff) (<Von) is applied.
In this state, as shown in (e) to (g) of FIG. 8, voltage pulses of the voltage value (-Vy) are sequentially applied as the voltages VY1 to VYN of the scan electrodes Y1 to YN. At this time, as shown in (c) of FIG.
An address discharge or an address discharge based on image data is generated in a discharge cell to which the first address auxiliary electrode 17T belongs among a plurality of discharge cells belonging to the selected scanning line in synchronization with the YN selection scanning timing. That is, based on the image data of the discharge cells to which the first address auxiliary electrodes 17T belong to the common address electrodes PA1 to PAM / 2,
The voltage Von or the voltage Voff is commonly applied as the voltages VA1 to VAM / 2.

On the other hand, in the second period AD2, which is the latter half of the address period AD0, as shown in FIGS. 8A and 8B, the voltage VT is Voff and Voff as opposed to the first period AD1. The voltage Vl on the same side is applied, and the voltage Vh on the same side as Von is applied as the voltage VB. In this state, as in the above-described first period AD1, as shown in (e) to (g) of FIG.
The voltage values (−V
The voltage pulse of y) is applied. At this time, in the second period AD2, the voltages VA1 to VAM / 2 are synchronized with the selection scan timing of the scan electrodes Y1 to YN, and the voltages VA1 to VAM / 2 are based on the image data of the discharge cells to which the second address auxiliary electrodes 17B belong. Von or voltage Voff is applied. Thus, an address discharge based on image data is generated in a discharge cell to which the second address auxiliary electrode 17B belongs among a plurality of discharge cells belonging to the selected scanning line.

As described above, the address auxiliary electrode 17 shown in FIG.
It has portions 17TB and 17BB which are not hidden by the common address electrode 16 when viewed from the side. Therefore, in the above-described address period AD0, the scan electrode Y that has been selectively scanned is used.
In order to form an electric field near the discharge space 51S in contact with the cathode film 4 above n, the common address electrode 16 (or PAk)
Of the first address auxiliary electrode 17T and the second address auxiliary electrode 17B.
The electric field due to T and VB has a great effect. For this reason,
In the driving method according to the first embodiment, the voltages (values) Vh, V
By appropriately adjusting and controlling 1, Von, Voff and Vy, the voltage VAk of the common address electrode 16 (or PAk) and the voltage VT or the voltage V
A voltage condition that both B and B have the same polarity as the voltage Von is set as a necessary and sufficient condition for generating an address discharge in a discharge cell belonging to the first address auxiliary electrode 17T or the second address auxiliary electrode 17B. ing.

According to the voltage setting conditions, the first period A
In D1, when the voltage Von is applied as the voltage VAk to the common address electrode PAk (or 16), an address discharge occurs in the discharge cell CT to which the voltage Vh is applied as the voltage VT. On the other hand, in the discharge cell CB to which the voltage Vl is applied as the voltage VB, no address discharge occurs. Conversely, in the second period AD2, when the voltage Von is applied to the common address electrode 16,
Discharge cell CB to which voltage Vh is applied as voltage VB
Address discharge occurs, whereas no address discharge occurs in the discharge cell CT to which the voltage Vl is applied as the voltage VT. That is, in the first period AD1, an address operation is performed only on the first discharge cell CT to which the first address auxiliary electrode 17T belongs, while in the second period AD2, the second discharge cell to which the second address auxiliary electrode 17B belongs. CB
Only the write operation for the target is executed. Thus, the address operation for all the lanes 35 or all the discharge cells CT and CB is performed throughout the address period AD0. In the transition from the first period AD1 to the second period AD2, the voltage VT shown in FIGS.
The period during which both VB and VB are set to voltage Vl is not an essential component.

As described above, according to the AC surface discharge type plasma display panel and the method of driving the same according to the first embodiment, the number of address electrode terminals 163 can be reduced by applying the common address electrode 16 to the conventional AC type. It can be half that of PDP. Therefore, high-density mounting in the terminal area AR3 can be effectively avoided. Needless to say, the number of the address electrode driving ICs is reduced by half because the number of the address electrode terminals 163 is reduced by half, so that a significant cost reduction can be realized.

A plurality of common address electrodes are grouped as a common address electrode (corresponding to the common address electrode 16) for the s lanes 35, and a plurality of address auxiliary electrodes are respectively assigned to the first through third lanes 35. The AC surface discharge type plasma display panel divided into a group consisting of the s-th address auxiliary electrodes T1 to Ts (corresponding to the first or second address auxiliary electrodes 17T and 17B) is also applicable.
The above driving method can be applied. At this time, the first to s-th address auxiliary electrodes are, for example, address auxiliary electrodes T1,
, Ts, T1, T2,..., Ts,... (However, the arrangement order of the address auxiliary electrodes is not limited to this example). Further, when the number of common address electrodes belonging to each group (or the number of common address electrodes to which a voltage is commonly supplied) and the number of address auxiliary electrodes belonging to each group (corresponding to the above s) are the same, Has the advantage that only relatively simple changes need to be made to the driving method described above.

At this time, the address period is divided into s periods by blocks, and during the j-th (1 ≦ j ≦ s) period, the common address electrode is connected to the lane 35 or the discharge cell to which the address auxiliary electrode Tj belongs. When applying the voltage Von or Voff based on the corresponding image data in synchronization with the selective scanning of the scanning electrode Yn, the address auxiliary electrode T
j and the other address auxiliary electrode Ti.
A voltage Vl is applied to (i ≠ j). In such a case, the number of address electrode terminals and address electrode drive ICs can be reduced to 1 / s, so that high-density mounting can be avoided and countdown can be further promoted.

Here, an AC-type PD having one address electrode shared by adjacent discharge cells and electrically different electrodes provided in each of the adjacent discharge cells is used.
P and its driving method are disclosed in, for example, Japanese Patent Application Laid-Open No. 9-325732.
No. 6,009,045. According to the driving method according to the prior art, it is possible to select which of the adjacent discharge cells to generate the address discharge by controlling the voltages applied to the electrodes electrically different from each other. The PDP according to the related art has a structure in which a sustain discharge is performed at an intersection of a row electrode and a column electrode facing each other across a discharge space, that is, a so-called opposed discharge structure.
On the other hand, the PDP according to the first embodiment is a so-called (AC) surface discharge type plasma display panel, and the basic structure of the PDP to which each driving method is applied is greatly different.

The PDP according to the prior art is, for example, M
A total of M /
Two common address electrodes are arranged. All the column electrodes belonging to the even-numbered sections of the column electrodes divided into two by the common address electrode are commonly connected to the first type of sustain electrodes and belong to the same odd-numbered sections. All the column electrodes are commonly connected to the second type of sustain electrodes.
In other words, first and second types of sustain electrodes, which are different types of sustain electrodes, are arranged on both sides of each common address electrode. At this time, by controlling the polarities of the two types of sustain electrodes, the discharge cells belonging to the column on one side of the common address electrode can be controlled based on the ON state or OFF state image data input to the common address electrode. A discharge for erasing wall charges is generated (erase address operation). According to such a driving method, the rows on both sides of the common address electrode are independently switched by one common address electrode.

However, the polarity control of the voltage applied to the first and second sustain electrodes requires switching at a frequency higher than the frequency of the voltage based on the image data input to the common address electrode. At this time, it is necessary to provide a circuit capable of recovering the reactive power generated accompanying the switching operation with high efficiency. Moreover, such circuits are very complex.

On the other hand, in the AC type PDP according to the first embodiment, the common address electrode and the sustain electrode are not in a positional relationship parallel to each other. As described above, the AC type PDP
Includes a common address electrode shared by adjacent lane areas (or discharge cells), and an address auxiliary electrode arranged in parallel with the common address electrode. Then, by simple control of the voltage applied to the address auxiliary electrode, one of the two discharge cells sharing the common address electrode is selected.
At this time, the switching operation according to the voltage control described above
Basically, once in one address period. The switching of the scan electrodes and the sustain electrodes during the address period is the same as that of the conventional driving method except that the line-sequential scanning of the scan electrodes during the address period of the conventional driving method is performed in two cycles. . That is, it can be said that the driving method according to the first embodiment has an advantage in that there is no need to perform high-frequency switching at all unlike the driving method according to the prior art.

(Modification 1 of Embodiment 1) In Modification 1, another example of the pattern shape of the common address electrode 16 and the address auxiliary electrode 17 will be described. FIG. 9 is a plan view corresponding to FIG. 7 described above. In FIG. 9, similarly to FIG. 7, the common address electrode 16 (or the center axis thereof) is schematically illustrated by a thick solid line.

As shown in FIG. 9, the first
The substrate 51Ra2 has a structure corresponding to a so-called “upper / lower block parallel addressing system” in which (a plurality of) scanning lines (not shown in FIG. 9) are driven by being divided into upper and lower blocks of a display area. Having. More specifically, the display area AR1 is divided into an upper display area AR11 and a lower display area AR12 at the center in the first direction D1, and the first display area AR11 and the lower display area AR12 are respectively divided into first and second display areas AR11 and AR12.
And the second common address electrodes 16T and 16B, that is, the common address electrodes 16 are arranged. First substrate 5 of FIG.
The common address electrode 16 in the display area AR1 of 1Ra2 corresponds to a structure in which the common address electrode 16 in FIG. 7 is electrically divided at the center of the display area AR1 in the first direction D1.

In such a case, the first and second common address electrodes 16T and 16B belonging to the upper display area AR11 are
The common terminal is connected in the lead-out area AR21, and is extended to the upper terminal area AR31 provided above the lead-out area AR21. And
The terminal 16 for the common address electrode 16 belonging to the upper display area AR11 at the end in the upper terminal area AR31.
3 is formed. Conversely, the common address electrode 16 belonging to the lower display area AR12 is
2 are connected in common, and the terminal area AR3 described above is connected.
It extends to the lower terminal area AR32 corresponding to (see FIG. 7). The terminal 1 for the common address electrode 16 belonging to the lower display area AR12 is defined by the end of the common address electrode 16 in the lower terminal area AR32.
63 is formed.

At this time, as shown in FIG. 9, when the terminal 17T3 for the first address auxiliary electrode 17T is arranged in the above-mentioned blank area generated by blocking the terminal 163 in the upper terminal area AR31, AR31, A
It is possible to further reduce the mounting density in R32.

The first address auxiliary electrode 1 shown in FIG.
Due to the symmetry of the structure of the first address auxiliary electrode 17T and the common electrode portion 17T2 of the first address auxiliary electrode 17T,
And the terminal 17T3 are arranged in the lower lead portion area AR22 and the lower terminal section area AR32, and the common electrode portion 17B2 of the second address auxiliary electrode 17B and the terminal 17B.
3 is an upper lead portion area AR21 and an upper terminal area A
Obviously, it may be arranged in R31.

(Embodiment 2) As shown in FIG. 6, the first and second address auxiliary electrodes 17T and 17B on the first substrate 51Ra are connected to the first substrate 51Ra.
To the discharge space 51S side or the surface 9 of the back glass substrate 9.
When viewed from the S side, the first and second common address electrodes 1
Part 17 overlapping (overlapping) with 6T, 16B
TA, 17BA. For this reason, the capacitance component of the capacitor structure composed of the common address electrode 16, the address auxiliary electrode 17, and the interlayer insulating layer 15 interposed between both electrodes lowers the driving speed of the PDP. May be one of the factors.

Further, for example, the first period AD1 (see FIG. 8)
In the case where the address discharge is performed on the discharge cells CT belonging to the lane area ARLm-1 in
RLm-2, second address auxiliary electrode 17B belonging to ARLm
Is applied to the discharge cell CT.
In some cases, the formation of an electric field (including its intensity) required to generate an address discharge may be hindered. For this reason, a case where a reliable write operation cannot be performed may occur.

Therefore, in the second embodiment, the first embodiment
AC PDP capable of operating at a higher speed than the AC PDP according to the present invention and capable of executing a reliable write operation
Will be described. The AC PDPs according to Embodiment 2 and Embodiments 3 to 10 to be described later are the same as the first substrate 5 described above.
Since the structure of the first substrate corresponding to 1Ra is characteristic, the description will be focused on this point. For this reason, the same components are denoted by the same reference numerals, and the detailed description thereof will be referred to.
At this time, since the second substrate of each AC type PDP is applicable to the second substrate 51F of FIG. 6, the description thereof will be omitted. This is the same in the following description of Embodiments 3 to 10.

FIG. 10 shows the first substrate 5 according to the second embodiment.
It is a longitudinal cross-sectional view which shows typically the structure in the display area of 1Rb. In FIG. 10 and FIGS. 11 to 13 and 22 to 23 to be described later, in order to avoid complication of the drawings,
Although illustration of the phosphor 8 shown in FIG. 6 is omitted, the phosphor 8 of FIG. 6 (as described above,
(Comprising phosphors for emitting red, green and blue light).

As shown in FIG. 10, a plurality of barrier ribs 7 are arranged on a first substrate 51Rb according to the second embodiment. In each lane area defined by the adjacent barrier ribs 7, the first common address electrode 26T and the first common address electrode 26T which do not overlap each other in the third direction D3 are provided.
An address auxiliary electrode 27T or, similarly, a second common address electrode 26B and a second address auxiliary electrode 27B that do not overlap each other in the third direction D3 are arranged. In the following description, the first and second common address electrodes 26T and 26B are collectively referred to as “common address electrode 26”, and the first and second address auxiliary electrodes 27T and 27B are collectively referred to as “address auxiliary”. Also referred to as "electrode 27".

More specifically, in the lane area ARLm-1 shown in FIG. 10, for example, the first address auxiliary electrode 27T projects the lane Lm-1 and the barrier rib Bm-1 onto the surface 9S of the rear glass substrate 9. In this case, the two elements Lm-1 and Bm-1 are arranged at positions over both projected portions. And the first
The common address electrode 26T is arranged on the surface 15S of the interlayer insulating layer 15 covering the first address auxiliary electrode 27T. At this time, when the lane Lm-1 and the barrier rib Bm are projected on the surface 15S, the first common address electrode 26T is arranged at a position extending over both the projected portions of both the elements Lm-1 and Bm. . As the first substrate 51Rb as a whole,
The address auxiliary electrodes 27T are arranged at a pitch twice as large as the width or pitch in the direction of arrangement of the lane regions.

On the other hand, the lane area ARLm-1
When the second address auxiliary electrode 27B projects the lane Lm and the barrier rib Bm + 1 on the surface 9S in the lane area ARLm adjacent to, the projected portions of both the elements Lm and Bm + 1 It is located at a position that spans. Further, the common address electrode PA is provided together with the first common address electrode 26T.
k of the second common address electrode 26B
When the lane Lm and the barrier rib Bm are projected on the surface 15S, they are disposed on the surface 15 of the fifth element 5 over the projected portions of both the elements Lm and Bm. And
The overglaze layer 10 is arranged so as to cover the common address electrode 26.

As described above, the adjacent lane areas Lm−1,
Each component in Lm is arranged at a position symmetrical with respect to a boundary (plane) between both lane regions. Then, as a whole of the first substrate 51Rb, a structure in which the adjacent lane regions Lm-1 and Lm are a set is arranged along the second direction D2.

The structure or wiring pattern in the lead portion region and the terminal portion region of the first substrate 51Rb is as follows.
The same thing as that of the above-mentioned first embodiment or its modification 1 is applicable. The driving method according to the first embodiment (see FIG. 8) is applied to the driving method in the address period.

As described above, the common address electrode 26 and the address auxiliary electrode 27 on the first substrate 51Rb according to the second embodiment are such that both electrodes 26, 27 are
When viewed from the surface 9S side (that is, in the third direction D3), there is no overlapping portion. Therefore, the common address electrode 26 and the address auxiliary electrode 27
Is smaller than that of the first substrate 51Ra. Therefore, the A to which the first substrate 51Rb is applied
According to the C-type PDP, the AC-type PDP according to the first embodiment
As compared with, a higher-speed write operation can be realized.

Further, on the first substrate 51Rb, for example, the lane areas ARLm-1 and ARLm to which the common address electrode PAk belongs are included.
In RLm, the second common address electrode 26B is located closer to the first common address electrode 26T than the second address auxiliary electrode 27B. Therefore, when driving the AC PDP to which the first substrate 51Rb is applied, for example, in the first period AD1 (see FIG. 8), an address discharge is generated in the discharge cells CT (see FIG. 6) belonging to the lane area ARLm-1. In the case, the lane area ARL
The electric field due to the voltage Von applied to the second common address electrode 26B has a greater influence on the electric field formation in m-1 than the electric field due to the voltage V1 applied to the second address auxiliary electrode 27B. Therefore, the AC according to the first embodiment
Discharge cell C belonging to lane Lm-1 as compared with type PDP
At T, regular address discharge is likely to occur. That is, a reliable write operation can be performed. Further, as a result, the voltages Von and Vh can be reduced.
In the plasma display device including the DP, an advantage is obtained in that the load on the address electrode drive IC can be reduced.

(Embodiment 3) As described above, in the AC PDP having the first substrate 51Rb according to Embodiment 2, for example, the discharge belonging to the lane area ARLm-1 in the first period AD1 (see FIG. 8). When the address discharge is performed on the cell CT (see FIG. 6), the adjacent lane area A
The electric field due to the voltage Von applied to the second common address electrode 26B located closer to the discharge cell CT in the RLm region has an effect of assisting the formation of the electric field in the lane Lm-1.

However, the second address auxiliary electrode 27B belonging to the lane area ARLm-2 adjacent to the lane area ARLm-1 on the side opposite to the lane area ARLm.
Are arranged adjacent to the lane area ARLm-1.
For this reason, in the above-mentioned driving, the lane area ARL
The electric field due to the voltage Vl applied to the second address auxiliary electrode 27B belonging to the m-2 may hinder the address discharge in the discharge cells belonging to the lane area ARLm-1.

Therefore, in a third embodiment, a description will be given of a first substrate capable of providing an AC type PDP in which such a point is improved.

FIG. 11 shows a first substrate 5 according to the third embodiment.
It is a longitudinal cross-sectional view which shows typically the structure in the display area of 1Rc. As shown in FIG. 11, the first substrate 51Rc
Then, the first address auxiliary electrode 37T corresponding to the first address auxiliary electrode 27T shown in FIG. 10 and the second address auxiliary electrode 37B corresponding to the second address auxiliary electrode 27B shown in FIG. This is characterized by the arrangement position of the “address auxiliary electrode 37” (generically called “address auxiliary electrode 37”). More specifically, the first substrate 51Rb shown in FIG.
Address auxiliary electrode 27T and second address auxiliary electrode 27B
Are alternately arranged in the second direction D2, whereas in the first substrate 51Rc, as shown in FIG.
First address auxiliary electrode 37T and second address auxiliary electrode 3
7B are alternately arranged in units of two. That is, the first
Address auxiliary electrode 37T, first address auxiliary electrode 37
T, the second address auxiliary electrode 37B, the second address auxiliary electrode 37B,... Are arranged at positions corresponding to the arrangement positions of the address auxiliary electrodes 27 in FIG. The interlayer insulating layer 15 is arranged so as to cover the first and second address auxiliary electrodes 37T and 37B. And
The first and second common address electrodes 36T, 36T are located on the surface 15S of the interlayer insulating layer 15 at positions corresponding to the respective arrangement positions of the first and second common address electrodes 26T, 26B in FIG.
6B (generally referred to as “common address electrode 36”). At this time, as shown in FIG. 11, the first common address electrodes 36T belonging to the lane area ARLm-1
And the second common address electrode 36B belonging to the lane area ARLm adjacent to the area ARLm-1 form a common address electrode PAk.

The AC type PDP in which the first substrate 51Rc of FIG. 11 and the second substrate 51F of FIG.
The driving method described above (see FIG. 8) is applicable. That is,
In the address period AD0, the first address auxiliary electrode 3
7T, second address auxiliary electrode 37B, sustain electrodes X1 to XN
A voltage having a voltage waveform of (a), (b), (d), (e) to (g) in FIG. 8 is applied to each of the scan electrodes Y1 to YN. Then, the common address electrode 37
, The following voltages are applied. That is, in the first period AD1, the voltage Von or Voff based on the image data corresponding to the lane 35 or the discharge cell CT to which the first address auxiliary electrode 37T belongs is applied, while the second period AD2 is applied.
The lane 35 to which the second address auxiliary electrode 37B belongs
Alternatively, a voltage Von or Voff based on image data corresponding to the discharge cell CB is applied. As a result, an address operation for all lanes or all discharge cells is performed.

Thus, unlike the first substrate 51Rb of FIG. 10, the first substrate 51Rc according to the third embodiment has
The first address auxiliary electrode 37T is provided in the lane area ARLm-2 adjacent to the lane area ARLm-1. Therefore, for example, in the first period AD1, the lane region ARL
When the address discharge is performed on the discharge cells CT belonging to the m-1, the lane area AR among the electrodes belonging to the lane areas ARLm-2 and ARLm on both sides of the corresponding lane area ARLm-1.
The first address auxiliary electrode 37T and the lane area ARL belonging to the lane area ARLm-2 arranged in a portion close to Lm-1
A voltage having the same polarity as the voltage Von is applied to the second common address electrode 36B belonging to m. That is, a voltage having the same polarity as that of the voltage Von is applied to the electrodes existing in the vicinity of the discharge cells in which the address discharge is to be generated. For this reason, according to the AC PDP having the first substrate 51Rc, the AC PDP according to the second embodiment is used.
The address discharge can be more easily and reliably generated as compared with the DP. Of course, the second period A
In D2 (see FIG. 8), the second common address electrode 36
B having the second address auxiliary electrode 37B and the second address auxiliary electrode 37B
The same effect can be obtained when a write discharge is performed to a discharge cell belonging to (for example, lane Lm). At this time, the voltages Von and Vh can be further reduced.

Further, in the first period AD1, when the voltage Voff is applied to the common address electrode 36 (for example, the common address electrode PAk), the second address auxiliary electrode 37
A voltage having the same polarity as the voltage Voff is applied to all the electrodes near the lane 35 to which B belongs (for example, the lane Lm). Therefore, in the discharge cell to which the second address auxiliary electrode 37B belongs, the erroneous write discharge is very unlikely to occur. This is because, when the voltage Voff is applied to the common address electrode 36 (for example, the common address electrode PAk) in the second period AD2, the lane 35 having the first address auxiliary electrode 37T (for example, the lane Lm-
The same applies to the discharge cells belonging to 1). Therefore,
By increasing the voltages Voff and Vl and reducing the potential difference or the switching width (Von-Voff) and (Vh-Vl), the load on the address electrode drive IC can be reduced. At this time, the voltages VT, VB (voltage Vh or Vl) applied to the first or second address auxiliary electrodes 37T, 37B belonging to each lane 35 and the voltage VPAk (voltage Von or Voff) applied to the common address electrode 36 ), It is necessary to set the voltages Voff and Vl so that an erroneous write discharge does not occur when the polarity becomes opposite to that in FIG. However, as described above, the voltages Von,
Since Vh can be reduced, the above condition for the increase in the voltages Voff and Vl is very mild.

As described above, the first substrate 51Rc according to the third embodiment and the AC-type PD including the substrate 51Rc
P denotes each A provided with the above-mentioned first substrates 51Ra and 51Rb.
Compared with the C-type PDP, it is possible to further promote the speeding up of the write operation and the reduction of the switching width (Von-Voff). At this time, the number of address electrode drive ICs can be halved by applying the common address electrode. In the driving method shown in FIG. 8 described above, the output bit or the output terminal 1 of the address electrode drive IC in the address period AD0.
Considering that the number of output pulses per unit is twice that of the conventional plasma display device and its driving method, the first substrate 51Rc according to the third embodiment is the same as the first substrates 51Ra and 51Rb described above. It can be said that a more practical AC PDP can be provided for the driving method as compared with. That is, by increasing the speed of the write operation, it is possible to sufficiently secure the time allocated to the sustain period, and as a result, it is possible to secure a sufficient number of gradations. Needless to say, it is desirable to further reduce the switching width (Von-Voff) from the viewpoint of reducing the load on the address electrode drive IC.

(Embodiment 4) FIG. 12 shows Embodiment 4 of the present invention.
FIG. 6 is a longitudinal sectional view schematically showing a structure in a display area of a first substrate 51Rd according to the first embodiment. As shown in FIG. 12, in the first substrate 51Rd, a first address auxiliary electrode 47T and a second address auxiliary electrode 47B (collectively referred to as “address auxiliary electrodes 47”) are formed on the surface 9S of the rear glass substrate 9. Are alternately arranged in the second direction D2 which is the arrangement direction.

The first address auxiliary electrode 47T has a structure in which two adjacent first address auxiliary electrodes 37T are formed as one electrode on the first substrate 51Rc of FIG. Specifically, the first address auxiliary electrode 4
7T is, for example, a portion of the portion where the lane Lm-2 is projected on the surface 9S along the third direction D3 from the position slightly closer to the barrier rib Bm-1 from the center axis in the first direction D1 and the position and the lane area. It is a strip-shaped electrode having a width (length along the second direction D2) reaching a position symmetrical with respect to a boundary (plane) between ARLm-2 and ARLm-1, and extending in the first direction D1.

Similarly, the second address auxiliary electrode 47B disposed on the front surface 9S on the first substrate 51Rd.
Has a structure in which two adjacent second address auxiliary electrodes 37B are formed as one electrode on the first substrate 51Rc of FIG. That is, the second address auxiliary electrode 47B
Has a structure equivalent to that of the first address auxiliary electrode 47T. For example, two adjacent lane regions ARLm and ARL
It has a width of Lm + 1. The interlayer insulating layer 15 is arranged so as to cover the first and second address auxiliary electrodes 47T and 47B.

Further, the first substrate 51Rd is provided with an interlayer insulating layer 1
5 has a common address electrode 46 arranged on the surface 15S. The common address electrode 46 has the same structure as the first and second address auxiliary electrodes 47T and 47B. That is, the structure of the common address electrode 46 corresponds to a structure in which two adjacent first and second common address electrodes 36T and 36B are formed as one electrode on the first substrate 51Rc in FIG. Specifically, the common address electrode 4
6 is, for example, in a portion where the lane Lm-1 is projected on the surface 15S along the third direction D3 from a position slightly closer to the barrier rib Bm from the central axis in the first direction D1, the position and the lane area ARLm- 1, a strip-shaped electrode having a width reaching a position symmetrical with respect to a boundary (plane) between ARLm and extending in the first direction D1. At this time, the common address electrode 46 and the first and second address auxiliary electrodes 47T, 47
B does not have portions overlapping each other in the third direction D3. Then, so as to cover the common address electrode 46,
An overglaze layer 10 is provided.

According to the first substrate 51Rd according to the fourth embodiment, the number of the address auxiliary electrodes 47 disposed on the front surface 9S and the number of the common address electrodes 46 disposed on the front surface 15S in the display area have already been described. Of the first substrate 51R
The number of the same electrodes in a, 51Rb and 51Rc can be reduced to half.

Further, according to the first substrate 51Rd, each electrode 47, 4 on each surface or the formation surface 9S, 15S is formed.
6 and the pattern density of the space region (the region where the electrodes are not arranged) are determined by the first substrate 51 described above.
Ra, 51Rb and 51Rc can be reduced. That is, the line width or the width (the length along the second direction D2) of each of the electrodes 47 and 46 is
It can be at least twice that of the first substrates 51Ra, 51Rb and 51Rc described above. In addition, the first substrate 51Rd is, for example, between two adjacent first or second address auxiliary electrodes 37T or 37B and between the adjacent first and second common address electrodes 36T, 36B in the first substrate 51Rc of FIG. Can be eliminated. For this reason, the space area present on the first substrate 51Rd has a wider width than the space area on the first substrate 51Rc, and the space area between the adjacent first and second address auxiliary electrodes 47T and 47B and the adjacent space area. Only the space area between the common address electrodes 46 is provided.

Therefore, even when the density of the lane 35 is increased due to the high definition of the AC type PDP, each electrode 47, 4
The formation of 6 is much easier than the first substrate 51Ra, 51Rb, 51Rc and the back panel 51RP (see FIG. 31) of the conventional AC type PDP. That is, the first substrate 5
According to 1Rd, a high yield can be achieved. Here, as a specific example, S having 3840 lanes
First substrate 5 capable of supporting XGA grade high definition panels
In the case of 1Rd, the first and second address auxiliary electrodes 47T,
The pattern formation of the 47B pattern and the pattern formation of the common address electrode 46 are performed using the address electrodes (FIG. 3) of a conventional VGA-grade AC type PDP having 1920 lanes.
(Corresponding to one address electrode 6P).

Furthermore, as described above, the first substrate 51Rd
Is narrow between two adjacent first address auxiliary electrodes 37T or between second address auxiliary electrodes 37B and between adjacent first and second common address electrodes 36T and 36B on the first substrate 51Rc in FIG. No space area. Therefore, the first substrate 51Rd according to Embodiment 4
According to the AC type PDP provided with the first substrate 51Rd, the first substrate 5 of FIG.
The formation of an electric field required to generate an address discharge is much easier than that of an AC PDP having 1Rc. Therefore, the AC type PDP including the first substrate 51Rc of FIG.
As compared with the above, it is possible to further increase the speed of the writing operation and reduce the load on the address electrode drive IC.

(Embodiment 5) FIG. 13 shows Embodiment 5 of the present invention.
5 is a longitudinal sectional view schematically showing a structure in a display area of a first substrate 51Re according to the first embodiment. As shown in FIG. 13, the first substrate 51Re includes first address auxiliary electrodes 57T and second address auxiliary electrodes alternately arranged on the front surface 9S of the rear glass substrate 9 in the second direction D2 which is the arrangement direction. 57B (also collectively referred to as “address auxiliary electrodes 57”), and the first and second address auxiliary electrodes 57T and 57B.
And a common address electrode 56 disposed on the surface 15S of the interlayer insulating layer 15 covering the semiconductor device.

In particular, the first substrate 51Re of FIG.
As can be seen from a comparison with the first substrate 51Rd, the first substrate 51Re has the same pattern as the first address auxiliary electrode 57T and the second address auxiliary electrode 57B when the substrate 51Re is viewed from the third direction D3. , And the pattern of the common address electrode 56 correspond to each surface or formation surface 9S, 15
S are arranged so as to substantially complement each other's space area. That is, the first substrate 51Re has almost no area corresponding to the gap in the second direction D2 between the electrodes 46 and 47 of the first substrate 51Rd in FIG.

More specifically, as shown in FIG. 13, the first address auxiliary electrode 57T extends from the position corresponding to the central axis in the first direction D1 of the lane Lm-2 on the surface 9S, for example. This is a strip-shaped electrode having a width reaching the position corresponding to the central axis of the adjacent lane Lm-1 in the same direction D1 and extending in the first direction D1. Similarly,
The second address auxiliary electrode 57B is, for example, from a position corresponding to the central axis with respect to the lane Lm on the surface 9S.
It is a strip-shaped electrode extending in the first direction D1 and having a width reaching an equivalent position with respect to the adjacent lane Lm + 1. At this time, the width (the length along the second direction D2) of both the first and second address auxiliary electrodes 57T, 57B and the space region between the adjacent electrodes 57T, 57B is substantially the same.
The interlayer insulating layer 15 is arranged so as to cover the address auxiliary electrode 57.

The common address electrode 56 has the same structure as the address auxiliary electrode 57. That is, as shown in FIG. 13, the common address electrode 56
5 from the position corresponding to the center axis of the lane Lm-1 on the surface 15S in the first direction D1 to the position on the surface 15S corresponding to the center axis of the adjacent lane Lm in the same direction D1. And a strip-shaped electrode extending in the first direction D1. At this time, the widths of both the common address electrode 56 and the space region between the adjacent same electrodes 56 are substantially the same. The widths of both the common address electrode 56 and the address auxiliary electrode 57 are substantially the same. Then, the overglaze layer 1 is formed so as to cover the common address electrode 56.
0 is arranged.

In the AC PDP having the first substrate 51Re according to the fifth embodiment, compared to the AC PDP having the first substrate 51Rd of FIG. 12, the width of each of the electrodes 56 and 57 is increased. It is easy to form an electric field for further generating the address discharge. Accordingly, the load on the address electrode drive IC can be further reduced.

Although the common address electrode 56 and the address auxiliary electrode 57 hardly overlap, the capacitance between the electrodes 56 and 57 is smaller than that of the AC type PDP having the first substrate 51Rd in FIG. Increase slightly. However, the influence of the electric field formation in the discharge cell (indicated by α in the figure) and the capacitance (indicated by β in the figure) on the amount of overlap between the common address electrode and the address auxiliary electrode.
According to FIG. 14, which schematically shows the correlation between the two electrodes 5
When there is a gap between 6, 57, it can be seen that the rate of increase of the electric field formation influence with the decrease in the gap amount is larger than that of the capacitance. Further, when the electrodes 56 and 57 overlap each other, it can be seen that the capacitance sharply increases with the increase of the overlap amount, but the influence of the electric field formation hardly changes. That is, according to FIG. 14, when there is no gap between the common address electrode and the address auxiliary electrode and they do not overlap, A
Driving of the C-type PDP, in particular, the writing operation can be performed at the highest speed. Therefore, the first substrate 51 according to the fifth embodiment
The AC type PDP provided with Re can further increase the speed of the write operation as compared with the AC type PDP provided with the first substrate 51Rd according to the fourth embodiment.

Even if the widths of the common address electrode and the address auxiliary electrode arranged over the adjacent lane areas are different from each other, there is no gap between the two electrodes, and As long as they do not overlap, the above-described effect can be obtained to a certain extent. At this time, when the width of both the common address electrode and the address auxiliary electrode is the same, that is, in the case of the structure shown in FIG.

(Embodiment 6) The common address electrode 56 and the address auxiliary electrode 5 of the first substrate 51Re of FIG.
7 are formed by a pattern forming process which is separate from each other. For this reason, if an alignment shift occurs during the pattern formation of the electrodes 56 and 57, an overlap in the third direction D3 and the above-described gap may occur between the common address electrode 56 and the address auxiliary electrode 57. . In such a case, the above-described effects may not be effectively exhibited.

In the sixth embodiment, a practical method of manufacturing the first substrate 51Re shown in FIG. 13, particularly a method of forming the common address electrode 56 and the address auxiliary electrode 57 will be described.

Hereinafter, an example of a method for manufacturing the first substrate 51Re will be described as a first manufacturing method according to the sixth embodiment with reference to FIGS. 15 to 18 are longitudinal sectional views for explaining each step in the manufacturing method. As will be described later, the present manufacturing method is characterized in that the common address electrode 56 is patterned by using a photoengraving technique using a conductive paste having negative photosensitive characteristics as a raw material of the common address electrode 56.
Details will be described below.

(First Step According to First Manufacturing Method) In the first step, as shown in FIG. 15, an address auxiliary electrode 57 is formed at a predetermined position on the surface 9S with a predetermined shape. Further, the rear glass substrate 9 in a state where the uniform translucent interlayer insulating layer 15 is formed so as to cover the electrode 57 and the surface 9S is prepared. The address auxiliary electrode 57 is formed by, for example, a screen printing method, a sand blast method,
It is formed using a forming method such as a sputtering method. Further, the interlayer insulating layer 15 is formed by, for example, printing a low dielectric glass paste over the entire surface 9S by a screen printing method,
Thereafter, it is formed by a method equivalent to the method of forming the overglaze layer, such as a method of drying and sintering.

(Second Step According to First Manufacturing Method) In the second step, first, a conductive paste 156 having negative photosensitivity (see FIG. 16) is applied on the entire surface 15S of the interlayer insulating layer 15. It is dried by applying in the same manner and passing through an appropriate drying treatment.

Thereafter, as shown in FIG. 16, an appropriate amount of light from an exposure light source optimal for the photosensitive characteristics of the conductive paste is vertically irradiated from the surface 9S2 opposite to the surface 9S of the rear glass substrate 9. At this time, since the back glass substrate 9 and the interlayer insulating layer 15 have a light transmitting property, the (dry film of) the negative photosensitive conductive paste 156 is exposed using the pattern of the address auxiliary electrode 57 having the light shielding property as a mask. .
That is, the negative photosensitive conductive paste 156 is exposed and cured in a pattern shape obtained by inverting the electrode pattern of the address auxiliary electrode 57 (hereinafter, referred to as an “inversion pattern of the address auxiliary electrode 57”).

(Third Step According to First Manufacturing Method) Next,
In the third step, the negative photosensitive conductive paste (dry film)
156 by subjecting it to an appropriate development process.
Only the portions that were not photocured in the process are selectively removed. Thereby, the negative photosensitive conductive paste 1 of FIG.
As shown in FIG. 17, a negative photosensitive conductive paste 256 having a reverse pattern of the address auxiliary electrode 57 remains on the surface 15S.

(Fourth Step According to First Manufacturing Method) Then, in the fourth step, the negative-type photosensitive conductor paste (dry film) 256 shown in FIG. Is completed (see FIG. 18).

According to the first substrate manufacturing method including the first to fourth steps according to the first manufacturing method described above, the relative alignment between the common address electrode 56 and the address auxiliary electrode 57 shown in FIG. Deviation can be effectively avoided.

Next, an example of another manufacturing method of the first substrate 51Re will be described as a second manufacturing method according to the sixth embodiment with reference to FIGS. 19 to 21 are longitudinal sectional views for explaining each step in the manufacturing method.

(First Step According to Second Manufacturing Method) In the first step, first, the back glass substrate 9 with the address auxiliary electrode 57 and the interlayer insulating layer 15 shown in FIG. prepare.

(Second Step According to Second Manufacturing Method) In the second step, a resist film 101 having a positive photosensitive characteristic is formed so as to cover the entire surface 15S of the interlayer insulating layer 15.
(See FIG. 19) is applied uniformly and dried. Then, as shown in FIG. 19, an appropriate amount of light from an exposure light source optimal for positive photosensitive characteristics is vertically irradiated from the surface 9S2 of the rear glass substrate 9 opposite to the surface S. At this time, since the back glass substrate 9 and the interlayer insulating layer 15 have a light transmitting property, the (dry film of) the positive photosensitive resist 101 is exposed using the pattern of the address auxiliary electrode 57 having the light shielding property as a mask. . That is, the inverted pattern portion of the address auxiliary electrode 57 in the positive photosensitive resist 101 is exposed and softened.

(Third Step According to Second Manufacturing Method) Then, in the third step, as shown in FIG. 20, the exposed resist film 101 is subjected to an appropriate developing treatment,
In the third step, only the portions softened by light are selectively removed. Thus, the resist 201 having the same pattern shape as the address auxiliary electrode 57 remains on the surface 15S.

(Fourth Step According to Second Manufacturing Method) Next,
In the fourth step, as shown in FIG. 21, a predetermined conductor material 356 is formed on the surface 15S on which the resist 201 is formed. At this time, the conductive material 356 is formed by a film forming method such as a sputtering method, a vacuum evaporation method, and a plating method. Then, the electrode pattern of the common address electrode 56 shown in FIG. 18 is completed by removing the conductive material 356 on the resist 201 together with the resist 201 by a lift-off method.

According to the method of manufacturing the first substrate including the first to fourth steps according to the above-described second manufacturing method, the common address electrode 56 shown in FIG. Relative misalignment between the address and the address auxiliary electrode 57 can be effectively avoided.

Note that both the first and second manufacturing methods described above relate to the manufacture of the common address electrode 56 and the address auxiliary electrode 57 in the display area. For this reason, both the first and second manufacturing methods require the lead portion areas AR21, AR21, in which the electrode patterns of the electrodes 56, 57 do not necessarily exist at positions complementary to each other in the third direction D3.
AR22 (see FIG. 7 or FIG. 9) and the terminal area AR3.
It cannot be applied to the formation of the electrode patterns in AR31 and AR32 (see FIG. 7 or FIG. 9).
However, high-precision alignment is not required for the arrangement positions of the electrodes 56 and 57 over the entire lead portion regions AR21 and AR22 and the terminal portion regions AR3, AR31 and AR32. Therefore, the electrode pattern of the common address electrode 56 in the regions AR21, AR22, AR3, AR31, and AR32 can be easily formed in a separate manufacturing process capable of reliably performing the connection between the lead portion region of the electrode 56 and the display area. Note that it can be formed.

(Embodiment 7) FIG.
FIG. 5 is a longitudinal sectional view schematically showing a structure in a display area of a first substrate 51Rf according to the first embodiment. As shown in FIG. 22, the first substrate 51Rf includes a first common address electrode 66T and a second common address electrode 66B (collectively, “common address electrode 66”) disposed on the front surface 9S of the rear glass substrate 9.
) And the first address auxiliary electrode 67T and the second address auxiliary electrode 67B (collectively, "address auxiliary electrode 6").
7 "). Specifically, the electrodes 37T and 37B are located at positions corresponding to the respective positions of the first and second address auxiliary electrodes 37T and 37B of the first substrate 51Rc shown in FIG. Equivalent first and second address auxiliary electrodes 67T and 67B are arranged. Further, the arrangement positions of the first and second common address electrodes 36T and 36B of the first substrate 51Rc in FIG.
First and second common address electrodes 66T and 66B equivalent to the electrodes 36T and 36B are arranged at the positions projected above. The overglaze layer 10 is disposed so as to cover the common address electrode 66, the address auxiliary electrode 67, and a predetermined range of the surface 9S. At this time,
The overglaze layer 10 is arranged at least in the display area.

As described above, since the common address electrode 66 and the address auxiliary electrode 67 are arranged on the same surface 9S on the first substrate 51Rf, both electrodes 66 and 67 can be formed collectively. Therefore, when forming both electrodes 66 and 67 collectively, misalignment between the patterns of both electrodes 66 and 67 can be effectively avoided. Furthermore, according to the first substrate 51Rf, the number of manufacturing steps of the first substrate can be significantly reduced as compared with the above-described method of manufacturing the first substrates 51Ra, 51Rb, 51Rc, 51Rd, and 51Re. Conventional AC type PDP5 shown in FIG.
There is an advantage that the number of manufacturing steps on the rear glass substrate 9P side in 1P can be made approximately equal to the number of manufacturing steps.

(Embodiment 8) The above-described first substrate 51Rf
When the common address electrode 66 and the address auxiliary electrode 67 are collectively formed, the number of electrodes to be formed on the surface 9S is twice as large as that of the address electrode 6P in the conventional AC PDP 51P. Requires density patterning technology. Therefore, in the eighth embodiment, a first substrate having a structure that does not require such a high-density pattern forming technique will be described.

FIG. 23 shows the structure of the first substrate 5 according to the eighth embodiment.
It is a longitudinal cross-sectional view which shows typically the structure in the display area of 1Rg. As shown in FIG. 23, the first substrate 51Rg
Includes a common address electrode 76, a first address auxiliary electrode 77T, and a second address auxiliary electrode 77B (also collectively referred to as an "address auxiliary electrode 77") disposed on the front surface 9S of the rear glass substrate 9. Specifically, the surface 9
In S, the first according to the fourth embodiment shown in FIG.
The first and second address auxiliary electrodes 47T of the substrate 51Rd,
The electrodes 47T, 47T,
47B, the first and second address auxiliary electrodes 77T,
77B are arranged. Further, the first substrate 51 of FIG.
A common address electrode 76 equivalent to the Rd common address electrode 46 is arranged at a position where the arrangement position of the common address electrode 46 is projected on the surface 9S. Then, the common address electrode 76
The overglaze layer 10 is disposed so as to cover the address auxiliary electrode 77 and a predetermined range of the surface 9S. At this time, the overglaze layer 10 is arranged at least in the display area.

According to the first substrate 51Rg, the pattern density of the common address electrode 76 and the address auxiliary electrode 77 can be made substantially equal to that of the conventional AC PDP 51P (see FIG. 31). Therefore, even when both electrodes 76 and 77 are formed collectively, a high-density pattern forming technique is not required. Of course, the same effects and advantages as those of the first substrate 51Rf according to the seventh embodiment can be obtained.

FIG. 24 is a plan view schematically showing the arrangement of the electrodes 76 and 77 on the first substrate 52Rg.
As shown in FIG. 24, the common address electrode 76 is connected to the lower terminal area AR32 via the lower extraction area AR22.
The terminal 763 for the common address electrode 76 is formed at the end in the terminal area AR32. On the other hand, the address auxiliary electrode 77 is connected to the upper terminal area AR through the upper lead area AR21.
31 is extended. Then, the second address auxiliary electrode 77B is disposed in the upper terminal area AR31 and corresponds to the common electrode section 7B2 corresponding to the common electrode section 17B2 in FIG.
7B2 (wiring portion). In addition, the second
The second address auxiliary electrode 77B is connected to the common electrode portion 77B2.
, Or, for example, the terminal 1 in FIG.
A terminal corresponding to 7B3 may be separately provided. On the other hand, the first address auxiliary electrode 77T is connected to the upper terminal area AR31.
Of the electrode 77T or the terminal 77T3
24 and an output terminal of the drive circuit for the electrode 77T (not shown in FIG. 24).

According to such a wiring pattern, since the terminals of the electrodes 76 and 77 are dispersed above and below the rear glass substrate 9, it is possible to effectively avoid high-density mounting in the terminal area AR31 and AR32. Can be.

(Modification 1 of Embodiment 8) In this modification 1, the structure of the first and second address auxiliary electrodes 77T and 77B of the first substrate 51Rg in the lead portion region and the terminal portion region is described. Another example will be described with reference to FIGS. FIG. 25 is an enlarged plan view of an essential part for explaining such a structure, and FIG. 26 is a diagram when a vertical cross section taken along line II in FIG. 25 is viewed from the direction of the arrow.

As shown in FIGS. 25 and 26, the second address auxiliary electrode 77B extends from the display area AR1 (see FIG. 24) to the upper lead-out area AR21. 77B2. Then, a second portion extending from a desired position of the common electrode portion 77B2 into the terminal portion region AR31.
A terminal 77B3 for the address auxiliary electrode 77B is arranged. Then, on the front surface 9S of the rear glass substrate 9, from the boundary between the lead-out area AR21 and the terminal area AR31 to the draw-out area AR21 or the display area AR.
An insulating film 75 is arranged in a predetermined area on one side so as to cover the electrodes arranged in the area.

Then, on the surface 75S of the insulating layer 75 which is not in contact with the surface 9 of the back glass substrate 9, a common electrode portion (wiring portion) 77T equivalent to the common electrode portion 17T2 shown in FIG.
2 are arranged. The common electrode portion 77T2 and the first
The address auxiliary electrode 77T is partially connected to the surface 75.
They are connected by a wiring unit 177T arranged on S. Then, a terminal 77T3 for the first address auxiliary electrode 77T extending from a desired position of the common electrode portion 77T2 toward the inside of the terminal portion region AR31 is arranged.

According to this structure, the terminal 77T3,
77B3 to the first and second address auxiliary electrodes 77T, 7
The relay wiring up to the output terminal of each drive circuit for 7B can be simplified as compared with the case of the structure shown in FIG. That is, in the structure shown in FIG. 24, it is necessary to prepare (one or more) FPCs corresponding to the number and arrangement pitch of the terminals 77T3 for the first address auxiliary electrode 77T. Moreover, as described above, the path must be commonly connected between the terminal 77T3 and the output terminal of the drive circuit for the first address auxiliary electrode 77T. Further, it is necessary to mount the terminal of the FPC and the terminal 77T3 while positioning them.

On the other hand, according to the structure shown in FIGS. 25 and 26, the first and second address auxiliary electrodes 77T, 7T
Any of the terminals 77T3 and 77B3 of 7B can be formed at a desired position and in a desired number.
Therefore, the terminals 77T3, 77B3 and the electrodes 77T, 77B3
As the relay wiring between the output terminal of each driving circuit for
A flat cable (FFC) that is less expensive than a PC can be used. At this time, the connection between the terminals 77T3 and 77B3 and the flat cable does not require an advanced positioning process. As described above, according to the structure shown in FIG. 25, the relay wiring can be simplified as compared with the structure shown in FIG. As a result, there is also an advantage that the material cost and the manufacturing cost of the relay wiring can be significantly reduced.

Note that, instead of the insulating film 75, the overglaze layer 10 (for example, see FIG.
R21, the overglaze layer 10
A structure equivalent to the structure shown in FIG. 25 may be formed by providing a structure such as a contact hole. In such a case, it is not necessary to separately provide a step of forming the insulating film 75.

(Modification 2 according to the eighth embodiment) In the second modification, the first substrate 51Rg according to the eighth embodiment is provided with an AC type P which can support a so-called upper and lower block parallel address system.
The arrangement of each electrode when applied to DP will be described. In the second modification, it is assumed that the common address electrode 76 of the first substrate 51Rg is vertically divided at the center of the display area AR1 like the common address electrode 16 shown in FIG. Also, upper and lower display areas AR11, AR1
2 (see FIG. 9) are connected to the upper or lower terminal area AR31, A
It shall be provided in R32.

At this time, when both the terminals for the first and second address auxiliary electrodes 77T and 77B are provided concentrated on one of the upper or lower terminal area AR31 or AR32, the terminal for the common address electrode 76 is provided. The arrangement density or pattern density of the terminals in the area AR31 or AR32 including the area 763 becomes extremely high. Therefore, it is desirable to provide the terminals for the first and second address auxiliary electrodes 77T and 77B in separate terminal area AR31 and AR32.

Further, for example, as shown in FIG. 24, the lead portion area AR22 and the terminal section area AR32 (in this case,
The arrangement interval (pitch) of the common address electrodes 76 in the lower block regions 22 and 32 in FIG. 9) is set smaller than that in the display area AR1. In such a structure, when the address auxiliary electrodes 77 are formed to extend in the same area AR22, AR32 as they are, a plurality of address auxiliary electrodes 77 (up to the common electrode portions 77T2, 77B2 (see, for example, FIG. 7)) are formed. This leads to a region where the common address electrode 76 (terminal thereof) is dense. Such a high-density wiring pattern is not preferable from the viewpoint of forming technology and mounting technology.

One of the structures that can solve such a problem is as follows.
A first substrate 51Rg according to the second modification will be described with reference to FIGS. FIG. 27 is an enlarged plan view of the vicinity of the upper lead-out area AR21 and the upper terminal area AR31, corresponding to FIG. 25 described above. FIG. 28 is a vertical sectional view taken along line II-II in FIG. FIG. Here, as shown in FIG. 27, the first lead portion area AR21 and the upper terminal section area AR31 have the first
The structure in the case where the address auxiliary electrode 77T is drawn out will be described. The structure of the lower lead-out area AR22 and the lower terminal area AR32 (both see, for example, FIG. 9) from which the second address auxiliary electrode 77B is drawn out is the area AR2
1, the following description regarding AR31 is only incorporated.

As shown in FIG. 27, the common address electrode 7
6 and the terminal area AR3
24. The structure in 1 is the same as the structure in the lower lead portion area AR32 and the terminal section area AR32 in FIG.

As shown in FIGS. 27 and 28, the first address auxiliary electrode 77T extends from the display area AR1 to a predetermined position in the lead portion area AR21 (the common address electrode 76T).
Is preferably a non-dense area). Then, an insulating layer 175 equivalent to the above-described insulating layer 75 shown in FIGS.
It is arranged so as to cover a part of the common address electrode 76 in R21.

Then, the back glass substrate 9 of the insulating layer 175 is formed.
Of the common electrode portion 7 on the surface 175S that does not contact the surface 9S
7T2 is arranged. The common electrode portion 77T2 and the first address auxiliary electrode 77T are partially connected to the wiring portion 277T (FIGS. 25 and 2).
6 (corresponding to the wiring portion 177T).
Then, a terminal 77T3 for the first address auxiliary electrode 77T is provided which extends from the common electrode portion 77T2 to a region within the terminal portion region AR31 where the terminals 763 for the common address electrode 76 are not densely packed.

At this time, similarly to the above-described first modification, the overglaze layer 10 (see, for example, FIG. 23) extended to the lead-out area AR21 is formed in an appropriate shape, so that the same layer 10 is insulated. A role equivalent to that of the film 175 may be given.

The first modification according to the second modification having the above-described structure is described.
According to the substrate 51Rg, it is possible to reliably avoid the above-described problems associated with the increase in the density of wiring in the lead portion region and the terminal portion region.

The structure of the address auxiliary electrode in the above-mentioned lead portion area and terminal area is the same as that of the terminals 77T3, 77 for the first and second address auxiliary electrodes 77T, 77B.
The present invention is applicable to a case where B3 is provided in separate terminal area, and is not limited to a case where the shape of the common address electrode 76 corresponds to the upper and lower block parallel address system.

Ninth Embodiment In the ninth embodiment, FIG. 29 shows a driving method in the sustain period S when the AC PDP provided in each of the first substrates is driven by the driving method according to the base technology. It will be described using FIG. FIG. 29 is a timing chart showing a waveform of a voltage applied to each electrode during the sustain period S in the driving method according to the ninth embodiment. 29A to 29D show the voltages VT, VB, VAk (k: 1 to 1) applied to the first address auxiliary electrode, the second address auxiliary electrode, and the common address electrode PAk, respectively.
The timing chart of j) is shown. 29 (d) shows a voltage VX0 commonly applied to all sustain electrodes X1 to XN, and FIG. 29 (e) shows a voltage VY0 commonly applied to all scan electrodes Y1 to YN. . Note that the voltage V
Timing charts of X0 and voltage VY0 are the same as (b) and (c) to (e) in FIGS. 2 and 3 according to the base technology. Here, the AC PDP according to Embodiment 1 shown in FIG. 6 described above will be described as an example.

As shown in FIG. 29, in the sustain period S0,
By applying the same voltage Va as the voltages VT, VB, and VPAk to the first and second address auxiliary electrodes and the common address electrode PAk, the sustain period S according to the prerequisite technique is applied.
(See FIGS. 1 to 3). By applying the same voltage Va to all the electrodes of the first substrate in this manner, the voltage Va applied to the address electrodes is applied to the electrode pair X in a manner similar to the driving method according to the base technology.
The starting voltage of the surface discharge DC2 between n and Yn (see FIG. 5) can be minimized. That is, when the sustain pulse Vs is applied to the sustain electrode Xn or the scan electrode Yn, the discharge space 5 near the surface on the discharge space 51S side of the phosphor 8 in FIG.
The potential in 1S is applied to the center of an internal gap G (a (three-dimensional) region between mutually facing edges of the electrodes Xn and Yn forming a pair, in the discharge space 51S near the cathode film 4; see FIG. 5). It can be made to substantially match the potential near the portion corresponding to the axis. As a result, the electric field distribution in the discharge space 51S above the internal gap G can be made symmetrical, so that the electrode pair Xn, Xn,
It is possible to start the surface discharge DC2 between Yn.
Therefore, according to the above-described voltage setting, an efficient surface discharge or sustain discharge DC2 can be obtained.

(Embodiment 10) In Embodiment 10,
With reference to FIG. 30, a description will be given of a driving method of an AC type PDP provided with each of the above-described first substrates, which is capable of suppressing and removing a moving image false contour at the time of displaying an image. FIG. 30 is a diagram for explaining a subfield division mode of one screen and each period in each subfield in the present driving method. Here, the case of displaying an image of 256 gradations will be described as an example.

As shown in FIG. 30, in the present driving method, 1
The video display time for the screen is divided into subfields SF1 to SF7 equivalent to the driving method according to the base technology (see FIG. 1) and subfields SF8A and SF8B which are features of the present driving method. That is, in the present driving method, the subfield SF8 in which the number of sustain pulses is the largest in the sustain period S of the driving method according to the base technology is 2
It is divided into two subfields SF8A and 8B.
Then, as shown in FIG. 30, the nine subfields are subfields SF1, SF2, SF8A, SF
3, SF4, SF8B, SF5, SF6, and SF.

As shown in FIG. 30, subfield SF
Each of the subfields 1 to SF7 includes an erasing period R in which the same operation as one of the predetermined periods in the erasing period RA or RB according to the base technology is performed, It includes a period in which the address period AD0 (see FIG. 8) is executed, and a sustain period S in which the driving method described in the ninth embodiment is executed subsequent to the address period AD0. In the erasing period R (RA or RB), a voltage capable of performing a predetermined erasing operation according to the base technology is applied to the common address electrode and the address auxiliary electrode.

On the other hand, the subfield SF8A has an address period AD1 consisting of only the first period AD1 of the address period AD0 instead of the address period AD0. On the other hand, in subfield SF8B,
An address period AD2 including only the second period AD2 of the address period AD0 is provided instead of the address period AD0. The erasing period and the sustaining period of each of the subfields SF8A and SF8B are the same as those of the subfields SF1 to SF7. At this time, the subfields SF8A, SF
In any sustain period S0 of FIG. 8B, the number of sustain pulses is equal to the number of subfields SF8 (see FIG. 1) according to the base technology.
And the same number as in.

Subfield SF8 having such a configuration
In A and SF8B, in the address period AD1 or AD2, the entire screen or all the lanes 35 (for example, see FIG. 6)
Address operation is performed only for half of all the discharge cells belonging to. For this reason, in the sustain period S, the image display is performed on the discharge cells belonging to the half lane 35 of the total number. Further, the sustain period S0 of the subfield SF7
In this case, the sustain discharge of all the discharge cells (belonging to all the lanes 35), that is, the image display, is performed with about half the number of the sustain pulses in the subfields SF8A and SF8B. Therefore, on average, three subfields SF8
A, SF8B and SF7 have the same light emission intensity, and have the largest weight or rank in a series of nine subfields. Therefore, the subfield SF
By arranging 8A, SF8B, and SF7 so as not to be biased within the video display time for one screen as shown in FIG. 30, it is possible to improve the pseudo contour of the moving image.

The first substrate of each AC type PDP according to the first to tenth embodiments may have a structure not having the overglaze layer 10.

[0179]

(1) According to the first aspect of the present invention, when driving the AC surface discharge type plasma display panel, the first to s-th common address electrodes are common (identical) to each group. A voltage and a plurality of j-th
When a discharge is generated in a discharge cell belonging to a predetermined lane region by applying a common (identical) voltage between groups to the address auxiliary electrode, the number of drive circuits for supplying a drive voltage to the common address electrode Is sufficient for the number of groups of the common address electrodes. The driving circuit for driving the address auxiliary electrodes of the entire panel is s.
It only needs an individual. As described above, since it is not necessary to provide the same drive circuit for each address electrode as in the conventional drive method, an AC surface discharge type plasma display which can significantly reduce the cost related to the drive circuit is provided. You can get a panel.

Further, in the above case, even when the common address electrode terminal for connecting to the output terminal of the common address electrode drive circuit is provided on the first substrate side, the number of the common address electrode terminal is the same as the above. The same number as the number of groups is sufficient. Similarly, even when the address auxiliary electrode terminal for connecting to the output terminal of the address auxiliary electrode drive circuit of the entire panel is provided on the first substrate side, the electrically independent number is s. I'm done. As described above, the arrangement density of the two terminals is significantly reduced as compared with that of the address electrode terminal of the conventional plasma display panel. Accordingly, since the mounting density of each terminal of the AC surface discharge type plasma display panel and each output terminal of the drive circuit is remarkably reduced as compared with the conventional plasma display panel, the manufacturing cost can be reduced.

Therefore, according to the first aspect of the present invention,
An AC surface discharge plasma display panel with higher definition can be obtained, and the AC surface discharge plasma display panel can be provided at low cost.

(2) According to the second aspect of the present invention, the first
To the s-th common address electrode, and the plurality of j-th address auxiliary electrodes are commonly connected to the entire AC surface discharge type plasma display panel, so that the above-mentioned effect (1) is exhibited. It is possible to provide an AC surface discharge type plasma display panel which can be used.

(3) According to the third aspect of the invention, the common address electrode and the address auxiliary electrode are arranged on different planes in the display area. Therefore, the density of the electrode patterns on one plane is lower than that in the case where both electrodes are arranged on the same plane. Therefore, an electrode pattern having a predetermined shape can be formed more reliably than when both electrodes are collectively formed on the same plane.

(4) According to the fourth aspect of the present invention, as compared with the case where the common address electrode and the address auxiliary electrode have a portion overlapping in the direction perpendicular to the surface of the substrate provided on the first substrate, The electric field by each voltage applied to the electrode farther from the substrate can be used more effectively when forming the electric field in the discharge space. Therefore, when appropriately setting the voltage applied to each electrode, the address discharge and the sustain discharge in the predetermined discharge cell can be more reliably generated as compared with the plasma display panel having the overlapping portion. .

Further, according to the invention of claim 4, the capacitance between the common address electrode and the address auxiliary electrode is:
It is smaller than when both electrodes have overlapping portions. Therefore, as compared with the plasma display panel having a structure having the above-mentioned overlapping portion, the writing operation in the address period can be speeded up.

(5) According to the fifth aspect of the invention, the width of each of the common address electrode and the address auxiliary electrode (the length in the electrode arrangement direction) is different from that of the AC surface discharge type plasma display panel according to the fourth aspect. ) Can be set to the maximum. Therefore, the influence of the electric field by the voltage applied to each electrode on the electric field formation in the discharge space can be made larger than that of the AC surface discharge type plasma display panel according to the fourth aspect. Therefore, since the voltage applied to each electrode can be reduced, the load on the drive circuit for the common address electrode can be reduced. At this time, since a large increase in the capacitance between the common address electrode and the address auxiliary electrode does not occur, the address operation during the address period can be more efficiently performed as compared with the AC surface discharge type plasma display panel according to claim 4. Can be executed at high speed.

(6) According to the invention of claim 6, when the common address electrode and the address auxiliary electrode are formed collectively, the number of steps for forming both electrodes can be reduced.

(7) According to the invention of claim 7, at least a part of the j-th address auxiliary electrode belonging to a different group is not arranged in each of two adjacent lane regions. Therefore, for example, for two adjacent lane areas, an address discharge is generated in the discharge space of a discharge cell belonging to one lane area based on image data, and a discharge cell belonging to the other lane area is generated. Even when driving so as not to generate an address discharge in the discharge space of the other lane, compared with the structure in which both j-th address auxiliary electrodes are arranged in each of two adjacent lane regions, The occurrence of erroneous write discharge in the discharge cells belonging to the region can be largely suppressed.

(8) According to the invention of claim 8, the plurality of address auxiliary electrodes are classified into two types of address auxiliary electrodes. Therefore, with the AC surface discharge type plasma display panel having a very simple structure, the above-described (1) to (1)
The same effect as (7) can be obtained.

(9) According to the ninth aspect of the present invention, when an address discharge is generated in a discharge cell in a lane region to which one j-th address auxiliary electrode of a plurality of j-th address auxiliary electrodes belongs, it is adjacent. The electric field due to the voltage applied to the other j-th address auxiliary electrode belonging to the lane region assists in forming the electric field required for generating the address discharge. For this reason,
The generation of the address discharge can be further facilitated. Therefore, the load related to the switching operation of the common address electrode drive circuit can be reduced. Further, the speed of the write operation can be increased.

(10) According to the tenth aspect,
With an AC surface discharge type plasma display panel having a very simple structure, the same effects as the above (1) to (6) and (9) can be obtained.

(11) According to the eleventh aspect,
Most of the influence of the electric field due to the voltage applied to the common address electrode on the formation of the electric field in the discharge space can be concentrated on the discharge cell to which the common address electrode belongs. Therefore, when a regular address discharge is generated in a predetermined discharge cell, the occurrence of an erroneous address discharge in a discharge cell adjacent to the discharge cell can be effectively suppressed.

(12) According to the twelfth aspect,
The effect of the electric field caused by the voltage applied to the electrodes having the pattern shape over the adjacent lane regions on the formation of the electric field in the discharge space is such that the electrodes of the same type (at least one of the common address electrode and the address auxiliary electrode) are adjacent to each other. It is much stronger than the electric field in the structure (see claim 11) arranged in each of the lane regions. For this reason, the electric field necessary for generating the address discharge can be more easily formed, and the address discharge can be easily generated. Therefore, each voltage related to the address discharge can be reduced, so that the load of the common address electrode drive circuit can be further reduced and the address operation can be further speeded up.

In addition, a structure in which the above-mentioned predetermined electrodes are arranged in each of the adjacent lane regions (see claim 11)
, The number of the predetermined electrodes can be halved. Therefore, by reducing the pattern density of the predetermined electrode, it is possible to suppress or eliminate the inconvenience relating to the high-density electrode pattern.

(13) According to the thirteenth aspect,
The respective wiring portions of the first and second address auxiliary electrodes and the respective electrode terminals are arranged in predetermined regions opposite to each other via the display area. Therefore, the wiring pattern of the address auxiliary electrode outside the display area can be formed in a very simple shape. Further, even when a plurality of first or second address auxiliary electrodes are commonly connected outside the display area, a wiring pattern for the common connection can be formed in a very simple shape. At this time, since it is not necessary to provide a terminal for each of the plurality of electrodes, the mounting density of each terminal and an output terminal of a drive circuit for the electrode can be significantly reduced.

(14) According to the fourteenth aspect,
Since the wiring portion of each electrode is three-dimensionally arranged via the insulating layer, it is possible to suppress the complexity of the wiring pattern outside the display area. At this time, a large degree of freedom can be given to the arrangement positions of the terminals for each electrode, so that high-density mounting between each terminal and the output terminal of the drive circuit can be avoided.

(15) According to the fifteenth aspect,
The effects of any of the above (1) to (14) are exerted, and a plasma display device with higher definition can be provided.

(16) According to the sixteenth aspect,
In the address period, the same voltage is applied to each of the first to s-th common address electrodes in each group, so that the number of drive circuits for supplying a drive voltage to the common address electrodes is sufficient to be the number of groups of the common address electrodes. That is, unlike the conventional driving method, it is not necessary to provide a driving circuit for each common address electrode, so that the cost of the driving circuit can be significantly reduced.

Furthermore, the number of terminals for the common address electrode for connecting the output terminals of the drive circuit is sufficient with the number of groups. That is, the arrangement density of the terminals can be significantly reduced as compared with the conventional plasma display panel. For this reason, the mounting density of the terminals of the AC surface discharge type plasma display panel to which the driving method is applied and the output terminal of the driving circuit is greatly reduced as compared with the case of the conventional plasma display panel, and the manufacturing cost is reduced. Can also be reduced.

Therefore, according to the sixteenth aspect,
Even a plasma display device including the plasma display panel with higher definition can be provided at low cost.

(17) According to the seventeenth aspect,
Only the discharge cells belonging to the lane area to which both the common address electrode to which the first voltage is applied and the address auxiliary electrodes to which the third voltage is applied are generated independently of the other discharge cells, thereby reliably generating the address discharge. be able to.

(18) According to the eighteenth aspect,
The address operation in the address period can be performed on all the discharge cells of the AC surface discharge type plasma display panel. Therefore, the above-mentioned (16) can also be applied to a high-definition AC surface discharge type plasma display panel.
Alternatively, it is possible to execute the write operation while exhibiting the effect of (17).

At this time, the driving circuit for driving the address auxiliary electrodes of the whole plasma display panel is s.
It only needs an individual. Therefore, the cost of the driving circuit can be further reduced. Similarly, even when the address auxiliary electrode terminal for connecting to the output terminal of the address auxiliary electrode drive circuit of the whole plasma display panel is provided on the first substrate side, the electrically independent number thereof is Only s pieces are needed. For this reason, since the arrangement density of the two terminals can be significantly reduced than that of the address electrode terminals in the conventional plasma display panel, it is possible to further promote the reduction of the manufacturing cost described above. it can.

(19) According to the nineteenth aspect,
For example, when a plurality of lane areas are classified into first and second lane areas, both subfields having an address period in which an address discharge is generated only in discharge cells belonging to the first or second lane area are maintained. In the case where the subfield is set to have a high light emission intensity in the period and is arranged so as not to be temporally biased within the video display time for one screen, the pseudo contour of the moving image can be improved.

(20) According to the twentieth aspect,
The discharge starting voltage of the surface discharge between the electrode pair can be minimized. As a result, an efficient sustain discharge can be obtained.

(21) According to the twenty-first aspect,
The effects of any one of the above (16) to (20) are exhibited, and it is possible to provide a plasma display device with higher definition.

(22) According to the twenty-second aspect,
The common address electrode and the address auxiliary electrode on the first substrate of the AC surface discharge type plasma display panel according to the fifth aspect can be formed without causing misalignment.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a subfield division mode of one screen and each period in each subfield in a driving method of an AC type PDP as a base technology of the present invention.

FIG. 2 is a timing chart showing a waveform of a signal applied to each electrode in a subfield in a method of driving an AC PDP as a base technology of the present invention.

FIG. 3 is a timing chart showing a waveform of a signal applied to each electrode in a subfield in another driving method of an AC type PDP as a base technology of the present invention.

FIG. 4 is a diagram for explaining a form of a counter discharge between a scanning electrode and an address electrode.

FIG. 5 is a diagram for explaining a form of surface discharge between an electrode pair.

FIG. 6 is a longitudinal sectional view schematically showing a structure in a display area of the AC type PDP according to the first embodiment.

FIG. 7 is a plan view schematically showing an arrangement of electrodes on a first substrate according to the first embodiment.

FIG. 8 is a timing chart showing a waveform of a voltage applied to each electrode during an address period in the method of driving an AC PDP according to the first embodiment.

FIG. 9 is a plan view schematically showing an arrangement of electrodes on a first substrate according to a first modification of the first embodiment.

FIG. 10 is a longitudinal sectional view schematically showing a structure in a display area of a first substrate according to a second embodiment.

FIG. 11 is a longitudinal sectional view schematically showing a structure in a display area of a first substrate according to a third embodiment.

FIG. 12 is a longitudinal sectional view schematically showing a structure in a display area of a first substrate according to a fourth embodiment.

FIG. 13 is a longitudinal sectional view schematically showing a structure in a display area of a first substrate according to a fifth embodiment.

FIG. 14 is a diagram schematically showing a correlation between an overlap amount between a common address electrode and an address auxiliary electrode, and a capacitance and an influence of electric field formation in a discharge cell.

FIG. 15 is a longitudinal sectional view for describing each step in a first method of manufacturing a first substrate according to a sixth embodiment.

FIG. 16 is a longitudinal sectional view for describing each step in a first method for manufacturing a first substrate according to a sixth embodiment.

FIG. 17 is a longitudinal sectional view for describing each step in a first method of manufacturing a first substrate according to a sixth embodiment.

FIG. 18 is a longitudinal sectional view for describing each step in a first method of manufacturing a first substrate according to a sixth embodiment.

FIG. 19 is a longitudinal sectional view for describing each step in a second method for manufacturing the first substrate according to the sixth embodiment.

FIG. 20 is a longitudinal sectional view for describing each step in a second manufacturing method of the first substrate according to the sixth embodiment.

FIG. 21 is a longitudinal sectional view for explaining each step in a second method for manufacturing the first substrate according to the sixth embodiment.

FIG. 22 is a longitudinal sectional view schematically showing a structure in a display area of a first substrate according to a seventh embodiment.

FIG. 23 is a longitudinal sectional view schematically showing a structure in a display area of a first substrate according to an eighth embodiment.

FIG. 24 is a plan view schematically showing an arrangement of electrodes on a first substrate according to an eighth embodiment.

FIG. 25 is an enlarged plan view schematically showing a structure in the vicinity of a lead portion region and a terminal portion region of a first substrate according to a first modification of the eighth embodiment.

26 is a diagram when a vertical section taken along line II in FIG. 25 is viewed from the direction of the arrow.

FIG. 27 is an enlarged plan view schematically showing a structure in the vicinity of a lead portion region and a terminal portion region of a first substrate according to a second modification of the eighth embodiment.

FIG. 28 is a diagram when a vertical section taken along line II-II in FIG. 27 is viewed from the direction of the arrow.

FIG. 29 is a timing chart showing waveforms of voltages applied to respective electrodes during a sustain period in the method of driving an AC PDP according to the ninth embodiment.

FIG. 30 is a diagram for describing a subfield division mode of one screen and each period in each subfield in the driving method of the AC PDP according to the tenth embodiment.

FIG. 31 is an exploded perspective view schematically showing a structure of an AC type PDP according to the related art.

[Explanation of symbols]

1 transparent electrode, 2 bus electrode, 3, 3A dielectric (layer), 1S, 3SA, 4S, 5S, 9S, 9S2, 1
0S, 15S, 35S, 75S, 175S Surface, 4 cathode film, 5 front glass substrate, 6, Am address electrode, 7, Bm barrier rib, 8 phosphor (layer), 9 rear glass substrate (substrate), 10 overglaze layer , 1
5 interlayer insulating layer, 16, 26, 36, 46, 56, 6
6,76, PAk common address electrode, 17B3, 17T
3,77B3,77T3,163,763 terminals, 16
T, 26T, 36T, 66T first common address electrode,
16B, 26B, 36B, 66B Second common address electrode, 17, 27, 37, 47, 57, 67, 77 Address auxiliary electrode, 17B, 27B, 37B, 47B, 57
B, 67B, 77B 2nd address auxiliary electrode, 17T,
27T, 37T, 47T, 57T, 67T, 77T First address auxiliary electrode, 17B2, 17T2, 77B2
77T2 Common electrode part (wiring part), 17BA, 17TA
Overlapping part, 17BB, 17TB Non-overlapping part, 35, Lm lane, 51F second substrate, 51
Ra, 51Ra2, 51Rb, 51Rc, 51Rd, 5
1Re, 51Rf, 51Rg first substrate, 51S discharge space, 156,256 photosensitive conductor paste (photosensitive material), 101,201 positive resist (photosensitive material),
75, 175 insulating film, 177T, 277T wiring part,
356 conductive material, AD0 address period, AD1 first period (address period), AD2 second period (address period), AR1, AR11, AR12 display area, A
R21, AR22 Leader area, AR3, AR3
1, AR32 terminal area, AR4 area, ARLm lane area, BL block, CB, CT discharge cell, D
1 first direction, D2 second direction, D3 third direction, DC1
Counter discharge (address discharge), DC2 surface discharge (sustain discharge), R, RA, RB erase period, S0 sustain period, S
F1 to SF8, SF8A, SF8B subfield,
Xn sustain electrode, Yn scan electrode, Von (first) voltage, Voff (second) voltage, Vh (third) voltage, V
l (fourth) voltage, Va, VB, VT, VPAk, VX
0, VY0, VY1 to VYN, Vx, Vy voltage.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01J 11/00 H01J 11/00 K F Term (Reference) 5C027 AA01 AA09 5C040 FA01 FA04 GB03 GB14 GC11 GC12 LA18 5C080 AA05 BB05 CC03 DD07 DD08 DD09 DD22 DD23 DD27 EE29 FF12 HH02 HH04 HH07 JJ04 JJ05 JJ06

Claims (22)

[Claims] 1. A substrate, disposed on one surface side of the substrate at least in a display area in parallel with each other.
A plurality of strip-shaped common address electrodes, each of which is classified into a group consisting of first to s-th (s is an integer of 2 or more) common address electrodes, and a group consisting of first to s-th address auxiliary electrodes, respectively. A first substrate including a plurality of band-shaped address auxiliary electrodes; and a band-shaped scan electrode and a sustain electrode each arranged in parallel with each other and arranged in a direction that intersects with the common address electrode and the address auxiliary electrode in a three-dimensional manner. A second substrate comprising: a plurality of electrode pairs; and a dielectric disposed so as to cover the plurality of electrode pairs. The second substrate includes: a space between the first substrate and the second substrate; And arranged along a longitudinal direction of the address auxiliary electrode via barrier ribs for partitioning into a plurality of discharge spaces filled with a discharge gas. A plurality of discharge cells formed at each intersection of the lane region defined as a region between the centers of the barrier ribs in the longitudinal direction and the electrode pairs; In the (1 ≦ j ≦ s) lane area, at least a part of the j-th common address electrode and at least a part of the j-th address auxiliary electrode are both arranged. An AC surface discharge type plasma display panel characterized by being classified. 2. The AC surface discharge type plasma display panel according to claim 1, wherein the first to s-th common address electrodes are commonly connected in the group unit, and are connected to each of the plurality of groups. The AC surface discharge type plasma display panel, wherein the j-th address auxiliary electrodes belonging to the plurality of groups are commonly connected. 3. The AC surface discharge type plasma display panel according to claim 1, wherein the plurality of common address electrodes and the plurality of address auxiliary electrodes are separated via an insulating layer in the display area. An AC surface-discharge type plasma display panel, which is disposed on a flat surface. 4. The plasma display panel according to claim 3, wherein the plurality of common address electrodes and the plurality of address auxiliary electrodes move the first substrate perpendicular to the surface of the substrate. An AC surface discharge type plasma display panel, characterized in that the display area has no overlapping portions when viewed from the direction. 5. The AC surface discharge type plasma display panel according to claim 4, wherein when the first substrate is viewed from a direction perpendicular to the surface of the substrate, the display area is the common address. An AC surface discharge type plasma display panel, which is completely filled with electrodes and the address auxiliary electrodes without gaps. 6. The AC surface discharge type plasma display panel according to claim 1, wherein the common address electrode and the address auxiliary electrode are arranged on the same plane in the display area. Characterized by an AC surface discharge type plasma display panel. 7. The AC surface discharge type plasma display panel according to claim 1, wherein at least a part of the j-th address auxiliary electrode of one of the plurality of j-th address auxiliary electrodes. Wherein at least a part of the j-th address auxiliary electrode of the plurality of j-th address auxiliary electrodes is not arranged in the lane area adjacent to the lane area to which the Discharge type plasma display panel. 8. The AC surface discharge type plasma display panel according to claim 7, wherein the plurality of address auxiliary electrodes are respectively arranged at a predetermined pitch based on a width of the lane area in the arrangement direction. And an AC surface discharge type plasma display panel characterized by being classified into first and second address auxiliary electrodes alternately arranged. 9. The AC surface discharge type plasma display panel according to claim 1, wherein at least a part of the j-th address auxiliary electrode of the plurality of j-th address auxiliary electrodes. At least one of the plurality of j-th address auxiliary electrodes is disposed in at least one of the lane areas on both sides adjacent to the lane area to which the j-th address auxiliary electrode belongs. An AC surface discharge type plasma display panel characterized in that: 10. The AC surface discharge type plasma display panel according to claim 9, wherein the plurality of address auxiliary electrodes are respectively arranged at a predetermined pitch based on a width of the lane area in the arrangement direction. And an AC surface discharge type plasma display panel characterized by being classified into first and second address auxiliary electrodes alternately arranged with each other in units of two electrodes of the same type. 11. The alternating current surface discharge type plasma display panel according to claim 1, wherein one common address electrode is entirely disposed for each lane area. Characterized by an AC surface discharge type plasma display panel. 12. The AC surface discharge type plasma display panel according to claim 1, wherein at least one of the common address electrode and the address auxiliary electrode is connected to two adjacent electrodes. An AC surface discharge type plasma display panel having a pattern shape covering a lane area. 13. The AC surface discharge type plasma display panel according to claim 1, wherein the plurality of address auxiliary electrodes are classified into first and second address auxiliary electrodes, and the first address auxiliary electrode. A wiring portion extending along the longitudinal direction in the display area and extending to one side in the longitudinal direction, and reaching the terminal for the first address auxiliary electrode disposed outside the display area. In addition to the above, the second address auxiliary electrode is formed so as to extend on the other side in the longitudinal direction along the longitudinal direction in the display area, and the second address auxiliary electrode is arranged outside the display area. An AC surface discharge type plasma display panel, further comprising a wiring portion extending to a terminal for an auxiliary electrode. 14. The AC surface discharge type plasma display panel according to claim 1, wherein each of the plurality of common address electrodes and the plurality of address auxiliary electrodes is connected to one end of each of the electrodes. The display device further includes a wiring portion extending to the terminal for each electrode provided outside the display area, wherein each of the wiring portions is electrically separated from each other by an insulating layer disposed outside the display area. An AC surface-discharge type plasma display panel characterized by being arranged in a vertical direction. 15. A plasma display device comprising the AC surface discharge type plasma display panel according to claim 1. Description: 16. The method of driving the AC surface discharge type plasma display panel according to claim 1, wherein the image display time for one screen is divided into a plurality of subfields, and Each of the sub-fields includes at least an address period in which an address discharge based on image data is generated in the predetermined discharge cell in synchronization with the selective scanning of the scan electrode, and a predetermined period in the discharge cell in which the address discharge has occurred. And a sustain period for generating a number of sustain discharges, wherein in the address period, the j-th group of each group is provided.
Either the first voltage or the second voltage based on the image data of the discharge cells belonging to the lane area is shared by the first to s-th common address electrodes belonging to the group in the group unit. When applying a third voltage to the j-th address auxiliary electrode,
A method for driving an AC surface discharge type plasma display panel, comprising applying a fourth voltage having a voltage value different from the third voltage to the address auxiliary electrodes other than the j-th address auxiliary electrode. 17. The method of driving an AC surface discharge type plasma display panel according to claim 16, wherein the common address electrode to which the first voltage is applied and the address auxiliary electrode to which the third voltage is applied. Driving the AC surface discharge type plasma display panel, wherein the first to fourth voltages are set so that the address discharge can be generated only in the discharge cells belonging to the lane region to which both of them belong. Method. 18. The driving method for an AC surface discharge type plasma display panel according to claim 16, wherein the driving method for the j-th lane region is the first driving method.
A method for driving an AC surface discharge type plasma display panel, wherein the method is performed for each of the s-th lane region. 19. The method of driving an AC surface discharge type plasma display panel according to claim 16, wherein at least one of the plurality of subfields forming the image display time for one screen is used. In the address period, the address discharge is generated only in the discharge cells belonging to predetermined t (t is an integer of 1 or more and less than s) lanes of the first to s-th lane regions. A method for driving an AC surface discharge type plasma display panel. 20. The method for driving the AC surface discharge type plasma display panel according to claim 1, wherein the image display time for one screen is divided into a plurality of subfields, and Each of the sub-fields includes at least an address period in which an address discharge based on image data is generated in the predetermined discharge cell in synchronization with the selective scanning of the scan electrode, and a predetermined period in the discharge cell in which the address discharge has occurred. An AC surface-discharge type plasma display panel, wherein the same voltage is applied to both the common address electrode and the address auxiliary electrode during the sustain period. Drive method. 21. A plasma display device driven by applying the method for driving an AC surface discharge type plasma display panel according to claim 16. Description: 22. The method of manufacturing the AC surface discharge type plasma display panel according to claim 5, wherein: (a) one of the common address electrode or the address auxiliary electrode. One of the electrodes and the light-transmitting insulating layer disposed to cover the one electrode are provided on the one surface side, and the light-transmitting substrate is prepared. (B) arranging a photosensitive material on the surface where the insulating layer is exposed; and (c) irradiating light from the other surface side of the substrate using the one electrode as a mask. Exposing the photosensitive material to light, and manufacturing the AC surface discharge type plasma display panel.