WO2008004135A2 - Système de rendu graphique parallèle multimode utilisant un profilage de scène automatique en temps réel et une commande de mode - Google Patents

Système de rendu graphique parallèle multimode utilisant un profilage de scène automatique en temps réel et une commande de mode Download PDF

Info

Publication number
WO2008004135A2
WO2008004135A2 PCT/IB2007/003464 IB2007003464W WO2008004135A2 WO 2008004135 A2 WO2008004135 A2 WO 2008004135A2 IB 2007003464 W IB2007003464 W IB 2007003464W WO 2008004135 A2 WO2008004135 A2 WO 2008004135A2
Authority
WO
WIPO (PCT)
Prior art keywords
graphics
graphics rendering
rendering system
mode parallel
mode
Prior art date
Application number
PCT/IB2007/003464
Other languages
English (en)
Other versions
WO2008004135A3 (fr
WO2008004135A9 (fr
Inventor
Reuven Bakalash
Yaniv Leviathan
Original Assignee
Lucid Information Technology, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lucid Information Technology, Ltd. filed Critical Lucid Information Technology, Ltd.
Priority to CA002637800A priority Critical patent/CA2637800A1/fr
Publication of WO2008004135A2 publication Critical patent/WO2008004135A2/fr
Priority to US12/077,072 priority patent/US20090027383A1/en
Publication of WO2008004135A9 publication Critical patent/WO2008004135A9/fr
Priority to US12/231,304 priority patent/US8284207B2/en
Priority to US12/231,296 priority patent/US20090179894A1/en
Priority to US12/231,295 priority patent/US20090128550A1/en
Publication of WO2008004135A3 publication Critical patent/WO2008004135A3/fr
Priority to US13/646,710 priority patent/US20130120410A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/06—Use of more than one graphics processor to process data before displaying to one or more screens

Definitions

  • the present invention relates generally to the field of computer graphics rendering, and more particularly, ways of and means for improving the performance of parallel graphics rendering processes supported on multiple GPU-based 3D graphics platforms associated with diverse types of computing machinery.
  • Object-Oriented Graphics Systems also known as Graphical Display List (GDL) Graphics Systems
  • 3D scenes are represented as a complex of geometric objects (primitives) in 3D continuous geometric space, and 2D views or images of such 3D scenes are computed using geometrical projection, ray tracing, and light scattering/reflection/absorption modeling techniques, typically based upon laws of physics
  • VOXEL VOlume ELement
  • 3D graphics subsystem based the "Object-Orient Graphics" (or Graphical Display List) system design.
  • objects within a 3D scene are represented by 3D geometrical models, and these geometrical models are typically constructed from continuous-type 3D geometric representations including, for example, 3D straight line segments, planar polygons, polyhedra, cubic polynomial curves, surfaces, volumes, circles, and quadratic objects such as spheres, cones, and cylinders.
  • 3D geometrical representations are used to model various parts of the 3D scene or object, and are expressed in the form of mathematical functions evaluated over particular values of coordinates in continuous Cartesian space.
  • the 3D geometrical representations of the 3D geometric model are stored in the format of a graphical display list (i.e. a structured collection of 2D and 3D geometric primitives).
  • a graphical display list i.e. a structured collection of 2D and 3D geometric primitives.
  • planar polygons mathematically described by a set of vertices, are the most popular form of 3D geometric representation.
  • the 3D scene is graphically displayed (as a 2D view of the 3D geometrical model) along a particular viewing direction, by repeatedly scan-converting the graphical display list.
  • the scan- conversion process can be viewed as a "computational geometry” process which involves the use of (i) a geometry processor (i.e. geometry processing subsystem or engine) as well as a pixel processor (i.e. pixel processing subsystem or engine) which together transform (i.e. project, shade and color) the display-list objects and bit-mapped textures, respectively, into an unstructured matrix of pixels.
  • the composed set of pixel data is stored within a 2D frame buffer (i.e. Z buffer) before being transmitted to and displayed on the surface of a display screen.
  • a video processor/engine refreshes the display screen using the pixel data stored in the 2D frame buffer.
  • a typical PC based graphic architecture has an external graphics card (105).
  • the main components of the graphics card (105) are the graphics processing unit (GPU) and video memory, as shown.
  • the graphic card is connected to the display (106) on one side, and the CPU (101 ) through bus (e.g. PCIExpress) (107) and Memory Bridge (103, termed also "chipset", e.g. 975 by Intel), on the other side.
  • bus e.g. PCIExpress
  • Memory Bridge e.g. 975 by Intel
  • Fig. IB illustrates a rendering of three successive frames by a single GPU.
  • the application assisted by graphics library, creates a stream of graphics commands and data describing a 3D scene.
  • the stream is pipelined through the GPU's geometry and pixel subsystems to create a bitmap of pixels in the Frame Buffer, and finally displayed on a display screen.
  • a sequence of successive frames generates a visual illusion of a dynamic picture.
  • the structure of a GPU subsystem on a graphic card comprises: a video memory which is external to GPU, and two 3D engines: (i) a transform bound geometry subsystem (224) for processing 3D graphics primitives; (ii) and a fill bound pixel subsystem (225).
  • the video memory shares its storage resources among geometry buffer (222) through which all geometric (i.e. polygonal) data is transferred, commands buffer, texture buffers (223), and Frame Buffer (226).
  • the first potential bottleneck (221 ) stems from transferring data from CPU to GPU.
  • Two other bottlenecks are video memory related: geometry data memory limits (222), and texture data memory limits (223).
  • transform bound (224) in the geometry subsystem and fragment rendering (225) in pixel subsystem. These bottlenecks determine overall throughput. In general, the bottlenecks vary over the course of a graphics application.
  • FIG. 2A there is shown an advanced chipset (e.g. Bearlake by Intel) having two buses (107, 108) instead of one, and allowing the interconnection of two external graphics cards in parallel: primary card (105) and secondary card (104), to share the computation load associated with the 3D graphics rendering process.
  • the display (106) is attached to the primary card (105). It is anticipated that even more advanced commercial chipsets with >2 busses will appear in the future, allowing the interconnection of more than two graphic cards.
  • the general software architecture of prior art graphic system (200) comprises: the graphics application (201), standard graphics library (202), and vendor's GPU driver (203).
  • This graphic software environment resides in the "program space" of main memory (102) on the host computer system.
  • the graphic application (201) runs in the program space, building up the 3D scene, typically as a data base of polygons, each polygon being represented as a set of vertices. The vertices and others components of these polygons are transferred to the graphic card(s) for rendering, and displayed as a 2D image, on the display screen.
  • a GPU subsystem on the graphics card is shown as comprising: a video memory disposed external to the GPU, and two 3D engines: (i) a transform bound geometry subsystem (224) for processing 3D graphics primitives; and (ii) a fill bound pixel subsystem (225).
  • the video memory shares its storage resources among geometry buffer (222), through which all geometric (i.e. polygonal) data is transferred to the commands buffer, texture buffers (223), and Frame Buffer FB (226).
  • the division of graphics data among GPUs reduces (i) the bottleneck (222) posed by the video memory footprint at each GPU, (ii) the transform bound processing bottleneck (224), and (iii) the fill bound processing bottleneck (225).
  • a third type of method of parallel graphics rendering referred to as the Object Division Method
  • the Object Division Method illustrated in Fig. 3A, can be found applied on conventional graphics platforms of the kind shown in Fig. 3, as well as specialized graphics computing platforms as described in US Patent Application Publication No. US 2002/0015055, assigned to Silcon Graphics, Inc. (SGI), published on February 7, 2002, and incorporated herein by reference.
  • the parallel graphics platform uses the multiple sets of pixel data generated by each graphics pipeline to synthesize (or compose) a final set of pixels that are representative of the 3D scene (taken along the specified viewing direction), and this final set of pixel data is then stored in a frame buffer;
  • the Image Division (Sort-First) Method of Parallel Graphics Rendering distributes all graphics display list data and commands to each of the graphics pipelines, and decomposes the final view (i.e. projected 2D image) in Screen Space, so that, each graphical contributor (e.g. graphics pipeline and GPU) renders a 2D tile of the final view.
  • This mode has a limited scalability due to the parallel overhead caused by objects rendered on multiple tiles.
  • the Split Frame Rendering mode divides up the screen among GPUs by continuous segments, e.g. two GPUs each one handles about one half of the screen. The exact division may change dynamically due to changing load accross the screen image. This method is used inVidia's SLITM multiple-GPU graphics product.
  • Tiled Frame Rendering mode divides up the image into small tiles. Each GPU is assigned tiles that are spread out across the screen, contributing to good load balancing. This method is implemented by ATI's CrossfireTM multiple GPU graphics card solution.
  • the entire database is broadcast to each GPU for geometric processing.
  • the processing load at each Pixel Subsystem is reduced to about 1/N. This way of parallelism relieves the fill bound bottleneck (225).
  • the image division method ideally suits graphics applications requiring intensive pixel processing.
  • the Time Division (DPlex) Method of Parallel Graphics Rendering distributes all display list graphics data and commands associated with a first scene to the first graphics pipeline, and all graphics display list data and commands associated with a second/subsequent scene to the second graphics pipeline, so that each graphics pipeline (and its individual rendering node or GPU) handles the processing of a full, alternating image frame.
  • each graphics pipeline and its individual rendering node or GPU
  • each GPU is give extra time of N time frames (for " N parallel GPUs) to process a frame.
  • the released bottlenecks are those of transform bound (224) at geometry subsystem, and fill bound (225) at pixel subsystem.
  • each GPU must access all of the data. This requires either maintaining multiple copies of large data sets or creating possible access conflicts to the source copy at the host swelling up the video memory bottlenecks (222, 223) and data transfer bottleneck (221).
  • the Object Division (Sort-last) Method of Parallel Graphics Rendering decomposes the 3D scene (i.e. rendered database) and distributes graphics display list data and commands associated with a portion of the scene to the particular graphics pipeline (i.e. rendering unit), and recombines the partially rendered pixel frames, during recomposition.
  • the geometric database is therefore shared among GPUs, offloading the geometry buffer and geometry subsystem, and even to some extend the pixel subsystem. The main concern is how to divide the data in order to keep load balance.
  • An exemplary multiple-GPU platform for supporting the object-division method of Fig. 3B is shown in Fig. 3A.
  • the platform requires complex and costly pixel compositing hardware which prevents its current application in a modern PC-based computer architecture.
  • a given pipeline along a parallel graphics system is only as strong as the weakest link of it stages, and thus a single bottleneck determines the overall throughput along the graphics pipelines, resulting in unstable frame-rate, poor scalability, and poor performance.
  • a primary object of the present invention is to provide a new and improved method of and apparatus for practicing parallel 3D graphics rendering processes in modern multiple- GPU based computer graphics systems, while avoiding the shortcomings and drawbacks associated with prior art apparatus and methodologies.
  • Another object of the present invention is to provide such apparatus in the form of a multi- mode multiple graphics processing unit (GPU) based parallel graphics system having multiple graphics processing pipelines with multiple GPUs supporting a parallel graphics rendering process having time, frame and object division modes of operation, wherein each GPU comprises video memory, a geometry processing subsystem and a pixel processing subsystem, and wherein 3D scene profiling is performed in real-time, and the parallelization state/mode of the system is dynamically controlled to meet graphics application requirements.
  • GPU graphics processing unit
  • Another object of the present invention is to provide a multi-mode parallel graphics rendering system having multiple graphics pipelines, each having a GPU and video memory, and supporting multiple modes of parallel graphics rendering using real-time graphics application profiling and configuration of the multiple graphics pipelines supporting multiple modes of parallel graphics rendering, namely, a time-division mode, a frame-division mode, and an object-division mode of parallel operation.
  • Another object of the present invention is to provide such a multi-mode parallel graphics rendering system, which is capable of dynamically handling bottlenecks that are automatically detected during any particular graphics application running on the host computing system.
  • Another object of the present invention is to provide such a multi-mode parallel graphics rendering system, wherein different parallelization schemes are employed to reduce pipeline bottlenecks, and increase graphics performance.
  • Another object of the present invention is to provide such a multi-mode parallel graphics rendering system, wherein image, time and object division methods of parallelization are implemented on the same parallel graphics platform.
  • Another object of the present invention is to provide a novel method of multi-mode parallel graphics rendering that can be practiced on a multiple GPU-based PC-level graphics system, and dynamically alternating among time, frame and object division modes of parallel operation, in realtime, during the course of graphics application, and adapting the optimal method to the real time needs of the graphics application.
  • Another object of the present invention is to provide such a multi-mode parallel graphics rendering system, which is capable of supervising the performance level of a graphic application by dynamically adapting different parallelization schemes to solve instantaneous bottlenecks along the graphic pipelines thereof.
  • Another object of the present invention is to provide such a multi-mode parallel graphics rendering system, having run time configuration flexibility for various parallel schemes to achieve the best parallel performance.
  • Another object of the present invention is to provide such a multi-mode parallel graphics rendering system having architectural flexibility and real-time profiling and control capabilities which enable utilization of different modes for high and steady performance along the application running on the associated host system.
  • Another object of the present invention is to provide a novel method of multi-mode parallel graphics rendering on a multiple GPU-based graphics system, which achieves improved system performance by using adaptive parallelization of multiple graphics processing units (GPUs), on conventional and non-conventional platform architectures, as well as on monolithic platforms, such as multiple GPU chips or integrated graphic devices (IGD).
  • GPUs graphics processing units
  • IGD integrated graphic devices
  • Another object of the present invention is to provide a multi-mode parallel graphics rendering system, wherein bottlenecks are dynamically handled.
  • Another object of the present invention is to provide such a multi-mode parallel graphics rendering system, wherein stable performance is maintained throughout course of a graphics application.
  • Another object of the present invention to provide a multi-mode parallel graphics rendering system supporting software-based adaptive graphics parallelism for the best performance, seamlessly to the graphics application, and compliant with graphic standards (e.g. OpenGL and Direct3D).
  • graphic standards e.g. OpenGL and Direct3D
  • Another object of the present invention is to provide a multi-mode parallel graphics rendering system, wherein all parallel modes are implemented in a single architecture.
  • Another object of the present invention is to provide a multi-mode parallel graphics rendering system, wherein the architecture is flexible, supporting fast inter-mode transitions.
  • Another object of the present invention is to provide a multi-mode parallel graphics rendering system which is adaptive to changing to meet the needs of any graphics application during the course of its operation.
  • Another object of the present invention is to provide a multi-mode parallel graphics rendering system, which can be implemented using a software implementation of present invention.
  • Another object of the present invention is to provide a multi-mode parallel graphics rendering system, which can be realized using a hardware implementation.
  • Another object of the present invention is to provide a multi-mode parallel graphics rendering system, which can be implemented using IGD technology.
  • Another object of the present invention is to provide a multi-mode parallel graphics rendering system, characterized by run-time configuration flexibility for various parallel schemes to achieve the best parallel performance.
  • Another object of the present invention is to provide a multi-mode parallel graphics rendering system which operates seamlessly to the application and is compliant with graphic standards (e.g. OpenGL and Direct3D).
  • graphic standards e.g. OpenGL and Direct3D
  • Another object of the present invention is to provide a multi-mode parallel graphics rendering system, which can be implemented on conventional multi-GPU platforms replacing image division or time division parallelism (e.g. SLI by Nvidia).
  • Another object of the present invention is to provide a multi-mode parallel graphics rendering system, which enables the multiple GPU platform vendors to incorporate the solution in their systems supporting only image division and time division modes of operation.
  • Another object of the present invention is to provide such multiple GPU-based graphics system, which enables implementation using low cost multi-GPU cards.
  • Another object of the present invention is to provide a multi-mode parallel graphics rendering system implemented using IGD technology, and wherein it impossible for the IGD to get disconnected by the BIOS when an external graphics card is connected and operating.
  • Another object of the present invention is to provide a multiple GPU-based graphics system, wherein a new method of dynamically controlled parallelism improves the system's efficiency and performance.
  • Another object of the present invention is to provide a multi-mode parallel graphics rendering system, which can be implemented using an IGD supporting more than one external GPU.
  • Another object of the present invention is to provide a multi-mode parallel graphics rendering system, which can be implemented using an lGD-based chipset having two or more IGDs.
  • Fig. IA is a graphical representation of a typical prior art PC-based computing system employing a conventional graphics architecture driving a single external graphic card (105);
  • Fig. IB a graphical representation of a conventional GPU subsystem supported on the graphics card of the PC-based graphics system of Fig. IA;
  • Fig. 1C is a graphical representation of a conventional method rendering successive 3D scenes using single GPU graphics platform
  • Fig. 2A is a graphical representation of a typical prior art PC-based computing system employing a conventional dual-GPU graphic architecture comprising two external graphic cards (i.e. primary (105) and secondary (107) graphics cards) connected to the host computer, and a display device (106) attached to the primary graphics card;
  • two external graphic cards i.e. primary (105) and secondary (107) graphics cards
  • Fig. 2B is a graphical representation illustrating the general software architecture of the prior art PC-based graphics system shown in Fig. 2A;
  • Fig. 2C a graphical representation of a conventional GPU subsystem supported on each of the graphics cards employed in the prior art PC-based computing system of Fig. 2A;
  • Fig. 2D is a graphical representation of a conventional parallel graphics rendering process being carried out according to the Time Division Method of parallelism using the dual GPUs provided on the prior art graphics platform illustrated in Figs. 2A through 2C;
  • Fig. 2E. is a graphical representation of a conventional parallel graphics rendering process being carried out according to the Image Division Method of parallelism using the dual GPUs provided on the prior art graphics platform illustrated in Figs. 2A through 2C;
  • Fig. 3 A is a schematic representation of a prior art parallel graphics platform comprising multiple parallel graphics pipelines, each supporting video memory and a GPU, and feeding complex pixel compositing hardware for composing a final pixel-based image for display on the display device;
  • Fig. 3B is a graphical representation of a conventional parallel graphics rendering process being carried out according to the Object Division Method of parallelism using multiple GPUs on the prior art graphics platform of Fig. 3A;
  • Fig. 4A is a schematic representation of the multi-mode parallel 3D graphics rendering system of present invention employing automatic 3D scene profiling and multiple GPU and state control, wherein the system supports three primary parallelization stages, namely, Decompose (401), Distribute (402) and Recompose (403), and wherein each stage is configured (i.e. set up) into a sub- state by set of parameters A for 401, B for 402, and C for 403, and wherein the "Parallelism State" for the overall parallel graphics system is established or determined by the combination of sub-states of these component stages;
  • Decompose 401
  • Distribute 402
  • Recompose Recompose
  • Fig. 4Al is a schematic representation for the Mode Definition Table which shows the four combinations of sub-modes A:B:C for realizing the three Parallel Modes of the parallel graphics system of the present invention, and its one Single (GPU) (Non-Parallel Functioning) Mode of the system of present invention, if needed;
  • Fig. 4B is a State Transition Diagram for the multi-mode parallel 3D graphics rendering system of present invention, illustrating that a parallel state is characterized by A, B 3 C sub-state parameters, that the non-parallel state (single GPU) is an exceptional state, reachable from any state by a graphics application or PCM requirement, and that all state transitions in the system are controlled by Profiling and Control Mechanism (PCM), wherein in those cases of known and previously analyzed graphics applications, the PCM, when triggered by events (e.g. drop of FPS), automatically consults the Behavioral Database in course of application, or otherwise, makes decisions which are supported by continuous profiling and analysis of listed parameters, and/or trial and error event driven or periodical cycles;
  • PCM Profiling and Control Mechanism
  • Fig. 5A is a schematic representation of process carried out by the Profiling and Control Cycle in the Profiling and Control Mechanism employed in the multi-mode parallel 3D graphics rendering system of present invention, shown in Fig. 4A;
  • Fig. 5B is a schematic representation of process carried out by the Periodical Trial & Error Based Control Cycle in the Profiling and Control Mechanism employed in the multi-mode parallel 3D graphics rendering system of present invention, shown in Fig. 4A;
  • Fig. 5C is a schematic representation of process carried out by the Event Driven Trial & Error Control Cycle in the Profiling and Control Mechanism employed in the multi-mode parallel 3D graphics rendering system of present invention, shown in Fig. 4 A;
  • Fig. 5D is a schematic representation showing the various inputs into, and tasks of the Application Profiling and Analysis Module within the Profiling and Control Mechanism employed in the multi-mode parallel 3D graphics rendering system of present invention, shown in Fig. 4A;
  • Fig. 6A is a schematic block representation of a general software-based architecture of the multi-mode parallel 3D graphics rendering system of present invention depicted in Fig. 4A, and illustrating the Profiling and Control Mechanism (400) supervising the flexible parallel rendering structure which enables the real-time adaptive, multi-mode parallel 3D graphics rendering system of present invention;
  • Fig. 6B is a schematic block representation of a general hardware-based architecture of the multi-mode parallel 3D graphics rendering system of present invention depicted in Fig, 4A, and illustrating the Profiling and Control Mechanism (400) that supervising the flexible Hub-based parallel rendering structure which enables the real-time adaptive, multi-mode parallel 3D graphics rendering system of present invention;
  • Fig. 7A is a schematic block representation of an illustrative software-based architecture of the multi-mode parallel 3D graphics rendering system of present invention (700), employing two GPUs and software package (701 ) comprising the Profiling and Control Mechanism (400) and a suit of three parallelism driving the software-based Decomposing Module (401 '), Distributing Module (402') and Recomposing Module (403').
  • Fig. 7B is a schematic block representation of an illustrative hardware-based architecture of the multi-mode parallel 3D graphics rendering system of present invention (710), employing two GPUs, Graphic Hub (comprising Distributor Module 402" and Recomposer Module 403") and software components comprising the Profiling and Control Mechanism (400) and Decomposing Module (401);
  • Fig. 8A is a schematic block representation of a hardware-based embodiment of the multi-mode parallel graphics rendering system of the present invention present invention, using multiple discrete graphic cards and hardware-based distributor and recomposer components (402" and 403") implemented on a hardware-based hub of the present invention;
  • Fig. 8B is a schematic block representation of a first illustrative hardware-based embodiment of the multi-mode parallel graphics rendering system of the present invention present invention, using a discrete dual graphics cards and hardware-based distributor and recomposer components (402" and 403") implemented on a hardware-based hub of the present invention;
  • Fig. 8C is a schematic block representation of a second illustrative hardware-based embodiment of the multi-mode parallel graphics rendering system of the present invention, using discrete multiple graphics cards and hardware-based distributor and recomposer components (402" and 403") implemented on a hardware-based hub of the present invention;
  • Fig. 8D is a schematic block representation of a third illustrative hardware-based embodiment of the multi-mode parallel graphics rendering system of the present invention, using discrete multiple graphics cards and hardware-based distributor and recomposer components (402" and 403") implemented on a hardware-based hub of the present invention;
  • Fig. 8E is a schematic block representation of a software-based implementation of the multi- mode parallel graphics rendering system of the present invention, using multiple discrete GPUs, and software-based decomposer, distributer and recomposer components (701) implemented within host memory space of the host computing system;
  • Fig. 8F is a schematic block representation of a first illustrative embodiment of a software- based implementation of the multi-mode parallel graphics rendering system of the present invention, employing discrete dual GPU graphics cards and software-based decomposer, distributer and recomposer components (701) implemented within host memory space of the host computing system;
  • Fig. 8G is a schematic block representation of a second illustrative embodiment of a software- based implementation of the multi-mode parallel graphics rendering system of the present invention, employing discrete dual GPU graphics cards and software-based decomposer, distributer and recomposer components (701) implemented within host memory space of the host computing system;
  • Fig. 8H is a schematic block representation of a third illustrative embodiment of a software- based implementation of the multi-mode parallel graphics rendering system of the present invention, employing discrete dual GPU graphics cards and software-based decomposer, distributer and recomposer components (701) implemented within host memory space of the host computing system;
  • Fig. 9A is a schematic block representation of a generalized hardware implementation of the multi-mode parallel graphics rendering system of the present invention, wherein multiple GPUs (715) and hardware-based distributor and recomposer (hub) components (402" and 403") the present invention are implemented on a single graphics display card (902), and to which the display device is attached;
  • Fig. 9B is a schematic block representation of an illustrative embodiment of the multi-mode parallel graphics rendering system of the present invention, wherein multiple GPUs (715) and hardware-based distributor and recomposer (hub) components (402" and 403") the present invention are implemented on a single graphics display card (902), and to which the display device is attached;
  • Fig. 1 OA is a schematic block representation of a generalized hardware implementation of the multi-mode parallel graphics rendering system of the present invention using system on chip (SOC) technology, wherein multiple GPUs and the hardware-based distributor and recomposer are implemented on a single SOC-based graphics chip (1001) on a single graphics card (1002), while the software-based decomposer component is implemented in host memory space of the host computing system;
  • SOC system on chip
  • Fig. 1 OB is a schematic block representation of an illustrative embodiment of a SOC implementation of the multi-mode parallel graphics rendering system of the present invention, wherein multiple GPUs and hardware distributor and recomposer components are realized on a single SOC implementation of the present invention (1001) on a single graphics card (1002), while the software-based decomposer component is implemented in host memory space of the host computing system;
  • Fig. 1OC is a schematic block representation of an illustrative embodiment of the multi-mode parallel graphics rendering system of the present invention, employing a multiple GPU chip installed on a single graphics card, and the software-based decomposer, distributor, and recomposer components of the present invention implemented in host memory space, and to which a single graphics card is attached, and to which the display device is attached;
  • Fig. 1 I A is a schematic block representation of an illustrative embodiment of the multi-mode parallel graphics rendering system of the present invention, implemented using (i) an integrated graphics device (IGD, 1 101) within the memory bridge (1 101) of the host computing system, implementing the hardware-based distributor and recomposer components of present invention, (ii) the software-based decomposer and distributor components of the present invention implemented within the host memory space, and (iii) multiple graphics display cards (717) connected to the IDG, and to which the display device is attached; and
  • Fig. 1 I B is a schematic block representation of an illustrative embodiment of the multi-mode parallel graphics rendering system of the present invention, implemented using an integrated graphics device (IGD, 1 1 12) within the memory bridge (11 1 1) of the host computing system, and the software- based decomposer, distributor and recomposer components of the present invention implemented within the host memory space, and (iii) multiple graphics display cards (717) connected to the IDG, and to which the display device is attached.
  • IGD integrated graphics device
  • one aspect of the present invention teaches how to dynamically retain high and steady performance of a three-dimensional (3D) graphics system on conventional platforms (e.g. PCs, laptops, servers, etc.), as well as on silicon level graphics systems (e.g. graphics system on chip (SOC), and integrated graphics device IGD implementations).
  • 3D three-dimensional
  • SOC graphics system on chip
  • IGD implementations integrated graphics device IGD implementations
  • the multiple-mode multiple GPU-based parallel graphics rendering system fulfills the great need of the marketplace by providing a highly-suited parallelism scheme, wherein different GPU- parallel rendering schemes dynamically, alternate throughout the course of any particular graphics application, and adapting the optimal parallel rendering method (e.g. Image, Time or Frame Division Method) in real-time to meet the changing needs of the graphics application.
  • a highly-suited parallelism scheme wherein different GPU- parallel rendering schemes dynamically, alternate throughout the course of any particular graphics application, and adapting the optimal parallel rendering method (e.g. Image, Time or Frame Division Method) in real-time to meet the changing needs of the graphics application.
  • Multi-mode Parallel Graphics Rendering System Employing Automatic Profiling And Control
  • the multi-mode parallel graphics rendering system of present invention employing automatic 3D scene profiling and multiple GPU control comprising: Multi-mode Parallel Rendering Subsystem including three parallelization stages realized by a Decompose Module (401 ), Distribute Module (402) and Recompose Module (403), and an array of Graphic Processing Units (GPUs); and (ii) Profiling and Control Mechanism (PCM) 400.
  • Each stage is induced (i.e. set up) into a sub-state by set of parameters; A for 401 , B for 402, and C for 403.
  • the state of parallelism of the overall graphic system is established by the combination of sub-states A, B and C, as listed in the Mode/State Definition Table of Fig. 4Al and as it will be elaborated hereinafter.
  • the unique flexibility of the multi-mode parallel graphics system stems from its ability to quickly change its sub-states, resulting in transition of the overall graphic system to another parallel state: Object Division State, Image Division State or Time Division, as well as to other potential parallelization schemes.
  • the array of GPUs (407) comprises N pairs of GPU and Video Memory pipelines, while only one of them, termed "primary,” is responsible for driving the display unit (e.g. LCD panel and the like).
  • Each one of the staging blocks i.e. Decompose Module (401), Distribute Module (402) and Recompose Module (403), carries out all functions required by the different parallelization schemes supported on the multi-mode parallel graphics rendering platform of the present invention.
  • the Decompose Module (401) splits up the stream of graphic data and commands according to the required parallelization mode.
  • the typical graphics pipeline is fed by stream of commands and data from the application and graphics library (OpenGL or Direct 3D).
  • This stream which is sequential in nature, has to be properly handled and eventually partitioned, according to parallelization method.
  • the Decompose Module can be set to different decomposing sub-states (Al through A4), according to Fig. 4Al : Object decomposition, Image decomposition, Alternate decomposition, and Single, for Object Division, Image Division, Time Division and Single GPU (non parallel), respectively.
  • Fig. 4Al Object decomposition, Image decomposition, Alternate decomposition, and Single, for Object Division, Image Division, Time Division and Single GPU (non parallel), respectively.
  • the Distribute Module (402) physically distributes the streams of data and commands to the cluster of GPUs.
  • This Module is set to one of its Bl through B3 sub-states of Divide and Broadcast, for Object Division and Image Division States, respectively, and Single GPU substate, for the Time Division and Single GPU (i.e. non parallel system state).
  • the Re-compose Module (403) merges together the partial results of multiple graphics pipelines, according to parallelization mode.
  • the resulting final Frame Buffer (FB) is sent into the display device.
  • This Module has three (Cl through C3) sub-states.
  • the Test based sub-state carries out re-composition based on predefined test performed on pixels of partial frame buffers; typically these are depth test, stencil test, or combination thereof.
  • the Screen based sub-state combines together parts of the final frame buffers, in a puzzle like fashion, creating a single image.
  • the None mode makes no merges, just moves one of the pipeline frame buffers to the display, as required in time division parallelism or in single GPU (non parallel).
  • each GPU renders the next successive frame.
  • the Single GPU State of Operation is a non parallel state of operation, it is allowed and supported in the system of the present invention as it is beneficial in some exceptional cases.
  • the Profiling and Control Mechanism comprises tri-parte structure comprising: Decompose Module (401); Distribute Module (402); and Recompose Module (403).
  • the PCM comprises three algorithmic modules, namely:
  • each such Module (401), (402) and (403) has a sub-state, and each allowed state of the multi-mode parallel graphics rendering system (i.e. Image-Division State, Time-Division State, Object-Division State, and Single GPU State) is the determined by the combination of these sub-states, at any instant in time.
  • each allowed state of the multi-mode parallel graphics rendering system i.e. Image-Division State, Time-Division State, Object-Division State, and Single GPU State
  • the PCM (400) controls the state of the overall multi-mode parallel graphics rendering system, as well as the substates of the modules (401), (402) and 403, and interstate transitions thereof.
  • the PCM (400) performs such system functions using two data stores, namely: the Historical Repository (404); and the Behavioral Profile DB (405).
  • a graphics application when a graphics application starts, the PCM tries identifying whether this application is previously known to the system.
  • AU analyzed and known application profiles are stored in the Behavioral Profile DB (405).
  • the optimal starting state is recommended by the DB, and also further on the behavioral database assists the PCM in course of application.
  • Fig. 5C a trial and error cycle of trying out all three parallelization schemes is exercised to choose the optimal one.
  • Trial & error is based on comparing results of a single (or very few) cycle spent by the system at each parallelization state. As shown in Fig. 5D, Trial & error can be driven by an event, e.g. drop of frame rate, or as indicated in Fig. 5C, performed periodically.
  • an event e.g. drop of frame rate, or as indicated in Fig. 5C, performed periodically.
  • each parallel state is characterized by A, B, C sub-state parameters.
  • the non-parallel state i.e. "singl”e GPU state
  • the PCM considers the following parameters for determining when a state transition should occur:
  • Steps A-C test whether the graphics application is listed in the Behavioral DB. If the application is listed in the Behavioral DB, then application's profile is taken from the DB (step E), a preferred state is set (at Step G), N successive frames are rendered (steps I-J), performance data collected (step K), by the way addition to Historical Repository (step M) and analyzed for next optimal state (step F). Upon conclusion of application, the Behavioral DB is updated at Step N by the collected data from Historical Repository.
  • the "Periodical Trial & Error" Process differs from the above process/method in its empirical approach.
  • the best parallelization scheme for the graphical application at hand is chosen by a series of trials (Steps A-M). After N frames (performed during Steps N-O) another periodical trial is done.
  • a preventive condition for any of parallelization schemes can be set and tested (during Steps B, E, and H), such as use by the application of the Frame Buffer FB for the next successive frame, which prevents entering the Time Division State.
  • Fig. 5C shows flowchart of a slightly different empirical approach, in which the tests towards change of state are done only in case of drop-in-frame-rate event (as indicated during Steps O, B-M)
  • the Profiling and Control Mechanism comprises three algorithmic components, namely: a Application Profiling and Analysis Module (407); Parallel Policy Management Module (408) and Distributed Graphics Function Control.
  • PCM Profiling and Control Mechanism
  • the Application Profiling and Analysis (407) module monitors and analyzes profiling data of running application.
  • the inputs into and the tasks of the Application Profiling and Analysis Module are shown in Fig. 5D.
  • the Application Profiling and Analysis Module performs its analysis based on the following:
  • Historical repository which continuously stores up the acquired data (i.e. this data having historical depth, and beingused for constructing behavioral profile of ongoing application);
  • Knowledge based Behavioral Profile DB (405) which is an application profile library of priorly known graphics applications (and further enriched by newly created profiles based on data from the Historical Depository).
  • the choice of parallelism is based on profiling and analysis of the system's performance at Performance Data Inputs from several sources within the graphics system: GPUs, vendor's driver, chipset, and graphic Hub (optional).
  • the performance data includes the following components, needed for estimating the performance and locate casual bottlenecks:
  • the Performance Data is fed and processed for real time analysis and following tasks of the Application Profiling and Analysis module:
  • Object-Division Method supersedes the other division modes in that it reduces more bottlenecks.
  • the Object-Division Mode relaxes bottleneck across the pipeline: (i) the geometry (i.e. polygons, lines, dots, etc) transform processing is offloaded at each GPU, handling only 1/N of polygons (N - number of participating GPUs) ; (ii) fill bound processing is reduced since- less polygons are feeding the rasterizer, (iii) less geometry memory is needed; (iv) less texture memory is needed.
  • the Time-Division Mode is favorable for the bottlenecks of transform and fill by allowing more time, however the video memory bottleneck remains unsolved. Moreover, this method suffers from severe problems such as (i) CPU bottlenecks, (ii) the GPU generated frame buffers are not available to each other in cases the previous frame is required as a start point for the successive one, and (iii) from pipeline latency. In many applications these are stoppages from using time division; however, for some other applications this method may be suitable and perform better than other parallel ization schemes.
  • Image- division render time is given by:
  • the render time is:
  • An algorithm to choose between Image-Division and Object- Di vision Modes detects which of transform and fill bound processing is smaller. Once the layer-depth reaches some threshold value throughput the scene; Object-Division Mode will not minimize the Fill function any more.
  • Render(n,p) the time taken to draw one pixel.
  • the drawings time is assumed to be constant for all pixels (which may be a good approximation, but is not perfectly accurate).
  • the screen space of general scene is divided into sub-spaces based on the layer-depth of each pixel. This leads to some meaningful figures. For example, suppose a game engine has most of the screen (90%) with a depth of four layers (the scenery) and a small part covered by the player (10%) with a depth of 20 layers.
  • the value of Render without Object Division Mode support is given by:
  • the improvement factor in this case is thus 1.3602643398952217.
  • a CAD engine on the other hand, might have a constant layer depth of 4.
  • the Object Division Mode is not improving the rendering time by a large amountm and if rendering time is the bottleneck of the total frame calculation procedure, then the Image-Division Mode might be a better approach.
  • Parallel Policy Management module makes up final decision regarding the preferred parallel mode, based on profiling and analysis results of the previous module. The decision is made per some N frames basis. As shown above, the layer depth factor, differentiating between the effectiveness of object division vs. image division can be evaluated by analyzing the relationship of geometric data vs. fragment data at a scene, or alternatively can be found heuristically. illustrative control policies have ben described above and in Figures 5A-5C. Distributed Graphic Function Control
  • Distributed Graphic Function Control Module (409) carries out all the functions associated with the different parallelization modes according to decision made by the Parallel Policy Management Module.
  • the Distributed Graphic Function Control Module (409) drives directly the configuration sub-states of the Decompose, Distribute and Recompose Modules, according to the parallelization mode. Moreover, it includes drivers needed for hardware components such as graphic Hub, described herein later in the specifications.
  • the multi-mode parallel graphics rendering system of present invention employing automatic scene profiling and mode control has two principally different embodiments, expressed in software and hardware, although both are embraced by the scope and spirit of the present invention illustrated in Fig. 4A.
  • a generalized software embodiment is the new General Software Architecture of present invention, block, showing the Profiling and Control Mechanism (400) that supervises the flexible parallel structure of multi-GPU rendering system.
  • the Profiling and Control Mechanism has been already thoroughly described in reference to Fig. 4A.
  • the multiple-GPU rendering system comprises of Decompose Module (401'), Distribute Module (402'), Recompose Module (403'), and Cluster of Multiple GPUs (410').
  • the Decompose Module is implemented by three software modules, OS-GPU interface and Utilities, Division Control and State Monitoring.
  • OS-GPU Interface and Utilities performs all the functions associated with interaction with the Operation System, graphic library (e.g. OpenGL or DirectX), and interfacing with GPUs. It is responsible for interception of the graphic commands from the standard graphic library, forwarding and creating graphic commands to Vendor's GPU Driver, controlling registry and installation, OS services and utilities. Another task of this module is reading performance data from different sources (GPUs, vendor's driver, chipset) and forwarding the data to Profiling and Control Mechanism.
  • graphic library e.g. OpenGL or DirectX
  • GPUs e.g. OpenGL or DirectX
  • It is responsible for interception of the graphic commands from the standard graphic library, forwarding and creating graphic commands to Vendor's GPU Driver, controlling registry and installation, OS services and utilities.
  • Another task of this module is reading performance data from different sources (GPUs, vendor's driver, chipset) and forwarding the data to Profiling and Control Mechanism.
  • Division Control controls the division parameters and data to be processed by each GPU, according to parallelization scheme, e.g. division of data among GPUs in object division mode, or image partition among GPUs in image division mode.
  • the polygon division control consists of sending each polygon randomly to a different GPU. This is an easy algorithm to implement, while turns out to be quite efficient. There are different variants on this basic algorithm.
  • every even polygon can be sent to GPUl and every odd polygon to GPU2 (or more GPUs accordingly).
  • vertex-arrays are kept in their entirety and sent to different GPUs, as the input might be of the form of vertex arrays, and dividing it may be too expensive.
  • GPU loads are detected at real time and the next polygon is sent to the least loaded GPU. Dynamic load balancing by complex objects (built out of polygons). GPU loads are detected at real time and the next object is sent to the least loaded GPU.
  • the graphic libraries e.g. OpenGL and DirectX
  • the graphic libraries are state machines. Parallelization must preserve cohesive state across the graphic system. It is done by continuous analysis of all incoming commands, while the state commands and some of the data must be duplicated to all pipelines in order to preserve the valid state across the graphic pipeline. This function is exercised mainly in object division scheme, as disclosed in detail in inventor's previous pending patent PCT/IL04/001069.
  • the Distribute Module is implemented by the Distribution Management module, which addresses the streams of commands and data to the different GPUs via chipset outputs, according to needs of the parallelization schemes.
  • the Re-compose Module is realized by two modules: (i) Merge Management handling the read-back of frame buffers and the compositing sub-states of: test based, screen based and none, (ii) Merger is an algorithmic module that performs the different compositing algorithms:
  • the Test Based sub-state suits compositing of object division sets of Z-buffcr, stencil-buffer and color-buffer are read back from GPU FBs to host's memory for compositing.
  • the pixels of color-buffers from different GPUs are merged into single color-buffer, based on per pixel comparison of depth and/or stencil values (e.g. at given x-y position only the pixel associated with the lowest z value is let out to the output color-buffer).
  • This is a software technique to perform hidden surface elimination among multiple frame buffers required for object division mode.
  • Frame buffers are merged based on depth and stencil tests. Stencil tests, with or without combination with depth test, are used in different multipass algorithms.
  • the final color-buffer is down-loaded to the primary GPU for display.
  • Screen based compositing is a puzzle like merging of image portions from all GPUs into a single image at the primary GPU, and sent out to display. It is a much simpler procedure than Test Based, no tests are needed. While the primary GPU is sending its color-buffer segment to display, the Merger reads back other GPUs color-buffer segments to host's memory just for downloading them into primary GPU's FB for display. None functioning mode is a non-compositing option moving the incoming Frame Buffer to the display. It is used when no compositing is required. In time division a single color-buffer is just read back from a GPU to host's memory and downloaded to primary GPU for display. In a non- parallel case of single GPU, usually the primary GPU is employed for rendering, so no host memory transit is needed.
  • the hardware embodiment is the new Graphic Hub Based Architecture of present invention, block diagramed in Fig. 6B, showing the Profiling and Control Mechanism (400) that supervises the flexible Hub based structure creating a real-time adaptively parallel multi-GPU system. Since the profiling and Control Mechanism (400) has been already thoroughly described in reference to Fig. 4A, we concentrate on the Decompose (401 '), Distribute (402"), and Recompose (403") modules.
  • the Decompose is a software module residing in the host, while Distribute and Recompose Modules are hardware based components residing in the Hub hardware, external to the host.
  • the Decompose Module is similar to the one of software embodiment, described above. Therefore we indicate only the dissimilarities of this module in hardware embodiment of present invention.
  • OS-GPU Interface and Utilities block Additional function of the OS-GPU Interface and Utilities block is driving the Hub hardware by means of soft driver.
  • the function of the Graphic Hub hardware is to interconnect the host and the cluster of GPUs, as shown in Fig. 6B.
  • Distribute Module (402") and Recompose Module (403").
  • the Distribute Module resides before the cluster, delivering commands and data for rendering (the "pre GPU unit"), and the Recompose Module that comes after the cluster and collects post rendering data (“post GPU unit”), however physically both units share the same hardware unit (e.g. silicon chip).
  • the Distribute Module (402") consists of three functional units: Router Fabric, Profiler, and Hub Control.
  • the Router Fabric is a configurable switch (e.g. 5 way PCI express xl6 lanes switch) that distributes the stream of geometric data and commands to GPUs. It can be set to one of three sub- states described therein before: Divide, Broadcast, and Single.
  • the Profiler being close to the raw data passing by, monitors these data for profiling.
  • the collected data is mainly related to the performance of Geometry subsystem.
  • Another part of Hub profiling is resident to the Recompose Module. Both profilers unify their performance data and deliver it as a feedback to Profiling and Control Mechanism, via Decompose Module.
  • the Hub Control a central control unit to the Hub, is under control of the Distributed Graphics Function Control unit of the Profiling and Control Mechanism at the host.
  • the Recompose Module (403") consists of hardware blocks of Merge management, Merger, Profiler and Router Fabric.
  • the Merge management unit handles the read-back of frame buffers and the compositing sub- states of: test based, screen based and none, described above in great detail.
  • the Merger is an algorithmic module that performs the different compositing algorithms of object division, image division and time division.
  • the Profiler collects performance data related to the pixel subsystem of GPUs. This data is passed to the other profiling unit (at Distribute Module), unified and moved to the host.
  • the other profiling unit at Distribute Module
  • the Router Fabric is a configurable switch (e.g. 5 way PCl express xl 6 lanes switch) that collects the streams of read-back FB data from GPUs, to be delivered to the Merger unit.
  • a configurable switch e.g. 5 way PCl express xl 6 lanes switch
  • Fig. 7A shows an illustrative example of software architecture for the multi-mode parallel graphics rendering system of the present invention comprising two GPUs (700).
  • This illustrative system architecture is implemented on a conventional PC platform with a dual-bus chipset.
  • Its software package (701 ) comprises Profiling and Control Mechanism (400) and a suit of three parallelism driving modules namely: the Decomposing Module (401), the Distributing Module (402) and the Recomposing Module (403).
  • Fig. 7B shows an illustrative example of hardware (Hub-based) architecture for the multi- mode parallel graphics rendering system of the present invention (710), implemented on a conventional PC architecture with a single-bus chipset.
  • the illustrative system architecture comprises a software driver (711 ) and Graphic Hub.
  • the software components comprise the Profiling and Control Mechanism (400), and the Decomposing module (401).
  • the cluster of GPUs (717) includes primary GPU (715 primary) attached to Display and number of secondary GPUs (715).
  • the multi-mode parallel graphics rendering system of present invention employing automatic profiling and multiple GPU control mechanism has two embodiments, software and hardware.
  • the present invention can be implemented on a great variety of conventional PC, laptop, servers and other architectures, as well as new systems in the following ways
  • FIG. 8 A a general approach is shown for a hardware implementation of the system of the present invention using multiple discrete graphic cards.
  • Figs, 8B-8D there are shown three possible packaging options.
  • Fig. 8B there is shown an extender card (81 1) with a graphic Hub chip, on a PC motherboard (814), having two graphic card mounted (812, 813).
  • Fig. 8C there is sbown an external multiple-GPU box, having graphic HUB chip on backplane, connected by PCIexpress cable to the host.
  • Fig. 8D there is shown a Graphic Hub chip (402" + 403") implemented on a motherboard (831), with multiple graphic cards (832).
  • Fig. 8 E a general approach is shown for a software implementation of system of the present invention using multiple discrete GPUs.
  • Tn Figs. 8F-8H there are three possible three possible options here.
  • Fig. 8F there is shown a PC platform with dual GPU cards plus software embodiment of present invention.
  • Fig. 8G there is shown a PC or another platform with descrete multiple GPU card and plus software embodiment of present invention.
  • Fig. 8H there is shown an external multiple-GPU box, connected by PCIexpress cable to the host, plus software embodiment of present invention.
  • FIG. 9A a general approach is shown for a hardware implementation of present invention using single graphic card with multiple GPUs.
  • Fig. 9b one option is shown, concept of the above
  • Fig. 10 a general approach is shown for hardware implementation of system of the present invention using system on chip (SOC) (1001 ) with monolithic Hub implementation and multiple GPUs.
  • SOC system on chip
  • Fig. 1OB one possible SOC (1001) implementation is shown conceptually.
  • Fig. 1OC a general approach is shown for a software implementation of system of the present invention (701) using multiple GPUs chip (1031).
  • Fig. 1 1 A a general approach is shown for a hardware implementation of system of the present invention using integrated graphic device (IGD, 1 101) implementation including silicon embodiment of hardware distributor and recomposer of present invention.
  • IGD integrated graphic device
  • Fig. 1 IB a general approach is shown for a software implementation of the system of the present invention, wherein an integrated graphics device (IGD, 1111) plus software embodiment of present invention.

Abstract

La présente invention concerne un système graphique en 3D parallèle multimode qui comporte plusieurs pipelines de traitement graphique avec plusieurs unités de traitement graphique (GPU) acceptant un processus de rendu graphique parallèle avec des modes de fonctionnement de division de temps, de trame et d'objet. Chaque GPU comprend une mémoire vidéo, un sous-système de traitement géométrique et un sous-système de traitement de pixel. Selon cette invention, un profilage de scène en 3D est réalisé en temps réel et l'état/les modes de parallélisation du système sont commandés de façon dynamique afin de répondre aux exigences des applications graphiques. Les plusieurs modes de rendu graphique parallèle utilisent un profilage d'application graphique en temps réel et une commande dynamique sur des modes de fonctionnement parallèle de division de temps, de trame et d'objet, sur la même plate-forme graphique parallèle, lesquelles opérations peuvent être mises en oeuvre sur des architectures de système de calcul sur PC.
PCT/IB2007/003464 2003-11-19 2007-01-18 Système de rendu graphique parallèle multimode utilisant un profilage de scène automatique en temps réel et une commande de mode WO2008004135A2 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CA002637800A CA2637800A1 (fr) 2006-01-18 2007-01-18 Systeme de rendu graphique parallele multimode utilisant un profilage de scene automatique en temps reel et une commande de mode
US12/077,072 US20090027383A1 (en) 2003-11-19 2008-03-14 Computing system parallelizing the operation of multiple graphics processing pipelines (GPPLs) and supporting depth-less based image recomposition
US12/231,304 US8284207B2 (en) 2003-11-19 2008-08-29 Method of generating digital images of objects in 3D scenes while eliminating object overdrawing within the multiple graphics processing pipeline (GPPLS) of a parallel graphics processing system generating partial color-based complementary-type images along the viewing direction using black pixel rendering and subsequent recompositing operations
US12/231,296 US20090179894A1 (en) 2003-11-19 2008-08-29 Computing system capable of parallelizing the operation of multiple graphics processing pipelines (GPPLS)
US12/231,295 US20090128550A1 (en) 2003-11-19 2008-08-29 Computing system supporting parallel 3D graphics processes based on the division of objects in 3D scenes
US13/646,710 US20130120410A1 (en) 2003-11-19 2012-10-07 Multi-pass method of generating an image frame of a 3d scene using an object-division based parallel graphics rendering process

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US75960806P 2006-01-18 2006-01-18
US60/759,608 2006-01-18

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/648,160 Continuation-In-Part US8497865B2 (en) 2003-11-19 2006-12-31 Parallel graphics system employing multiple graphics processing pipelines with multiple graphics processing units (GPUS) and supporting an object division mode of parallel graphics processing using programmable pixel or vertex processing resources provided with the GPUS

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/655,735 Continuation-In-Part US8085273B2 (en) 2003-11-19 2007-01-18 Multi-mode parallel graphics rendering system employing real-time automatic scene profiling and mode control

Publications (3)

Publication Number Publication Date
WO2008004135A2 true WO2008004135A2 (fr) 2008-01-10
WO2008004135A9 WO2008004135A9 (fr) 2008-03-20
WO2008004135A3 WO2008004135A3 (fr) 2009-04-23

Family

ID=38894955

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2007/003464 WO2008004135A2 (fr) 2003-11-19 2007-01-18 Système de rendu graphique parallèle multimode utilisant un profilage de scène automatique en temps réel et une commande de mode

Country Status (2)

Country Link
CA (1) CA2637800A1 (fr)
WO (1) WO2008004135A2 (fr)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010041215A1 (fr) * 2008-10-09 2010-04-15 Nxp B.V. Système graphique d’ombrage de primitives géométriques
US7970968B2 (en) * 2004-03-25 2011-06-28 Sony Corporation Apparatus and method for controlling plural functional blocks using common command
CN102449665A (zh) * 2009-06-02 2012-05-09 高通股份有限公司 显示经渲染的图形元素的性能度量的视觉表示
US8319782B2 (en) 2008-07-08 2012-11-27 Dell Products, Lp Systems and methods for providing scalable parallel graphics rendering capability for information handling systems
WO2014108214A1 (fr) * 2013-01-14 2014-07-17 Neweb Système client-serveur pour un magasin de meubles sur internet
CN107958436A (zh) * 2017-11-24 2018-04-24 中国航空工业集团公司西安航空计算技术研究所 一种面向OpenGL的图形负载量化检测方法
WO2020004695A1 (fr) * 2018-06-29 2020-01-02 주식회사 에이펀인터렉티브 Système de réalisation d'un rendu parallèle en temps réel d'une image de capture de mouvement à l'aide d'une gpu
CN113971047A (zh) * 2021-10-22 2022-01-25 中国联合网络通信集团有限公司 分级平行系统的构建方法、应用方法、计算机设备及介质
CN114820279A (zh) * 2022-05-18 2022-07-29 北京百度网讯科技有限公司 基于多gpu的分布式深度学习方法、装置及电子设备
CN117830489A (zh) * 2024-03-05 2024-04-05 浙江小牛哥科技有限公司 智能室内设计图像渲染系统

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841444A (en) * 1996-03-21 1998-11-24 Samsung Electronics Co., Ltd. Multiprocessor graphics system
US6292200B1 (en) * 1998-10-23 2001-09-18 Silicon Graphics, Inc. Apparatus and method for utilizing multiple rendering pipes for a single 3-D display
US20020145612A1 (en) * 2001-01-29 2002-10-10 Blythe David R. Method and system for minimizing an amount of data needed to test data against subarea boundaries in spatially composited digital video
US6741243B2 (en) * 2000-05-01 2004-05-25 Broadcom Corporation Method and system for reducing overflows in a computer graphics system
US6778177B1 (en) * 1999-04-15 2004-08-17 Sp3D Chip Design Gmbh Method for rasterizing a graphics basic component
US6844879B2 (en) * 2001-07-19 2005-01-18 Nec Corporation Drawing apparatus
US6864894B1 (en) * 2000-11-17 2005-03-08 Hewlett-Packard Development Company, L.P. Single logical screen system and method for rendering graphical data
US6885376B2 (en) * 2002-12-30 2005-04-26 Silicon Graphics, Inc. System, method, and computer program product for near-real time load balancing across multiple rendering pipelines

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841444A (en) * 1996-03-21 1998-11-24 Samsung Electronics Co., Ltd. Multiprocessor graphics system
US6292200B1 (en) * 1998-10-23 2001-09-18 Silicon Graphics, Inc. Apparatus and method for utilizing multiple rendering pipes for a single 3-D display
US6778177B1 (en) * 1999-04-15 2004-08-17 Sp3D Chip Design Gmbh Method for rasterizing a graphics basic component
US6741243B2 (en) * 2000-05-01 2004-05-25 Broadcom Corporation Method and system for reducing overflows in a computer graphics system
US6864894B1 (en) * 2000-11-17 2005-03-08 Hewlett-Packard Development Company, L.P. Single logical screen system and method for rendering graphical data
US20020145612A1 (en) * 2001-01-29 2002-10-10 Blythe David R. Method and system for minimizing an amount of data needed to test data against subarea boundaries in spatially composited digital video
US6844879B2 (en) * 2001-07-19 2005-01-18 Nec Corporation Drawing apparatus
US6885376B2 (en) * 2002-12-30 2005-04-26 Silicon Graphics, Inc. System, method, and computer program product for near-real time load balancing across multiple rendering pipelines

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7970968B2 (en) * 2004-03-25 2011-06-28 Sony Corporation Apparatus and method for controlling plural functional blocks using common command
US8319782B2 (en) 2008-07-08 2012-11-27 Dell Products, Lp Systems and methods for providing scalable parallel graphics rendering capability for information handling systems
WO2010041215A1 (fr) * 2008-10-09 2010-04-15 Nxp B.V. Système graphique d’ombrage de primitives géométriques
CN102449665A (zh) * 2009-06-02 2012-05-09 高通股份有限公司 显示经渲染的图形元素的性能度量的视觉表示
WO2014108214A1 (fr) * 2013-01-14 2014-07-17 Neweb Système client-serveur pour un magasin de meubles sur internet
CN107958436B (zh) * 2017-11-24 2021-05-07 中国航空工业集团公司西安航空计算技术研究所 一种面向OpenGL的图形负载量化检测方法
CN107958436A (zh) * 2017-11-24 2018-04-24 中国航空工业集团公司西安航空计算技术研究所 一种面向OpenGL的图形负载量化检测方法
WO2020004695A1 (fr) * 2018-06-29 2020-01-02 주식회사 에이펀인터렉티브 Système de réalisation d'un rendu parallèle en temps réel d'une image de capture de mouvement à l'aide d'une gpu
CN113971047A (zh) * 2021-10-22 2022-01-25 中国联合网络通信集团有限公司 分级平行系统的构建方法、应用方法、计算机设备及介质
CN113971047B (zh) * 2021-10-22 2023-06-23 中国联合网络通信集团有限公司 分级平行系统的构建方法、应用方法、计算机设备及介质
CN114820279A (zh) * 2022-05-18 2022-07-29 北京百度网讯科技有限公司 基于多gpu的分布式深度学习方法、装置及电子设备
CN117830489A (zh) * 2024-03-05 2024-04-05 浙江小牛哥科技有限公司 智能室内设计图像渲染系统
CN117830489B (zh) * 2024-03-05 2024-05-03 浙江小牛哥科技有限公司 智能室内设计图像渲染系统

Also Published As

Publication number Publication date
WO2008004135A3 (fr) 2009-04-23
CA2637800A1 (fr) 2008-01-10
WO2008004135A9 (fr) 2008-03-20

Similar Documents

Publication Publication Date Title
US8085273B2 (en) Multi-mode parallel graphics rendering system employing real-time automatic scene profiling and mode control
US8754894B2 (en) Internet-based graphics application profile management system for updating graphic application profiles stored within the multi-GPU graphics rendering subsystems of client machines running graphics-based applications
US8125487B2 (en) Game console system capable of paralleling the operation of multiple graphic processing units (GPUS) employing a graphics hub device supported on a game console board
US20080094403A1 (en) Computing system capable of parallelizing the operation graphics processing units (GPUs) supported on a CPU/GPU fusion-architecture chip and one or more external graphics cards, employing a software-implemented multi-mode parallel graphics rendering subsystem
US20080211817A1 (en) Internet-based application profile database server system for updating graphic application profiles (GAPS) stored within the multi-mode parallel graphics rendering system of client machines running one or more graphic applications
WO2008004135A2 (fr) Système de rendu graphique parallèle multimode utilisant un profilage de scène automatique en temps réel et une commande de mode
US20070291040A1 (en) Multi-mode parallel graphics rendering system supporting dynamic profiling of graphics-based applications and automatic control of parallel modes of operation
US8497865B2 (en) Parallel graphics system employing multiple graphics processing pipelines with multiple graphics processing units (GPUS) and supporting an object division mode of parallel graphics processing using programmable pixel or vertex processing resources provided with the GPUS
US7800619B2 (en) Method of providing a PC-based computing system with parallel graphics processing capabilities

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07825653

Country of ref document: EP

Kind code of ref document: A2

DPE2 Request for preliminary examination filed before expiration of 19th month from priority date (pct application filed from 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2637800

Country of ref document: CA

NENP Non-entry into the national phase in:

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2007825653

Country of ref document: EP

122 Ep: pct application non-entry in european phase

Ref document number: 07825653

Country of ref document: EP

Kind code of ref document: A2