WO2007145307A1

WO2007145307A1 - Semiconductor integrated circuit device

Info

Publication number: WO2007145307A1
Application number: PCT/JP2007/062079
Authority: WO
Inventors: Shunsuke Toyoshima; Hiroyasu Ishizuka; Kazuo Tanaka
Original assignee: Renesas Technology Corp.
Priority date: 2006-06-15
Filing date: 2007-06-15
Publication date: 2007-12-21
Also published as: JP2011254100A; JPWO2007145307A1; JP4873504B2

Abstract

A semiconductor integrated circuit device wherein an ESD protection circuit is arranged and the number of external terminals is efficiently arranged. First and second power supply cells and an input/output cell are arranged, corresponding to first and second power supply pads for supplying first and second power supply voltages and a signal pad. A first power supply line is supplied with the first power supply voltage supplied from the first power supply pad, and a second power supply line is supplied with the second power supply voltage supplied from the second power supply pad. A first MOSFET is provided for permitting a surge current of the first power supply line and the second power supply line to flow to the input/output cell. The first and the second power supply cells are composed of a time constant circuit for having the first MOSFET arranged on the input/output cell temporarily in an on status, corresponding to positive static electricity at the first power supply pad; and a unidirectional element for permitting currents to flow to the first and the second power supply pads, respectively.

Description

Specification

Semiconductor integrated circuit device

Import by reference

[0001] This application claims the priority of Japanese Patent Application No. 2006-165473, filed on June 15, 2006, and is incorporated herein by reference. "

Technical field

The present invention relates to a semiconductor integrated circuit device, and relates to a technology that is effective when applied to an ESD (Electro-Static Discharge) protection circuit.

Background art

As an example of a distributed ESD circuit, WO2004Z015776 discloses a device in which a shunt device is provided in an input / output cell and is controlled by a trigger circuit provided in one or a plurality of power supply cells. In this distributed ESD circuit, a shunt device is also provided in the power cell, a boost bus is connected to the trigger circuit, and the trigger circuit drives the control electrode of the shunt device to a large voltage level during an ESD event. This is intended to reduce the on-resistance.

[0004] The number of external terminals is increased to several hundreds due to the high functionality of semiconductor integrated circuit devices having a microcomputer function. Power supply terminals must be supplied with the same power supply voltage through multiple power supply terminals in order to reduce power supply impedance. For example, in the semiconductor integrated circuit device as described above, the power supply terminal occupies about 10% of the total number of terminals. In recent years, the size of the input / output cell for signal processing is larger than that of the input / output cell because the ESD protection element for escaping ESD surge is arranged in the power cell, compared to the recent trend toward downsizing of the signal input / output cell. Become.

Disclosure of the invention

Problems to be solved by the invention

FIG. 9 shows a schematic layout diagram of a semiconductor integrated circuit device studied by the inventors of the present application prior to the present invention. The power cell GCNMOS has a time constant circuit CR that detects the surge voltage and a large size to discharge the powerful surge voltage at high speed. This is a larger size than the input / output cell IO. Since the power supply impedance needs to be evenly reduced, the power supply cell GCNMOS needs to be distributed and arranged for each of the plurality of input / output cells IO. Therefore, the input / output cell IO and the power cell GCNMOS of different sizes are mixedly arranged as shown in FIG. 9, and the pitch of the pad (PAD) on both sides of the power cell GCNMOS is set to the size of the power cell GCNMOS. Correspondingly widen. In the present inventor, if the input / output cell IO and the power supply cell GCNMOS are made different sizes as described above, a large space dl is generated on both sides of the power supply cell GCNMOS which is enlarged when viewed from the PAD side. We found that the number of PADs that can be placed is limited. In other words, the present inventor has realized that if cells of almost the same size are used, the interval between the PADs becomes smaller as the interval d2 between the input / output cells IO, and the number of PADs can be increased accordingly.

An object of the present invention is to provide a semiconductor integrated circuit device that can efficiently arrange the number of external terminals while providing an ESD protection circuit. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. Means for solving the problem

[0007] The following is a brief description of an outline of typical inventions among inventions disclosed in the present application. First and second power supply cells and input / output cells are provided corresponding to the first and second power supply pads and signal pads for supplying the first and second power supply voltages, respectively. The first power supply voltage supplied from the first power supply pad is supplied to the first power supply line, and the second power supply voltage supplied from the second power supply pad is supplied to the second power supply line. A first MOSFET is provided in the input / output cell to allow surge current flow between the first and second power lines. The first and second power cells include a time constant circuit that temporarily turns on the first MOSFET provided in the input / output cell in response to positive static electricity at the first power pad, and the first and second power cells. Consists of unidirectional elements that allow current to flow to the power pads.

[0008] The ability to reduce the size of the power cell to the same size as the input / output cell by distributing and disposing the first MOSFET for discharging the surge voltage generated at the power pad in the input / output cell. BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows a circuit diagram of an input / output circuit portion of an embodiment of a semiconductor integrated circuit device according to the present invention. FIG. 1 exemplarily shows two input / output cells (IO cells) and one power cell. Each I / O cell has a P-channel output MOSFET Q1 and an N-channel output MOSFET Q2 that transmit output signals to the input / output terminal DQO, an input circuit IB that receives the input signal input from the input / output terminal DQO, and an ESD protection circuit. It includes diodes Dl and D2 and resistors Rl and R2. Diode D1 causes a direct surge current to flow from input / output terminal DQO to power supply line VCCQ, and diode D2 causes the circuit's ground potential line VSSQ force to also flow a direct surge current to external terminal DQO. Resistors R1 and R2 serve as protection elements for the MOSFETs that make up MOSFETs Ql and Q2 and input circuit IB.

[0010] In this embodiment, the IO cell is provided with a MOSFET Q3 for discharging a surge voltage due to the power supply terminal VCCQ or the like. This MOSFET Q3 is formed with a small size. As a result, the occupied area of the IO cell is not substantially increased. The other IO cells including the IO cells corresponding to the input / output terminal DQn have the same configuration as described above. In other words, in each of the IO cells provided in the semiconductor integrated circuit device according to the present invention, the diodes Dl, D2 and the like that discharge the surge voltage at the corresponding input / output terminals DQO to DQn (n is a positive integer) are connected. In contrast, MOSFET power that discharges surge voltage due to power supply terminals VCCQ, etc. is divided like MOSFETQ3 and distributed to each IO cell.

[0011] The power cell corresponding to the power supply terminal VCCQ is provided with a time constant circuit GC for detecting a positive surge voltage of the power supply terminal VCCQ. In addition, a diode D3 is provided to discharge negative surge voltage at the power supply terminal VCCQ. This diode D3 carries a surge current so that the ground line VS SQ force is also directed to the power supply terminal VCCQ. Although not shown, the power supply cell corresponding to the circuit ground terminal VSSQ has the same configuration. The time constant circuit GC output lines GTDV and WLD V corresponding to the power supply terminal VCCQ and the ground terminal VSSQ and the time constant circuit GC output lines GTDV and WLDV (not shown) are connected in common to the IO cell. Connected to the gate and well of MOSFETQ3 etc. FIG. 2 shows a circuit diagram of an embodiment of the power cell. The time constant circuit GC is also composed of an integration circuit force consisting of a resistor R3 and a capacitor C1. The charge voltage of the capacitor C1 is supplied to the input terminals of the inverter circuits INV1 and INV2. The output terminals of these inverter circuits INV1 and INV2 are connected to output lines GTDV and WLDV. These inverter circuits INV1 and INV2 operate by receiving operating voltage from VCCQ.

[0013] For example, when a positive surge voltage is generated at the power supply terminal VCCQ, VCCQ power operating voltage is supplied to the inverter circuits INV1 and INV2, and the input terminal is delayed by the time constant circuit to a high level corresponding to the surge voltage. Is reported. Therefore, the inverter circuits I NV1 and INV2 maintain a high level from when a positive surge voltage is generated at the power supply terminal VCCQ until the logic voltage of the capacitor C1 charge voltage force inverter circuit is reached. Then, turn on the MOSFETQ3, etc., distributed in the IO cells, and discharge the surge voltage.

FIG. 3 shows a specific circuit diagram of an embodiment of the power cell. A P-channel MOSFET Q10 formed in series is provided as the resistor R3 in FIG. 2 between the power supply terminal VCCQ and the ground terminal VSSQ.

[0015] Capacitor C1 in FIG. 2 is configured by the gate capacitance of MOSFET Q11. That is, the source, drain, and tool of the MOS FET Q11 are connected to the circuit ground terminal VSSQ, and the gate is connected to the drain of the MOSFET Q10 corresponding to one end of the resistor element R3.

The inverter circuit INV1 in FIG. 2 includes a P-channel MOSFET Q12 and an N-channel MOSFET Q13. The inverter circuit INV2 in FIG. 2 is composed of a P-channel MOSFETQ 14 and an N-channel MOSFETQ15. The gates of the MOSFETs Q12 to Q15 are connected in common and connected to the gate of the MOSFET Q11 as the capacitor C1.

[0017] The output terminal of the CMOS inverter circuit composed of MOSFETs Q12 and Q13 is connected to the output line GT DV. The output terminal of the CMOS inverter circuit consisting of MOSFETs Q14 and Q15 is connected to the output line WLDV. Then, pull-down resistors RIO, R11 are provided between the output terminals of the two inverter circuits and the ground terminal VSSQ. MOSFETs Q10 to Q15 have a high withstand voltage structure because the gate insulating film is formed thick. MOSFETQ3, etc., whose gate is connected to the output line GTDV, has the same high voltage structure. FIG. 4A and FIG. 4B are explanatory diagrams of the operation of the MOSFET provided in the IO cell. Figure 4A shows the circuit symbol for the MOSFET, and Figure 4B shows the MOSFET element structure and parasitic elements. In this MOSFET, the output lines GTDV and WLDV are connected to the gate G and the well WELL, and both are made high by the surge voltage. Therefore, in addition to flowing current as a MOSFET, a parasitic transistor is constructed with n + type drain D as collector C, p type well as base B, and n + type source S as emitter E. Current is allowed to flow. As a result, the parasitic transistor can be operated by controlling the well potential WELL, so that a larger current can flow than when the surge current is flowed only as a MOSFET with the well potential equal to the source.

FIG. 5 shows a circuit diagram of another embodiment of the power cell. This embodiment is directed to a power supply cell that supplies a low voltage VDD for an internal circuit of a semiconductor integrated circuit device. This power cell has a MOSFET Q4 of the same size as the MOSFET Q3 provided in the IO cell, for example, within a range that does not become larger than the size of the 0 cell. Thereby, it is possible to cause a surge current to flow even in the power cell itself. This configuration can be similarly applied to the power cell of the power supply terminal VCCQ for the input / output circuit as in the embodiment of FIG.

FIG. 6 shows a layout diagram of an embodiment of a semiconductor integrated circuit device according to the present invention. In the semiconductor integrated circuit device (LSI chip) of this embodiment, input / output circuits are arranged around the chip, and an internal circuit is provided in the center of the chip. Although not particularly limited, the internal circuit is divided into two circuits such as internal circuit 1 and internal circuit 2. In the input / output circuit, a plurality of input / output circuit cells corresponding to a plurality of external terminals are arranged in the periphery of the chip. A plurality of power supply cells are arranged for a plurality of input / output circuit cells in order to reduce the power supply impedance and stabilize the power supply impedance. In FIG. 6, the power cells are shown with diagonal lines to distinguish them from the input / output circuits. This power cell has operating voltages VCCQ and VSSQ for input / output circuits and operating voltages VDD and VSS for internal circuits.

The input / output circuit cell in FIG. 6 is provided with an input / output circuit IO and an N-channel MOSFET as shown in FIG. Therefore, the input / output circuit cell is represented as IO + NMOS. The power cell is composed of a time constant circuit GC. As a result, power cell and input / output circuit cell support The pitch between the input / output terminal DQ and the power supply terminals VCCQ and VSSQ and the power supply terminals VDD and VSS for the internal circuits can be made to be a substantially constant narrow pitch d2, as shown in FIG. Since the useless space as in the above configuration does not occur, the chip size of the semiconductor integrated circuit device ((LSI chip) circuit) can be reduced. On the other hand, if it is! /, The number of external terminals can be increased.

[0022] For internal circuit 1 and internal circuit 2, drive signals (GTDV, WLDV) output from time constant circuit GC to power supply lines VDD and VSS arranged so as to surround internal circuits 1 and 2 ) Is provided. In Figure 6, this MOSFET is shown in black, like NMOS. Although not particularly limited, an inverter circuit as a buffer amplifier BA is provided corresponding to the NMOS. This buffer amplifier amplifies the drive signals from the output lines GTDV and WLDV to speed up the switching operation of the MNOS. Although not particularly limited, the NMOS corresponding to the internal circuit uses a MOSFET having a gate breakdown voltage equivalent to that of the MOSFET constituting the internal circuit, unlike the NMOS provided in the IO cell.

FIG. 7 shows a layout diagram of another embodiment of the semiconductor integrated circuit device according to the present invention. In the semiconductor integrated circuit device (LSI chip) of this embodiment, paying attention to the fact that the bonding pitch of bonding pads at the corners around the chip becomes coarse, an N-channel MOSFET for discharging a surge voltage is provided there. In other words, prepare an M NOS cell as shown by the dotted line in FIG. 7 and place the MNOS cell appropriately in the part where the spacing between the bonding pads PAD at the corners of the chip becomes rough, such as d3. That's it. Roughening the pitch of the bonding pad PAD is also the force required to maintain the spacing between adjacent wires arranged diagonally at the chip corner. When an NMOS cell is prepared as described above, it can be used to reduce the size of the N-channel MOSFET provided in the IO cell.

FIG. 8 shows a layout diagram of another embodiment of the semiconductor integrated circuit device according to the present invention. The semiconductor integrated circuit device (LSI chip) of this embodiment pays attention to the fact that the corner around the chip is a dead space where no IO cell or power cell is provided, and an N-channel MOSFET that discharges a surge voltage there. To be provided. That is, the dotted line in Figure 8 An NMOS cell as shown in Fig. 2 is prepared, and the NMOS cell is arranged at the corner of the chip. When an NMOS cell is prepared as described above, it can be used to reduce the size of the N-channel MOSFET provided in the IO cell. Further, the NMOS cell of FIG. 7 may be combined.

[0025] While the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. It is. For example, the MOSFET Q3 well may be connected to the source and the inverter circuit INV2 of the time constant circuit GC may be omitted. If there are two types of circuit ground potential pins, VS SQ and VSS, a surge protection circuit is provided with a diode that sends a surge current to VSS, and a diode that sends a surge current to VSS vs VSSQ. It is done. These diodes may be appropriately provided on the semiconductor chip. In addition, a buffer amplifier that amplifies a drive signal such as MOS FET Q3 may be provided in a portion where the pad pitch is wide as indicated by d3 in FIG. Furthermore, the present invention can be similarly applied to a power supply that supplies an external terminal power of 3 or more. The present invention can be widely used as an ESD protection circuit for semiconductor integrated circuit devices. While the above description has been made with reference to embodiments, it will be apparent to those skilled in the art that the present invention is not limited thereto and that various changes and modifications can be made within the spirit of the invention and the scope of the appended claims.

Brief Description of Drawings

FIG. 1 is a circuit diagram of an input / output circuit portion showing an embodiment of a semiconductor integrated circuit device according to the present invention.

2 is a circuit diagram showing an embodiment of the power cell of FIG.

FIG. 3 is a specific circuit diagram showing an embodiment of the power cell of FIG. 1.

FIG. 4A is an operation explanatory diagram of a MOSFET provided in the IO cell of FIG. 1.

FIG. 4B is an operation explanatory diagram of the MOSFET provided in the IO cell of FIG. 1.

FIG. 5 is a circuit diagram showing another embodiment of the power cell used in the present invention.

FIG. 6 is a layout diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention.

FIG. 7 is a layout diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention. FIG. 8 is a layout diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention.

FIG. 9 is a schematic outside layer view of a semiconductor integrated circuit device studied prior to the present invention.

Claims

The scope of the claims

[1] a first power supply pad for supplying a first power supply voltage;

A second power supply pad for supplying a second power supply voltage;

A signal pad for inputting or outputting signals;

A first power cell provided corresponding to the first power pad;

A second power cell provided corresponding to the second power pad;

An input / output cell provided corresponding to the first signal pad;

A first power supply line for supplying a first power supply voltage supplied from the first power supply pad; and a second power supply line for supplying a second power supply voltage supplied from the second power supply pad; The cell includes a circuit for inputting or outputting a signal, an electrostatic protection circuit, and a first MOSFET provided between the first power supply line and the second power supply line,

The first power supply cell includes a time constant circuit that temporarily turns on the first MOSFET provided in the input / output cell in response to positive static electricity at the first power supply pad; and the first power supply pad. And a unidirectional element that flows current toward

The second power cell includes a time constant circuit for temporarily turning on the first MOSFET provided in the input / output cell in response to positive static electricity at the second power pad, and the second power pad. And a unidirectional element for passing a current toward

Semiconductor integrated circuit device.

[2] The semiconductor integrated circuit device according to claim 1,

A third power supply pad for supplying a third power supply voltage;

A fourth power supply pad for supplying a fourth power supply voltage;

A third power cell provided corresponding to the third power pad;

A fourth power cell provided corresponding to the fourth power pad;

A third power supply line for supplying a third power supply voltage supplied from the third power supply pad; a fourth power supply line for supplying a fourth power supply voltage supplied from the fourth power supply pad; and the third power supply line. A plurality of second MOSFETs provided between a fourth power supply line, the third power supply voltage and the fourth voltage transmitted through the third power supply line and the fourth power supply line as operating voltages, and the input / output An internal circuit that transmits and receives signals to and from the cell, The third and fourth power supply cells have the same configuration as the first and second power supply cells, and control the plurality of second MOSFETs by the time constant circuit.

Semiconductor integrated circuit device.

[3] In the semiconductor integrated circuit device according to claim 2,

A semiconductor integrated circuit device in which a plurality of the first to fourth power cells and the input / output cells are arranged at a regular pitch corresponding to wire bonding.

[4] The semiconductor integrated circuit device according to claim 3,

The semiconductor integrated circuit device, wherein an operating voltage corresponding to the first power supply voltage and the second power supply voltage is greater than an operating voltage corresponding to the third power supply voltage and the fourth power supply voltage.

[5] In the semiconductor integrated circuit device according to claim 4,

The semiconductor integrated circuit device, wherein the first and second power cells have a third MOSFET having an element size equivalent to a MOSFET used for the time constant circuit between the first power line and the second power line.

[6] The semiconductor integrated circuit device according to claim 4,

The semiconductor integrated circuit device, wherein the third and fourth power cells have a fourth MOSFET having an element size equivalent to a MOSFET used for the time constant circuit between the third power line and the fourth power line.

[7] The semiconductor integrated circuit device according to claim 5,

A semiconductor integrated circuit device, wherein each of the plurality of second MOSFETs is provided with a buffer circuit for amplifying the control signal of the time constant circuit power.

[8] The semiconductor integrated circuit device according to claim 6,

[9] The semiconductor integrated circuit device according to claim 7,

A first protection cell including a fifth MOSFET provided between the first power supply line and the second power supply line and controlled by the time constant circuit, to maintain a regular pitch corresponding to the wire bonding; However, a semiconductor integrated circuit device in which the first protection cell is disposed between the power supply cell or the input / output cell.

[10] The semiconductor integrated circuit device according to claim 8,

[11] The semiconductor integrated circuit device according to claim 7,

A second protection cell including a sixth MOSFET provided between the first power supply line and the second power supply line and controlled by the time constant circuit, wherein the second protection cell is disposed at the chip corner portion; Semiconductor integrated circuit device.

[12] The semiconductor integrated circuit device according to claim 8,