JP2011119415A - Semiconductor integrated device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrostatic protection circuit suitable for the output circuit of a semiconductor integrated circuit for driving a display panel where snap-back operation does not occur in the semiconductor integrated circuit. <P>SOLUTION: The electrostatic protection circuit includes a PMOS transistor 2 formed on a semiconductor substrate with a gate electrode connected to an external connection terminal 10, and an NMOS transistor 3 formed on the semiconductor substrate with a gate electrode connected to the external connection terminal 10, wherein a surge current of positive polarity is dissipated as a forward current to a VDD power supply terminal 11a through a pn junction between the semiconductor substrate and the source region and drain region of the PMOS transistor 2, and a surge current of negative polarity is dissipated as a forward current to a VSS power supply terminal 11b through a pn junction between the semiconductor substrate and the source region and drain region of the NMOS transistor 3. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated device, and more particularly to an electrostatic protection circuit for preventing electrostatic breakdown in a semiconductor integrated device, for example, an electrostatic protection circuit for a semiconductor integrated device for driving a display panel.

  Regarding the occurrence of a failure phenomenon in a semiconductor integrated device, the following may be mentioned.

  In the process of handling a semiconductor integrated device, static electricity may flow into the semiconductor integrated device and cause a failure due to contact between the charged mechanical device or human body and the semiconductor integrated device.

  Thus, when static electricity is applied to the semiconductor integrated device, an excessive current (surge current) exceeding the steady state instantaneously flows inside the semiconductor integrated device. In response to this excessive current, an excessive voltage is applied to the components constituting the internal circuit of the semiconductor integrated device, causing breakdown of the junction, breakdown of the insulating film, fusing of the wiring, etc. in the semiconductor integrated device. The internal circuit of the integrated device will be destroyed. The destruction of the internal circuit of the semiconductor integrated device due to such application of static electricity is called electrostatic breakdown.

  Therefore, it is necessary to take measures for preventing electrostatic breakdown when designing a semiconductor integrated device.

  In general, an electrostatic protection element is disposed between an external connection terminal and an internal circuit of a semiconductor integrated device, and measures are taken to use this as an electrostatic detour (electrostatic protection circuit). Here, as the electrostatic protection circuit, a circuit using a protective NMOS has been conventionally used, and such an electrostatic protection circuit is disclosed in, for example, Patent Document 1.

  Hereinafter, the electrostatic protection circuit disclosed in Patent Document 1 will be described with reference to FIG.

  FIG. 4 shows an output unit of a conventional semiconductor integrated device.

  The semiconductor integrated device 200 includes an internal circuit 24 for performing various signal processing, an external connection terminal 20 for outputting an internal signal generated by the internal circuit 24 to the outside of the semiconductor integrated device, and the internal circuit 24. And an electrostatic protection circuit 21 provided between the external connection terminals 20. Here, the internal circuit 24 includes an output buffer 24 a having a CMOS configuration that outputs an internal signal to the external snow image terminal 20. The output buffer 24a has a PMOS transistor 25 and an NMOS transistor 26 connected in series via a current limiting resistor 23 between the VDD power supply terminal 21a and the VSS power supply terminal 21b. The PMOS transistor 25 is connected to the VDD power supply 21a, the NMOS transistor 26 is connected to the VSS power supply terminal 21b, a current limiting resistor 23 is inserted between the transistors 21a and 21b, and the gates of both transistors are common. It is connected.

  The electrostatic protection circuit 21 includes an NMOS transistor 22 connected between the output terminal 20 and the VSS power source 21b, and the current limiting resistor 23 constitutes the electrostatic protection circuit 21. .

  Next, the operation will be described.

  In such a semiconductor integrated device 200, the internal signal generated by the internal circuit 24 is converted into a signal level suitable for the signal level outside the semiconductor integrated device 200 by the output buffer 24 a, and is sent via the output terminal 20. And output to the outside of the semiconductor integrated device 200.

  In such a semiconductor integrated device 200, a positive surge current due to electrostatic discharge (ESD) applied from the external connection terminal 20 is generated by the protective NMOS transistor 22 performing a snapback operation. Detour to terminal (VSS terminal) 21b. At this time, a current limiting resistor 23 is connected between the drain terminal of the NMOS transistor 26 and the external connection terminal 20 so that the NMOS transistor 26 constituting the output buffer 24 a of the internal circuit 24 is not destroyed.

  A negative surge current caused by electrostatic discharge (ESD) applied from the external connection terminal 20 is supplied to the power supply terminal (VSS terminal) 21b via a parasitic diode formed between the drain and the substrate of the protective NMOS transistor 22. Detour. In this way, the surge current applied from the external connection terminal 20 can be either a positive or negative surge current, and can be bypassed to the power supply terminal (VSS terminal) 21b via the protective NMOS transistor 22. Is trying to prevent electrostatic breakdown.

JP 2008-305852 A

  However, when the electrostatic protection circuit using the prior art is applied to a semiconductor integrated device for driving a display panel, there are the following problems.

  Since the output circuit of the semiconductor integrated device for driving the display panel has a high operating voltage of about 10 to 20 V, it is very difficult to form a protective NMOS transistor that operates normally.

  FIG. 5 shows the characteristics of the medium-voltage protection NMOS transistor whose operating voltage is about 10 to 20V.

  As can be seen from FIG. 5, when the drain voltage (test pulse voltage) reaches 23 V, a snapback operation occurs and the drain current increases. As the drain current increases in this way, the ability to bypass the surge current increases.

  However, when evaluating the leakage current with the drain voltage of the intermediate voltage protection NMOS transistor being 16.5V, the leakage current of this transistor is a minute current of about 1E-10A until the snapback operation occurs. After the snapback operation occurs, it increases to about 5E-7A. This increase in leakage current is thought to occur because the junction portion of the protection NMOS transistor 22 is broken. In other words, the increase in leakage current in the protection NMOS transistor 22 causes an increase in output. This means that it is impossible to output a normal output waveform from the circuit (output buffer) 24a.

  As described above, the medium-voltage protection NMOS transistor has a problem in that when the snapback operation is performed, the junction portion is broken and the leakage current increases.

  Accordingly, there is a problem that a protection element that causes a snapback operation such as a protection NMOS transistor cannot be used as an electrostatic protection circuit of an output circuit of a semiconductor integrated device for driving a display panel.

  The present invention has been made to solve such a conventional problem, and does not cause a snapback operation, and can be used as a protection circuit for an output circuit having a high operating voltage for driving a display panel or the like. An object of the present invention is to provide a semiconductor integrated device including an electrostatic protection circuit.

  A semiconductor integrated device according to the present invention is a semiconductor integrated device having an internal circuit for performing signal processing and an external connection terminal for connecting the internal circuit to an external circuit, the internal circuit and the external connection terminal And an electrostatic protection circuit for bypassing a surge voltage applied to the external connection terminal to a power supply line, the electrostatic protection circuit being formed on a semiconductor substrate and connected to the external connection terminal An electrode having a first conductivity type MOS transistor and a second conductivity type MOS transistor formed on the semiconductor substrate and having a gate electrode connected to the external connection terminal; A negative surge current is released as a forward current to the first power supply line via a pn junction between the source region and drain region of the one-conductivity type MOS transistor and the semiconductor substrate. The second conductivity type MOS transistor is configured to escape to the second power supply line as a forward current through the pn junction between the source region and the drain region of the second conductivity type MOS transistor and the semiconductor substrate. Achieved.

  In the semiconductor integrated device, it is preferable that the present invention has a current limiting resistor connected between the internal circuit and the external connection terminal.

  According to the present invention, in the semiconductor integrated device, the internal circuit has an output buffer that outputs an internal signal generated by the internal circuit to the external circuit, and the electrostatic protection circuit serves as the external connection terminal. Preferably, it is provided between the output terminal and the output buffer.

  According to the present invention, in the semiconductor integrated device, the internal circuit has an input buffer that supplies a signal from the external circuit to the internal circuit, and the electrostatic protection circuit has an input terminal as the external connection terminal And the input buffer.

  According to the present invention, in the semiconductor integrated device, the internal circuit includes an output buffer that outputs an internal signal generated by the internal circuit to the external circuit, and an input buffer that supplies a signal from the external circuit to the internal circuit. As the static electricity protection circuit, an output side static electricity protection circuit is provided between the output terminal as the external connection terminal and the output buffer, and the input terminal as the external connection terminal and the input An input side electrostatic protection circuit is preferably provided between the buffer and the buffer.

  In the semiconductor integrated device according to the present invention, the first conductivity type MOS transistor is a PMOS transistor, the second conductivity type MOS transistor is an NMOS transistor, and the first power supply line is an electrode for supplying a VDD power supply. The second power line is preferably an electrode for supplying VSS power.

  According to the present invention, in the semiconductor integrated device, in the electrostatic protection circuit, a source electrode connection hole and a drain electrode connection hole of the PMOS transistor are connected to the external connection terminal, and a source electrode connection hole and a drain of the NMOS transistor are connected. It is preferable that an electrode connection hole and a gate electrode connection hole are connected, and a gate electrode connection hole of the PMOS transistor is connected to an element constituting the internal circuit.

  According to the present invention, in the semiconductor integrated device, in the electrostatic protection circuit, a source electrode connection hole and a drain electrode connection hole of the NMOS transistor are connected to the external connection terminal, and a source electrode connection hole and a drain of the PMOS transistor are connected. It is preferable that an electrode connection hole and a gate electrode connection hole are connected, and a gate electrode connection hole of the NMOS transistor is connected to an element constituting the internal circuit.

  In the semiconductor integrated device according to the present invention, it is preferable that the gate electrodes of the PMOS transistor and the NMOS transistor constituting the electrostatic protection circuit are made of polysilicon or a composite film of polysilicon and a refractory metal.

  According to the present invention, in the semiconductor integrated device, the gate electrode of the MOS transistor constituting the electrostatic protection circuit is formed of a strip-shaped conductive member arranged in parallel with the short side direction of the semiconductor chip as the semiconductor integrated device. Preferably it is.

  In the present invention, the semiconductor integrated device preferably constitutes a drive circuit for driving a display panel.

  The operation of the present invention will be described below.

  In the present invention, an electrostatic protection circuit is formed by using a diode formed between a drain and a substrate (well) of a MOSFET and between a source and a substrate (well), and polysilicon forming a gate electrode, or polysilicon and high. By constituting with a current limiting resistor formed of a laminated film of melting point metal, an electrostatic protection circuit that does not cause a snapback operation can be provided.

  As described above, according to the present invention, it is possible to provide an electrostatic protection circuit suitable for an output circuit of a display panel driving semiconductor integrated device in which a snapback operation does not occur. In addition, the size of the semiconductor integrated device in the short side direction can be reduced, so that more semiconductor integrated devices can be manufactured from the silicon wafer, and the manufacturing unit cost of the semiconductor integrated device can be reduced.

FIG. 1 is a diagram for explaining a semiconductor integrated device according to Embodiment 1 of the present invention, and shows an electrostatic discharge protection circuit on an output terminal side mounted on the semiconductor integrated device. FIG. 2 is a diagram showing a layout of the electrostatic discharge protection circuit on the output terminal side mounted on the semiconductor integrated device of the first embodiment. FIG. 3 is a diagram for explaining a semiconductor integrated device according to Embodiment 2 of the present invention, and shows an electrostatic discharge protection circuit on the input terminal side mounted on the semiconductor integrated device. FIG. 4 is a diagram for explaining a conventional semiconductor device, and shows an electrostatic discharge protection circuit on the output terminal side used in this semiconductor device. FIG. 5 is a diagram for explaining the characteristics of the medium breakdown voltage protection NMOS.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram for explaining a semiconductor integrated device according to Embodiment 1 of the present invention, and shows an electrostatic discharge protection circuit on an output terminal side mounted on the semiconductor integrated device.

  The semiconductor integrated device 100 of the first embodiment includes an internal circuit 5 that performs various signal processing, an external connection terminal 10 for outputting an internal signal generated by the internal circuit 5 to the outside of the semiconductor integrated device, The electrostatic protection circuit 1 is provided between the internal circuit 5 and the external connection terminal 10. Here, the internal circuit 5 includes an output buffer 5 a having a CMOS configuration that outputs an internal signal to the external connection terminal 10. The output buffer 5a has a PMOS transistor 6 and an NMOS transistor 7 connected in series between a VDD power supply terminal 11a and a VSS power supply terminal 11b. The source electrode of the PMOS transistor 6 is connected to the VDD power supply terminal 11a, the source electrode of the NMOS transistor 7 is connected to the VSS power supply terminal 11b, and the gate electrodes of the transistors 6 and 7 are connected in common.

  The electrostatic protection circuit 1 includes a PMOS transistor 2, an NMOS transistor 3, and a current limiting resistor 4. The output terminal (external connection terminal) 10 of the semiconductor integrated device 100 is connected to the source electrode and drain electrode of the PMOS transistor 2, and the source electrode, drain electrode, and gate electrode of the NMOS transistor 3 are connected, Further, one terminal of the current limiting resistor 4 is connected. The gate electrode of the PMOS transistor 2 is connected to the other terminal of the current limiting resistor 4. The other terminal of the current limiting resistor 4 is connected to the connection point of the serially connected transistors 6 and 7 constituting the output buffer 5a.

  The electrode formed in the substrate region (well) where the PMOS transistor 2 is formed is connected to the VDD power supply terminal 11a, and the electrode formed in the substrate region (well) where the NMOS transistor 3 is formed is the VSS power source. It is connected to the terminal 11b.

  FIG. 2 shows a layout of the semiconductor integrated device having the electrostatic protection circuit shown in FIG.

  As shown in FIG. 2, in the semiconductor integrated device (semiconductor chip) 100 of the first embodiment, the output buffer 5a in the internal circuit 5 is formed on the chip substrate 100a constituting the semiconductor integrated device along the short side direction. The PMOS transistor 6 and the NMOS transistor 7 constituting the, and the PMOS transistor 2 and the NMOS transistor 3 constituting the electrostatic protection circuit 1 are arranged.

  Here, the source electrode and the drain electrode of the PMOS transistor 2 are connected to the output terminal (external connection terminal) 10 of the semiconductor integrated device through the connection holes 2A and 2B, respectively, and the source electrode and the drain electrode of the NMOS transistor 3 are connected to each other. It is connected to an output terminal (external connection terminal) 10 of the semiconductor integrated device through holes 3A and 3B. The gate electrode of the transistor 2 is connected to the common drain electrode of the PMOS transistor 6 and the NMOS transistor 7 constituting the internal circuit 5 via the connection hole 2C, and the gate electrode of the NMOS transistor 3 is connected to the common hole electrode 5C via the connection hole 3C. It is connected to the output terminal 10 of the semiconductor integrated device.

  Here, the gate electrode of the transistor 2 is connected to the common drain electrode of the PMOS transistor 6 and the NMOS transistor 7 constituting the internal circuit 5 through the connection hole 2C, and the gate electrode of the NMOS transistor 3 passes through the connection hole 3C. However, instead of this, the gate electrode of the transistor 3 is common to the PMOS transistor 6 and the NMOS transistor 7 constituting the internal circuit 5 via the connection hole 3C. The gate electrode of the transistor 2 may be connected to the output terminal 10 of the semiconductor integrated device via the connection hole 2C.

  Further, the gate wiring formed along the short side direction above the PMOS transistor 2 and the NMOS transistor 3 functions as the current limiting resistor 4. The gate electrode functioning as the current limiting resistor 4 is composed of polysilicon or a laminated film of polysilicon and refractory metal.

  Next, the function and effect will be described.

  In such a semiconductor integrated device 100, the internal signal generated by the internal circuit 5 is converted into a signal level suitable for the signal level outside the semiconductor integrated device 100 by the output buffer 5 a, and the signal is output via the output terminal 10. And output to the outside of the semiconductor integrated device 100.

  In such a semiconductor integrated device 100, a positive surge current due to electrostatic discharge applied from the output terminal 10 is a parasitic formed by the source region and drain region of the PMOS transistor 2 and the substrate (well) from the output terminal 10. A forward current flows through the diode to the power supply terminal (VDD terminal) 11a. The negative surge current is diverted from the output terminal 10 to the power supply terminal (VSS terminal) 11b as a forward current through a parasitic diode formed by the source region and drain region of the NMOS transistor 3 and the substrate (well). Flowing.

  As described above, since the current limiting resistor 4 exists between the output terminal 10 and the internal circuit 5 for any polarity of the surge current, the surge current does not flow into the internal circuit 5 side, but depends on the polarity of the surge current. Then, it flows around the power supply terminal via each parasitic diode.

  Hereinafter, effects of the first embodiment having such a configuration will be described.

  For example, a semiconductor integrated device (semiconductor chip) for driving a display panel has several hundred to more than 1,000 output terminals, and the shape of the semiconductor integrated device is a very elongated rectangle. For example, while the dimension in the long side direction is 5 to 20 mm, the dimension in the short side direction is about 0.5 to 2 mm. The reason why the long side direction becomes long is that a large number of output terminals are arranged in the long side direction. In addition, since semiconductor integrated devices (semiconductor chips) are manufactured using circular silicon wafers, semiconductor integrated devices are manufactured for the purpose of reducing the unit price of semiconductor integrated devices by manufacturing as many semiconductor integrated devices as possible from silicon wafers having the same diameter. It is desirable to reduce the short-side dimension of the device.

  By laying out the electrostatic protection circuit as shown in FIG. 2, it is not necessary to arrange a current limiting resistor in a region different from the activation region (that is, the region in which the transistor is arranged) that constitutes the electrostatic protection circuit. It is possible to reduce the dimension in the side direction.

  Furthermore, it is desirable that the strip-like gate electrodes of the transistors 2 and 3 constituting the electrostatic protection circuit are arranged in parallel with the short side direction of the semiconductor integrated device as shown in FIG. This is because the arrangement direction of the source, gate, and drain constituting the transistor is perpendicular to the short side direction, and it is better to narrow the source, gate, and drain regions than the arrangement interval of the source, gate, and drain. This is because it can be easily realized. By laying out in this way, the size of the semiconductor integrated device can be reduced in the short side direction, more semiconductor integrated devices can be manufactured from a silicon wafer, and the manufacturing unit cost of the semiconductor integrated device can be reduced. Become.

  Furthermore, in the present embodiment, the electrostatic discharge protection circuit 1 is provided at the output terminal 10 and the current limiting resistor 4 is inserted between the output terminal 10 and the internal circuit 5. The polarity surge current does not flow into the internal circuit 5 side, but flows around the power supply terminal via each parasitic diode corresponding to the polarity of the surge current in the electrostatic protection circuit 1. As a result, surge current can be prevented from flowing into the semiconductor integrated device. As a result, an excessive voltage is not applied to the internal circuit of the semiconductor integrated device, and the internal circuit of the semiconductor integrated device is prevented from surge. It can be prevented from being destroyed by an electric current.

  That is, in the electrostatic protection circuit 1, parasitic diodes are formed between the source and drain regions of the PMOS and NMOS transistors and the substrate, and the gate electrodes of both MOS transistors form a current limiting resistor. Provides a static electricity protection circuit suitable for an output circuit of a semiconductor integrated device for driving a display panel in which a snapback operation does not occur.

  As described above, in this embodiment, in the electrostatic protection circuit 1 of the semiconductor integrated device 100, the gate electrode formed on the semiconductor substrate and connected to the external connection terminal 10 is formed on the PMOS transistor 2 and the semiconductor substrate. An NMOS transistor 3 having a gate electrode connected to a connection terminal 10, and a positive surge current is applied to a forward current via a pn junction between the source region and drain region of the PMOS transistor 2 and the semiconductor substrate. The negative surge current is released to the VSS power supply terminal 11b as a forward current via the pn junction between the source region and drain region of the NMOS transistor 3 and the semiconductor substrate. Therefore, the output of the semiconductor integrated device for driving the display panel without causing the snapback operation It is possible to obtain an electrostatic protection circuit suitable for road.

In the first embodiment, the gate electrode connection hole 3C connected to the output terminal 10 of the semiconductor integrated device and the gate electrode connection hole 2C connected to the transistor constituting the internal circuit 5 are interchanged, that is, the PMOS. Even if the gate electrode connection hole 2C of the transistor 2 is connected to the output terminal 10 and the gate electrode connection hole 3C of the NMOS transistor is connected to the transistor constituting the internal circuit, the same effect can be obtained.
(Embodiment 2)
FIG. 3 is a diagram for explaining a semiconductor integrated device according to Embodiment 2 of the present invention, and shows an electrostatic discharge protection circuit on the input terminal side mounted on the semiconductor integrated device.

  The semiconductor integrated device 101 according to the second embodiment includes an internal circuit 18 that performs various signal processing, and an external connection terminal (input terminal) 30 for supplying a signal from the outside of the semiconductor integrated device 101 to the internal circuit 18. And the electrostatic protection circuit 11 provided between the internal circuit 18 and the external connection terminal 30. Here, the internal circuit 18 includes an input buffer 18 a having a CMOS configuration that converts a signal from the external connection terminal 30 to a level suitable for the signal level in the internal circuit 18. The input buffer 18a has a PMOS transistor 16 and an NMOS transistor 17 connected in series between the VDD power supply terminal 31a and the VSS power supply terminal 31b. The source electrode of the PMOS transistor 16 is connected to the VDD power supply terminal 31a, the source electrode of the NMOS transistor 17 is connected to the VSS power supply terminal 31b, and the gate electrodes of the transistors 16 and 17 are connected in common.

  The electrostatic protection circuit 11 includes a PMOS transistor 12, an NMOS transistor 13, and a current limiting resistor 14. The source terminal and drain electrode of the PMOS transistor 12 are connected to the input terminal (external connection terminal) 30 of the semiconductor integrated device 101, and the source electrode, drain electrode, and gate electrode of the NMOS transistor 13 are connected. The one terminal of the current limiting resistor 14 is connected. The gate electrode of the PMOS transistor 12 is connected to the other terminal of the current limiting resistor 14. The other terminal of the current limiting resistor 14 is connected to a common gate electrode of the transistors 16 and 17 connected in series that constitute the input buffer 18a.

  Here, the gate electrode of the transistor 12 is connected to the common gate electrode of the PMOS transistor 16 and the NMOS transistor 17 constituting the internal circuit 18, and the gate electrode of the NMOS transistor 13 is connected to the input terminal 30 of the semiconductor integrated device. However, instead of this, the gate electrode of the transistor 13 is connected to the common gate electrode of the PMOS transistor 16 and the NMOS transistor 17 constituting the internal circuit 18, and the gate electrode of the transistor 12 is connected to the input of the semiconductor integrated device. It may be connected to the terminal 30.

  The electrode (first reference power supply terminal) formed in the substrate region (well) where the PMOS transistor 12 is formed is connected to the VDD power supply terminal 31a, and the substrate region (well) where the NMOS transistor 3 is formed. The electrode (second reference power supply terminal) formed on () is connected to the VSS power supply terminal 31b.

  The layout of the semiconductor integrated device 101 having the electrostatic protection circuit 11 according to the second embodiment forms the output buffer 5a in the layout of the semiconductor integrated device 100 having the electrostatic protection circuit 1 according to the first embodiment shown in FIG. The transistor is replaced with a transistor constituting the input buffer 18a, and the other terminal of the current limiting resistor is connected to a common gate electrode of the serially connected transistors 16 and 17 constituting the input buffer 18a.

  In the semiconductor integrated device 101 of the second embodiment, the signal from the input terminal 10 is converted to a signal level suitable for the signal level in the internal circuit 18 by the input buffer 18a in the first stage of the internal circuit, and the internal circuit 18 will be input.

  In such a semiconductor integrated device 101, a positive surge current due to electrostatic discharge applied from the input terminal 30 passes through a parasitic diode formed by the source region and drain region of the PMOS transistor 12 and the substrate (well). A forward current flows around the power supply terminal (VDD power supply terminal) 31a. The negative surge current is bypassed from the input terminal 30 to the power supply terminal (VSS power supply terminal) 31b as a forward current through a parasitic diode formed by the source region and drain region of the NMOS transistor 3 and the substrate (well). Then flow.

  As described above, in the second embodiment, the input terminal 30 is provided with the electrostatic protection circuit 11 and the current limiting resistor 14 is inserted between the input terminal 30 and the internal circuit 18. Without flowing into the circuit 18 side, it flows around the power supply terminal via each parasitic diode corresponding to the polarity of the surge current. As a result, surge current can be prevented from flowing into the semiconductor integrated device. As a result, an excessive voltage is not applied to the internal circuit of the semiconductor integrated device, and the internal circuit of the semiconductor integrated device is Can be prevented from being destroyed.

  In the semiconductor integrated device of the first embodiment, only the output terminal is shown, and in the semiconductor integrated device of the second embodiment, only the input terminal is shown. However, the semiconductor integrated device of any of the embodiments has an input terminal and an output terminal. Needless to say, therefore, as in the first and second embodiments, the electrostatic protection circuit is not provided only in either the output terminal or the input terminal, but both the output terminal and the input terminal are static. Needless to say, a protection circuit may be provided.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention provides an electrostatic protection circuit that prevents electrostatic breakdown in a semiconductor integrated device, for example, an electrostatic protection circuit that does not cause a snapback operation in the field of an electrostatic protection circuit of a semiconductor integrated device for driving a display panel. In addition, by making the direction of the strip-shaped gate electrode constituting the electrostatic protection circuit parallel to the short side direction of the semiconductor integrated device (semiconductor chip), it is possible to reduce the size of the semiconductor integrated device in the short side direction. Thus, more semiconductor integrated devices can be manufactured, and the manufacturing unit cost of the semiconductor integrated devices can be reduced.

1,11 Static protection circuit 2,6,12,16 PMOS transistor 2A PMOS transistor source electrode connection hole 2B PMOS transistor drain electrode connection hole 2C PMOS transistor gate electrode connection hole 3, 7, 13, 17 NMOS transistor 3A NMOS Transistor source electrode connection hole 3B NMOS transistor drain electrode connection hole 3C PMOS transistor gate electrode connection hole 4, 14 Current limiting resistor 5, 18 Internal circuit 5a Output buffer 10 Output terminal (external connection terminal)
11a, 31a VDD power supply terminal 11b, 31b VSS power supply terminal 18a Input buffer 30 Input terminal (external connection terminal)
100, 101 Semiconductor integrated device (semiconductor chip)

Claims (11)

A semiconductor integrated device having an internal circuit for performing signal processing and an external connection terminal for connecting the internal circuit to an external circuit,
An electrostatic protection circuit is connected between the internal circuit and the external connection terminal, and bypasses a surge voltage applied to the external connection terminal to a power line,
The electrostatic protection circuit is
A gate electrode formed on a semiconductor substrate and connected to the external connection terminal is connected to a first conductivity type MOS transistor,
A second conductivity type MOS transistor formed on the semiconductor substrate and having a gate electrode connected to the external connection terminal;
A positive surge current is released to the first power supply line as a forward current through a pn junction between the source region and drain region of the first conductivity type MOS transistor and the semiconductor substrate,
A negative surge current is configured to escape to the second power supply line as a forward current through a pn junction between the source region and drain region of the second conductivity type MOS transistor and the semiconductor substrate. Semiconductor integrated device. The semiconductor integrated device according to claim 1,
A semiconductor integrated device having a current limiting resistor connected between the internal circuit and the external connection terminal. The semiconductor integrated device according to claim 1,
The internal circuit has an output buffer that outputs an internal signal generated by the internal circuit to the external circuit;
The electrostatic protection circuit is a semiconductor integrated device provided between an output terminal as the external connection terminal and the output buffer. The semiconductor integrated device according to claim 1,
The internal circuit has an input buffer for supplying a signal from the external circuit to the internal circuit,
The electrostatic protection circuit is a semiconductor integrated device provided between an input terminal as the external connection terminal and the input buffer. The semiconductor integrated device according to claim 1,
The internal circuit is
An output buffer for outputting an internal signal generated by the internal circuit to the external circuit;
An input buffer for supplying a signal from the external circuit to the internal circuit;
As the electrostatic protection circuit,
An output side electrostatic protection circuit is provided between the output terminal as the external connection terminal and the output buffer, and an input side electrostatic protection circuit is provided between the input terminal as the external connection terminal and the input buffer. A semiconductor integrated device. The semiconductor integrated device according to claim 1,
The first conductivity type MOS transistor is a PMOS transistor;
The second conductivity type MOS transistor is an NMOS transistor;
The first power supply line is an electrode for supplying VDD power,
The semiconductor integrated device, wherein the second power supply line is an electrode for supplying VSS power. The semiconductor integrated device according to claim 6.
In the electrostatic protection circuit,
A source electrode connection hole and a drain electrode connection hole of the PMOS transistor are connected to the external connection terminal, and a source electrode connection hole, a drain electrode connection hole, and a gate electrode connection hole of the NMOS transistor are connected,
A semiconductor integrated device, wherein a gate electrode connection hole of the PMOS transistor is connected to an element constituting the internal circuit. The semiconductor integrated device according to claim 6.
In the electrostatic protection circuit,
A source electrode connection hole and a drain electrode connection hole of the NMOS transistor are connected to the external connection terminal, and a source electrode connection hole, a drain electrode connection hole, and a gate electrode connection hole of the PMOS transistor are connected,
A semiconductor integrated device, wherein a gate electrode connection hole of the NMOS transistor is connected to an element constituting the internal circuit. The semiconductor integrated device according to claim 7 or 8,
The gate electrode of the PMOS transistor and NMOS transistor which comprise the said electrostatic protection circuit is a semiconductor integrated device comprised by the composite film of polysilicon or a polysilicon and a refractory metal. The semiconductor integrated device according to claim 1,
A gate electrode of a MOS transistor constituting the electrostatic protection circuit is a semiconductor integrated device configured by a strip-like conductive member arranged in parallel with a short side direction of a semiconductor chip as the semiconductor integrated device.   The semiconductor integrated device according to claim 1, which constitutes a drive circuit for driving a display panel.

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