JP6624912B2 - Semiconductor device - Google Patents

Description

  The present invention provides an external connection terminal and an internal circuit area for protecting a semiconductor integrated circuit (hereinafter, referred to as IC) from destruction due to an electrostatic pulse generated by electrostatic discharge (hereinafter, referred to as ESD). Alternatively, the present invention relates to a semiconductor device having an ESD protection element formed between an external connection terminal and an output element.

  2. Description of the Related Art Conventionally, a semiconductor device typified by an IC includes an ESD protection element. The ESD protection element fixes the gate potential of an N-type MOS transistor to ground (hereinafter, referred to as VSS) and operates in a steady state. A so-called off transistor which is in an off state is known.

  As a countermeasure against ESD, it is important to capture as many proportions of electrostatic pulses as possible in the off-transistors and discharge them to VSS in order to prevent ESD damage to internal circuit elements or output elements such as drivers. Come. Therefore, in order to allow the current generated by the ESD electrostatic pulse to flow to VSS for the internal circuit elements and the output elements to be protected from ESD, the off-transistor has a reduced parasitic resistance as viewed from the IC VSS. It is important to do so.

  However, for example, when the IC size increases, the effect of the parasitic resistance of the source of the off-transistor becomes evident because the distance from VSS to the off-transistor becomes longer, and the off-transistor cannot exhibit sufficient capability. The electrostatic pulse to be captured is propagated to the internal circuit element or the output element, which may cause IC breakdown due to ESD.

  As an example of a measure for solving this problem, as described in the following Patent Document, the magnitude of the parasitic resistance is determined by the parasitic resistance from the external connection terminal to the ESD protection element and the parasitic resistance from the ESD protection element to the internal circuit element. There has also been proposed a device configuration characterized by incorporating as many electrostatic pulses as possible into the ESD protection element.

  2. Description of the Related Art Conventionally, power management ICs typified by a voltage detector or a voltage regulator have been developed with a focus on high drive capability and high added value. As a device for high driving capability, for example, the parasitic resistance has been reduced by arranging the output element near VSS. In order to devise high added value, for example, an original function has been added by forming an internal circuit by a conventional CMOS process.

  However, in the above-described high driving capability, as the parasitic resistance of the output element is reduced as compared with the off-transistor, the electrostatic pulse cannot be sufficiently captured by the off-transistor and propagates to the output element. It is feared that the IC will be destroyed.

  In addition, in the high added value described later, since the IC size has increased, the external connection terminal has become farther from the VSS of the IC, and the parasitic resistance of the source of the off-transistor has become apparent. There is a concern that the off-transistor will not be able to capture enough and will propagate to internal circuit elements, leading to IC destruction.

JP 2009-49331 A

  In view of the above, an object of the present invention is to provide a semiconductor device having an off-transistor with reduced source parasitic resistance.

  The present invention takes the following means in order to solve the above problems. That is, in a semiconductor device typified by an IC having an off-transistor, in order to reduce the parasitic resistance of the source of the off-transistor, an internal wiring connected to the source of the off-transistor and having a potential of VSS is provided around the IC. A semiconductor device is characterized in that the semiconductor device is connected in parallel with the arranged seal ring wiring.

  According to the present invention, in a semiconductor device including an off-transistor, by reducing the parasitic resistance of the source of the off-transistor, the off-transistor is quickly operated, and an electrostatic puls generated by ESD to an output element or an internal circuit element is reduced. It is possible to suppress propagation and improve resistance to ESD.

FIG. 3 is a schematic circuit diagram illustrating an external connection terminal, an ESD protection element, and an output element of the semiconductor device according to the embodiment of the present invention. FIG. 2 is a schematic layout diagram for explaining features of the present invention. 1 is an example of a semiconductor device capable of implementing the present invention.

Embodiments for implementing the present invention will be described with reference to the drawings.
FIG. 1 is a schematic circuit diagram showing an external connection terminal, an ESD protection element, and an output element of a semiconductor device according to an embodiment of the present invention. The first external connection terminal 1 is, for example, a terminal for output. The second external connection terminal 2 has a lower power supply voltage and is normally connected to the ground potential VSS. One of the elements connected between the first external connection terminal 1 and the second external connection terminal 2 is an off transistor 5 which is an ESD protection element. Further, an output element 6 is connected in parallel with the off transistor 5. That is, the output of the output element is connected to the first external connection terminal 1.

  The parasitic resistance of the source of the off-transistor 5 is a resistance parasitically included in the first internal wiring from the source of the off-transistor 5 to the second external connection terminal 2 and is represented by reference numeral 3 in the drawing. Hereinafter, the source parasitic resistance 3 of the off-transistor), and the parasitic resistance of the source of the output element 6 is a resistance parasitically included in the second internal wiring from the source of the output element 6 to the source of the off-transistor 5. , 4 in the figure. In the following, the source parasitic resistance 4 of the output element is used.

  The present invention is characterized in that the source parasitic resistance 3 of the off-transistor is lower than the source parasitic resistance 4 of the output element, and an embodiment for further explaining this will be described with reference to FIG.

FIG. 2 shows a part of the IC layout and shows the shape of the wiring. The seal ring wiring 7 and the internal wiring 8 installed on the outer periphery of the IC are illustrated. The internal wiring 8 is provided from the second external connection terminal 2 to the off-transistor 5, and the internal wiring 8 is electrically connected to the seal ring wiring 7 and the connection wiring 9. The parallel connection makes it possible to reduce the source parasitic resistance 3 of the off transistor.
In this case, the potential of the seal ring wiring 7 is connected to a second external connection terminal connected to a lower potential than the first external connection terminal, and is, for example, the ground potential VSS.

  The wiring of the seal ring wiring 7 is generally set on the outer periphery of the above-mentioned IC. It is connected to a second external connection terminal, and is, for example, a ground potential VSS. It is possible to arrange around the entire outer periphery of the IC without interruption. In addition, although there is a portion where one place is interrupted and is not continuous, it can be arranged substantially around. This is because the entirety of the seal ring wiring 7 is preferably at the same potential.

  FIG. 3 is an example of a semiconductor device capable of implementing the present invention. As shown in FIG. 3, in general, the seal ring wiring 7, the second external connection terminal 2, and the off-transistor 5 are often arranged along the outer periphery of the semiconductor device 20 which is a chip-shaped IC. It is not difficult to connect the internal wiring 8 connecting the two external connection terminals 2 and the off-transistor 5 in parallel with the seal ring wiring 7.

  On the other hand, the wiring from the source of the output element 6 to the source of the off-transistor 5 has only one layer, and the parasitic resistance can be relatively increased by further reducing the width. Furthermore, by arranging the output element 6 along the internal wiring 8 extending from the second external connection terminal 2 so as to be farther than the off-transistor 5, it is easy to relatively increase the parasitic resistance. Become.

  Further, when a multilayer wiring is used, the internal wiring 8 in FIG. 2 may have a laminated structure of the lowermost wiring and the uppermost wiring. In this case, a plurality of intermediate layer wirings may be further included between the lowermost wiring and the uppermost wiring, and may be electrically connected via the through holes 10 (also called vias). In the stacked structure, the width of the uppermost layer wiring may be the same as or different from that of the lowermost layer wiring. This makes it possible to make the source parasitic resistance 3 of the off-transistor lower than the source parasitic resistance 4 of the output element.

  Further, the above-described laminated structure including a plurality of wirings has a through hole 10 for electrically connecting the plurality of wirings. It may be arranged.

  The internal wiring 8 is electrically connected to the seal ring wiring 7 by a connection wiring 9, and the connection wiring 9 is electrically connected to the lowermost wiring, the uppermost wiring, or the wiring of other intermediate layers. It is possible. Further, in the connection between the seal ring wiring 7 and the internal wiring 8, a plurality of connection wirings 9 can be arranged intermittently in parallel as shown in FIG. is there.

  Although the output element 6 has been described as an example of an element located inside the IC rather than the off-transistor 5, the present invention can be similarly implemented even if the output element 6 is a general internal circuit. it is obvious.

1 first external connection terminal 1
2 Second external connection terminal 2
3 Source parasitic resistance of off transistor 4 Source parasitic resistance of output element 5 Off transistor 6 Output element 7 Seal ring wiring 8 Internal wiring 9 Connection wiring 10 Through hole 20 Semiconductor device

Claims (9)

A first external connection terminal;
A second external connection terminal connected to a lower potential than the first external connection terminal;
An off-transistor and an output element which are ESD protection elements disposed in parallel between the first external connection terminal and the second external connection terminal;
A seal ring wiring connected to the second external connection terminal;
Consisting of
Said second external connection terminal and said off first internal wiring connecting the source of the transistor and said seal ring line is connected in parallel by connecting lines, a parasitic resistance before Symbol first internal wiring off A semiconductor device, wherein a source parasitic resistance of a transistor is smaller than a source parasitic resistance of an output element which is a parasitic resistance of a second internal wiring connecting a source of the off transistor and a source of the output element.   2. The semiconductor device according to claim 1, wherein the first internal wiring has a stacked structure including a lowermost wiring and an uppermost wiring.   3. The semiconductor device according to claim 2, wherein the first internal wiring has a stacked structure including an intermediate wiring layer between a lowermost wiring and an uppermost wiring.   4. The semiconductor device according to claim 2, wherein wirings included in the stacked structure are electrically connected through through holes. 5.   3. The semiconductor device according to claim 2, wherein the connection wiring is formed of the lowermost wiring or the uppermost wiring.   4. The semiconductor device according to claim 3, wherein the connection wiring is formed of the lowermost wiring, the uppermost wiring, or the intermediate wiring layer. The plurality of connection wirings that connect the seal ring wiring and the first internal wiring are intermittently arranged in parallel, or are continuously arranged one by one on a plane. 7. The semiconductor device according to 6.   2. The semiconductor device according to claim 1, wherein the seal ring wiring is installed around an IC and continuously circulates.   2. The semiconductor device according to claim 1, wherein the seal ring wiring is provided around an outer periphery of the IC, and circulates except for one portion that is not continuous.

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