WO2007135694A1 - Dispositif de puissance à trois bornes et à vitesse de commutation élevée et procédé de fabrication - Google Patents

Dispositif de puissance à trois bornes et à vitesse de commutation élevée et procédé de fabrication Download PDF

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Publication number
WO2007135694A1
WO2007135694A1 PCT/IT2006/000372 IT2006000372W WO2007135694A1 WO 2007135694 A1 WO2007135694 A1 WO 2007135694A1 IT 2006000372 W IT2006000372 W IT 2006000372W WO 2007135694 A1 WO2007135694 A1 WO 2007135694A1
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WO
WIPO (PCT)
Prior art keywords
region
terminal
current
conductivity
type
Prior art date
Application number
PCT/IT2006/000372
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English (en)
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WO2007135694A8 (fr
Inventor
Cesare Ronsisvalle
Vincenzo Enea
Original Assignee
Stmicroelectronics S.R.L.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stmicroelectronics S.R.L. filed Critical Stmicroelectronics S.R.L.
Priority to CN2006800553395A priority Critical patent/CN101484996B/zh
Priority to US12/301,448 priority patent/US7982528B2/en
Priority to PCT/IT2006/000372 priority patent/WO2007135694A1/fr
Publication of WO2007135694A1 publication Critical patent/WO2007135694A1/fr
Publication of WO2007135694A8 publication Critical patent/WO2007135694A8/fr
Priority to US13/017,982 priority patent/US8420454B2/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/7404—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device
    • H01L29/742—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device the device being a field effect transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744—Gate-turn-off devices
    • H01L29/745—Gate-turn-off devices with turn-off by field effect
    • H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure

Definitions

  • the present invention relates to a three-terminal power device, and in particular to a power device that can be used as high-voltage actuator.
  • IGBTs Insulated-Gate Bipolar Transistors
  • MCTs MOS-Controlled Thyristors
  • ESTs emitter Switched Thyristors
  • the ones that have proven particular advantageous, for example because they enable a high blocking voltage (which is the maximum reverse voltage that the device can withstand without undergoing breakdown) are those based upon thyristors, which have a reduced forward voltage drop during operation, and driven as MOSFETs, i.e., with a control voltage applied to an insulated gate. Belonging to said category are MCTs and ESTs, which, however, have a somewhat modest reverse-bias safe-operating area (RBSOA) and long turn-off times.
  • RSOA reverse-bias safe-operating area
  • said power device designated by 1 in Figure 1
  • said power device comprises a thyristor 2 and a MOSFET 3 connected in series between two current- conduction terminals 4, 5.
  • the power device 1 also has a driving terminal 6, which is connected to an insulated-gate electrode of the MOSFET 3 and receives a voltage for turning on or off the device, and a further terminal 7 connected to the thyristor 2, for fast extraction of charges during the turn-off of the device. In this way, upon turn-off, no current tails occur, and turn-off is very rapid.
  • the power device does not have any parasitic components and so has a large RBSOA.
  • the power device 1 has, however, the drawback of not being of a standard type, in so far as it has four terminals (two control terminals and two current-conduction terminals) , unlike the majority of power actuators, which have only three terminals (one control terminal and two current-conduction terminals) .
  • the aim of the present invention is consequently to provide a power device that will enable the above drawbacks to be overcome and that will constitute a further improvement of power devices of a known type.
  • FIG. 1 shows a circuit diagram of a power device of a known type
  • FIG. 2 shows a circuit diagram of a power device according to an aspect of the present invention
  • FIG. 3 shows a cross section through an elementary structure of the power device of Figure 2;
  • Figures 4-8 show cross sections through a wafer of semiconductor material, in successive manufacturing steps of the power device of Figure 3;
  • FIG. 9 shows a cross section through an end portion of the power device of Figure 2, integrating a Zener diode thereof;
  • FIG. 10 and 11 show equivalent electrical circuit diagrams of the power device of Figure 2 in two different operating conditions, respectively a turn-on and a turn-off condition.
  • a power device 10 As shown in the equivalent electrical diagram of Figure 2, a power device 10 according to an aspect of the present invention has three terminals, and in particular a first current-conduction terminal A (anode) , a second current- conduction terminal K (cathode) , and a control terminal G
  • the power device 10 comprises a thyristor 12 (in particular, a silicon controlled rectifier - SCR) , and a first insulated- gate switch device 14 (in particular a MOS transistor) , connected in series between the first and second current- conduction terminals A, K.
  • the thyristor 12 has its anode connected to the first current-conduction terminal A, its cathode connected to a first internal node 15, and its base connected to a second internal node 16.
  • the first insulated-gate switch device 14 is connected between the first internal node 15 and the second current-conduction terminal K, and has its gate terminal connected to the control terminal G of the power device 10.
  • the power device 10 further comprises: a second insulated-gate switch device 18 (in particular a high-voltage IGBT) , which is connected between the first current-conduction terminal A and the second internal node 16 and has its gate terminal which is also connected to the control terminal G, and hence is connected to the gate terminal of the first insulated-gate switch device 14; and a Zener diode 19, which is connected between the second internal node 16 and the second current- conduction terminal K and in particular has its anode connected to the second current-conduction terminal and its cathode connected to the second internal node 16.
  • a second insulated-gate switch device 18 in particular a high-voltage IGBT
  • Figure 3 shows a cross section of an elementary structure of the power device 10, provided as monolithic structure integrated in a single body of semiconductor material 20.
  • the power device 10 can comprise in general a plurality of elementary structures arranged alongside one another, extending parallel to one another for example in a horizontal direction orthogonal to the vertical section of Figure 3, and each elementary structure can comprise one or more elementary cells.
  • the elementary structure comprises one elementary cell.
  • the body of semiconductor material 20 has a bottom surface 20a and a top surface 20b and comprises: a substrate 22, of a P + type; a buffer layer 23, of an N + type, which is arranged on the substrate 22 and has the function of increasing, in a per-se known manner, the breakdown voltage of the device; a first base region, referred to hereinafter as drift region 24, of an N " type, arranged on the buffer layer 23; a second base region, referred to hereinafter as base region 26, of a P type, housed within the drift region 24; a cathode region 27, of an N type, arranged on the base region 26; and an epitaxial region 28, of an N " type.
  • the epitaxial region 28 houses: first well regions 30, of a P + type, set partially in contact with the base region 26; second well regions 32, of an N + type, set in contact with the cathode region 27 and arranged beside and internally to the first well regions 30; first body regions 33, of a P type, housing first source regions 34, of an N + type, and arranged internally to the second well regions 32; and second body regions 35, of a P type, housing second source regions 36, of an N + type, and arranged externally to, and in contact with, the first well regions 30.
  • the bottom surface 20a of the power device 1, defined by the substrate 22, is covered by a metal layer 38 connected to the first current-conduction terminal A, accessible from outside the power device 10.
  • the drift region 24 is formed by a layer not accessible from outside, grown epitaxially, as explained in greater detail hereinafter, the characteristics (in terms of thickness and resistivity) of which depend upon the voltage class of the power device 10.
  • the base region 26 is a buried region, connected to the top surface 20b via the first well regions 30, which extend through the epitaxial region 28 between the top surface 20b and the base region 26.
  • the cathode region 27 is a buried region, connected to the top surface 20b via the second well regions 32, which extend through the epitaxial region 28 between the top surface 20b and the cathode region 27, and is delimited laterally by the first well regions 30, without necessarily being contiguous thereto.
  • the epitaxial region 28 has preferably the same resistivity as the drift region 24, - Q -
  • the first body regions 33 are housed within the epitaxial region 28 and are delimited laterally by the second well regions 32.
  • the first body regions 33 house two first source regions 34, similarly to what is known in the technology of vertical- conduction MOSFET power devices.
  • the presence of the second well regions 32 is advantageous for inhibiting the lateral parasitic transistors that could be formed between the first well regions 30, the epitaxial region 28 and the first body regions 33.
  • the second body regions 35 are housed within the epitaxial region 28 laterally in contact with the first well regions 30. In the example illustrated, the second body regions 35 each house a second source region 36.
  • the power device 10 comprises first insulated-gate regions 39, including in a known way an electrode, for example of polycrystalline silicon, surrounded by a dielectric layer, for example of silicon oxide.
  • the respective electrodes of the first insulated-gate regions 39 are connected to one another and to the control terminal G of the power device 10 (as shown schematically) , accessible from outside.
  • two first gate regions 39 are present adjacent to one another, extending, in a per-se known manner, above the portions of the first body regions 33 set between the first source regions 34 and the epitaxial region 28, and also partially above the epitaxial region 28 and the first source regions 34.
  • the power device 10 comprises second insulated-gate regions 40, the electrodes of which are also connected to one another and to the control terminal G of the power device 10.
  • two second insulated-gate regions 40 are present, extending, in a per-se known manner, above the portions of the second body regions 35 set between the second source regions 36 and the epitaxial region 28, and also partially above the epitaxial region 28 and the second source regions 36.
  • the power device 10 further comprises: a cathode metallization 42 extending on the top surface 20b between the first insulated-gate regions 39, in contact with the first body- regions 33 and source regions 34, and connected to the second current-conduction terminal K of the power device 10, accessible from outside; and a floating metallization 44, which is also set on the top surface 20b between respective first and second insulated-gate regions 39, 40, in contact with the second body and source regions 35, 36 and with the first well regions 30, and connected to the second internal node 16 ( Figure 2) of the power device 10.
  • the floating metallization 44 consequently short-circuits the second source regions 36 and the first well regions 30 adjacent thereto.
  • the thyristor 12 is formed by the substrate 22 (anode) , the buffer layer 23 (which may not be present) and the drift region 24 (first base), the base region 26 (second base, base terminal accessible from outside) , and the cathode region 27 (cathode) .
  • MOS transistor is formed by the cathode region 27 (drain) , the epitaxial region 28 and the first body regions 33
  • the second insulated-gate switch device (IGBT) 18 is formed by the substrate 22 (collector) , the drift region 24, the epitaxial region 28 and the second body regions 35 (channel), the second source regions 36 (emitter) , and the second insulated-gate regions 40 (gate) .
  • the Zener diode 19 (not shown in the cross section of Figure 3) can be integrated in the body of semiconductor material 20 using any known technique, for example in the way which will be described in detail hereinafter.
  • the junction of the Zener diode 19 can be provided by the layers and regions already formed for obtaining the various components described, with an appropriate layout of the power device.
  • the power device 10 is manufactured using traditional manufacturing techniques of silicon devices, for example, in the way described hereinafter with reference to Figures 4 to 9.
  • the buffer layer 23 and then the drift region 24 are grown epitaxially on the substrate 22; the buffer layer 23 has a reduced thickness (for example, 5-20 ⁇ m) and a low resistivity (for example, 1-5 ⁇ 'cm), and the drift region 24 has a larger thickness and higher resistivity
  • the epitaxial growth can be performed in a single step, or alternatively, through successive growth steps.
  • the cathode region 27 has a smaller width than the base region 26, to enable formation of the first well regions 30 laterally to iO the cathode region 27.
  • a further epitaxial growth is then carried out to form the epitaxial layer 28 (Figure 6) .
  • the epitaxial layer 28, of an N " type has a resistivity similar to that of the drift region ⁇ 5 24, but a smaller thickness (approximately 5 ⁇ m) .
  • the further epitaxial growth leads to an increase in the thickness of the cathode region 27, which thus extends in part within the epitaxial layer 28.
  • the process is then completed by providing the body and source regions of the first and second insulated-gate switch devices 14, 18, using standard process steps for manufacturing of vertical-flow DMOS structures.
  • the respective body .5 and source regions, and the respective gate regions and contacts, are formed simultaneously with the same process steps .
  • FIG. 9 shows a dedicated portion of the power device 10 (in
  • the Zener diode 19 is a lateral bipolar transistor with open base having as
  • SO emitter the first well region 30, of a P + type (connected to the second internal node 16 via the floating metallization 44), as base a first additional well 46 of an N + type (provided simultaneously with the first well regions 30) , and as collector a second additional well 48 of a P + type (provided
  • the Zener voltage of the Zener diode 19 is the BV ceo voltage of said lateral transistor.
  • the first insulated-gate switch device 14, set in series to the cathode of the thyristor 12, has a current- cutting function, i.e., it enables or blocks passage of current through the thyristor.
  • .5 switch device 18 set between the anode and the base of the thyristor 12, has, instead, the function of enabling turning- on thereof. Since the aforesaid switch devices are of the same type (with an N channel) and have the gate terminal in common, when the control voltage (designated by VG ATE ) exceeds a
  • the first current-conduction terminal A is set at a high positive voltage
  • the second current- conduction terminal K is set at a reference voltage (ground) BO so that the anode terminal A is at a higher voltage than the cathode K.
  • second source region 36 (second source region 36) . Since the second source region 36 is connected, via the floating metallization 44, to the first well region 30, the aforesaid current reaches the base region 26 of the thyristor 12. Said current, even though it is not particularly high, is in any case sufficient to trigger the thyristor 12 (in a way similar to traditional thyristors, the triggering current depends upon the common-base gain of the PNP and NPN transistors forming the thyristor) , which, in a known way, once it has been turned on, does not require a further modulation of the driving current.
  • Turn-on of the device causes a flow of current (designated by I 0n ) from the first current-conduction terminal A to the second current- conduction terminal K.
  • I 0n the voltage drop between said terminals is due substantially to the voltage drop across the thyristor 12 (the voltage drop across the first switch device 14 is in fact negligible in so far as it is a low-voltage MOSFET) , and is very low.
  • the Zener diode 19 (having a non-zero voltage across it, for example higher than 2 V) prevents a direct passage of current between the first current-conduction terminal A and the second current-conduction terminal K that would not enable turn-on of the thyristor 12.
  • VQ A T E When, instead, VQ A T E is lower than V TH , the first insulated-gate switch device 14 and the second insulated-gate switch device 18 switch off simultaneously, causing turn-off of the power device 10.
  • the first current-conduction terminal A (designated by Ioff) i since it cannot circulate in the two switches, is diverted into the base of the thyristor 12, and then, through the Zener diode 19, towards the second current-conduction terminal K. In this way, turn-off of the device is extremely fast (in the region of some hundreds of nanoseconds), without any current tail typical of bipolar-conduction actuator devices of a known type.
  • the Zener diode 19 hence enables a selective passage of current between the second internal node 16 and the second current-conduction terminal K, preventing passage of current during the on-phase of the thyristor 12, and enabling said passage of current only during the turn-off phase of the thyristor.
  • the structure of the device enables a high current density to be obtained, thanks to the presence of a thyristor, and a high switching speed, thanks to the cascode configuration between a thyristor and a MOSFET, with a fast removal by extraction of the base charges during turn-off.
  • the device has only three terminals (two current- conduction terminals and one control terminal) , and is consequently of a «standard» type, easily integrable in traditional technologies.
  • the power device does not have any parasitic components, so that it has both a large FBSOA (Forward-Bias Safe-Operating Area) and a large RBSOA.
  • FBSOA Forward-Bias Safe-Operating Area
  • the device is a power actuator that is particularly suitable for all those circuit applications in which a high reverse-bias blocking capacity (greater than 1 kV) and a high operating frequency (up to 100 kHz) are required.
  • the charge-extraction terminal in the turn-off phase (second internal node 16) to which the cathode of the Zener diode 19 is connected could be connected to another base region of the thyristor 12, in particular to the drift region 24.

Abstract

L'invention concerne un dispositif de puissance (10) possédant une première borne de conduction du courant (A) et une seconde borne de conduction du courant (K) ; une borne de commande (G) recevant, en utilisation, une tension de commande (VGATE) du dispositif de puissance (10) ; un dispositif de thyristor (12) ; un premier dispositif de commutation à grille isolée (14) connecté en série entre la première et la seconde borne de conduction. Le premier dispositif de commutation à grille isolée (14) est doté d'une borne de grille connectée à la borne de commande (G) ; le dispositif de thyristor (12) est doté d'une borne de base (16). Le dispositif de puissance (10) est, en outre, doté d'un second dispositif de commutation à grille isolée (18), connecté entre la première borne de conduction du courant (A) et la borne de base (16) du dispositif de thyristor (12), et présentant une borne de grille respective connectée à la borne de commande (G) ; il est également doté d'une diode de Zener (19), connectée entre la borne de base (16) du dispositif de thyristor (12) et la seconde borne de conduction du courant (K) de façon à permettre l'extraction de courant à partir de la borne de base (16) dans une condition de fonctionnement donnée.
PCT/IT2006/000372 2006-05-18 2006-05-18 Dispositif de puissance à trois bornes et à vitesse de commutation élevée et procédé de fabrication WO2007135694A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2006800553395A CN101484996B (zh) 2006-05-18 2006-05-18 具有高开关速度的三端功率器件以及制造工艺
US12/301,448 US7982528B2 (en) 2006-05-18 2006-05-18 Three-terminal power device with high switching speed and manufacturing process
PCT/IT2006/000372 WO2007135694A1 (fr) 2006-05-18 2006-05-18 Dispositif de puissance à trois bornes et à vitesse de commutation élevée et procédé de fabrication
US13/017,982 US8420454B2 (en) 2006-05-18 2011-01-31 Three-terminal power device with high switching speed and manufacturing process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IT2006/000372 WO2007135694A1 (fr) 2006-05-18 2006-05-18 Dispositif de puissance à trois bornes et à vitesse de commutation élevée et procédé de fabrication

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US12/301,448 A-371-Of-International US7982528B2 (en) 2006-05-18 2006-05-18 Three-terminal power device with high switching speed and manufacturing process
US13/017,982 Division US8420454B2 (en) 2006-05-18 2011-01-31 Three-terminal power device with high switching speed and manufacturing process

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Publication Number Publication Date
WO2007135694A1 true WO2007135694A1 (fr) 2007-11-29
WO2007135694A8 WO2007135694A8 (fr) 2008-12-31

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US (2) US7982528B2 (fr)
CN (1) CN101484996B (fr)
WO (1) WO2007135694A1 (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004102671A1 (fr) * 2003-05-19 2004-11-25 Stmicroelectronics S.R.L. Dispositif de puissance a vitesse de commutation elevee, et son procede de production
JP2008172165A (ja) * 2007-01-15 2008-07-24 Toshiba Corp 半導体装置
US7800128B2 (en) * 2008-06-12 2010-09-21 Infineon Technologies Ag Semiconductor ESD device and method of making same
JP2014060362A (ja) * 2012-09-19 2014-04-03 Toshiba Corp 半導体装置
US9006825B1 (en) * 2013-09-27 2015-04-14 Mediatek Inc. MOS device with isolated drain and method for fabricating the same
US10056372B2 (en) 2016-03-15 2018-08-21 Ideal Power Inc. Double-base-connected bipolar transistors with passive components preventing accidental turn-on
JP6937281B2 (ja) * 2018-09-14 2021-09-22 株式会社東芝 半導体装置
JP7068211B2 (ja) * 2019-02-15 2022-05-16 株式会社東芝 半導体装置
US11579645B2 (en) * 2019-06-21 2023-02-14 Wolfspeed, Inc. Device design for short-circuitry protection circuitry within transistors
CN113437143B (zh) * 2021-06-25 2023-05-02 电子科技大学 一种具有寄生二极管的三维mos栅控晶闸管及其制造方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980741A (en) * 1989-02-10 1990-12-25 General Electric Company MOS protection device
US5378903A (en) * 1993-03-23 1995-01-03 Fuji Electric Co., Ltd. Semiconductor device with low on-voltage and large controllable turn-off current
EP0731508A2 (fr) * 1995-03-09 1996-09-11 Hitachi, Ltd. Thyristor à contrÔle par MOS et méthode de commande
US5757034A (en) * 1994-07-28 1998-05-26 International Rectifier Corporation Emitter switched thyristor
US6118141A (en) * 1996-09-21 2000-09-12 Vishay Semicondcutor Gmbh Emitter-switched thyristor
US6313485B1 (en) * 1997-07-30 2001-11-06 Infineon Technologies Ag Gate-controlled thyristor
WO2002075892A1 (fr) * 2001-03-16 2002-09-26 Sarnoff Corporation Structures de protection contre les decharges electrostatiques a courant de maintien eleve pour eviter les declenchements parasites
US6933541B1 (en) * 1997-09-30 2005-08-23 Virginia Tech Intellectual Properties, Inc. Emitter turn-off thyristors (ETO)

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4199774A (en) * 1978-09-18 1980-04-22 The Board Of Trustees Of The Leland Stanford Junior University Monolithic semiconductor switching device
US5194927A (en) * 1990-08-16 1993-03-16 Fuji Electric Co., Ltd. Semiconductor device
US5381026A (en) * 1990-09-17 1995-01-10 Kabushiki Kaisha Toshiba Insulated-gate thyristor
JP3163677B2 (ja) * 1991-09-24 2001-05-08 富士電機株式会社 Ｍｉｓｆｅｔ制御型サイリスタを有する半導体装置
US6326648B1 (en) * 1999-12-20 2001-12-04 Stmicroelectronics S.A. Power switch with a controlled DI/DT
US6952335B2 (en) * 2002-03-22 2005-10-04 Virginia Tech Intellectual Properties, Inc. Solid-state DC circuit breaker
WO2004102671A1 (fr) 2003-05-19 2004-11-25 Stmicroelectronics S.R.L. Dispositif de puissance a vitesse de commutation elevee, et son procede de production
US7352233B1 (en) * 2004-06-14 2008-04-01 Otward Mueller Efficient thyristor-type power switches
EP1742272A1 (fr) 2005-07-08 2007-01-10 STMicroelectronics S.r.l. Dispositif de puissance ayant une structure cascode monolithique et une diode Zener intégrée

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980741A (en) * 1989-02-10 1990-12-25 General Electric Company MOS protection device
US5378903A (en) * 1993-03-23 1995-01-03 Fuji Electric Co., Ltd. Semiconductor device with low on-voltage and large controllable turn-off current
US5757034A (en) * 1994-07-28 1998-05-26 International Rectifier Corporation Emitter switched thyristor
EP0731508A2 (fr) * 1995-03-09 1996-09-11 Hitachi, Ltd. Thyristor à contrÔle par MOS et méthode de commande
US6118141A (en) * 1996-09-21 2000-09-12 Vishay Semicondcutor Gmbh Emitter-switched thyristor
US6313485B1 (en) * 1997-07-30 2001-11-06 Infineon Technologies Ag Gate-controlled thyristor
US6933541B1 (en) * 1997-09-30 2005-08-23 Virginia Tech Intellectual Properties, Inc. Emitter turn-off thyristors (ETO)
WO2002075892A1 (fr) * 2001-03-16 2002-09-26 Sarnoff Corporation Structures de protection contre les decharges electrostatiques a courant de maintien eleve pour eviter les declenchements parasites

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Publication number Publication date
CN101484996A (zh) 2009-07-15
US20110129967A1 (en) 2011-06-02
US20100001783A1 (en) 2010-01-07
US7982528B2 (en) 2011-07-19
CN101484996B (zh) 2011-05-18
WO2007135694A8 (fr) 2008-12-31
US8420454B2 (en) 2013-04-16

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