WO2007130789A3 - Method and apparatus for caching variable length instructions - Google Patents

Method and apparatus for caching variable length instructions Download PDF

Info

Publication number
WO2007130789A3
WO2007130789A3 PCT/US2007/066980 US2007066980W WO2007130789A3 WO 2007130789 A3 WO2007130789 A3 WO 2007130789A3 US 2007066980 W US2007066980 W US 2007066980W WO 2007130789 A3 WO2007130789 A3 WO 2007130789A3
Authority
WO
WIPO (PCT)
Prior art keywords
boundary position
cache
instruction
variable length
length instructions
Prior art date
Application number
PCT/US2007/066980
Other languages
French (fr)
Other versions
WO2007130789A2 (en
Inventor
Michael William Morrow
Original Assignee
Qualcomm Inc
Michael William Morrow
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc, Michael William Morrow filed Critical Qualcomm Inc
Priority to BRPI0711166-5A priority Critical patent/BRPI0711166A2/en
Priority to JP2009509929A priority patent/JP4755281B2/en
Priority to CA2649476A priority patent/CA2649476C/en
Priority to MX2008013776A priority patent/MX2008013776A/en
Priority to CN200780015669.6A priority patent/CN101432703B/en
Priority to EP07760923.8A priority patent/EP2089801B1/en
Publication of WO2007130789A2 publication Critical patent/WO2007130789A2/en
Publication of WO2007130789A3 publication Critical patent/WO2007130789A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)

Abstract

An instruction cache controller uses supplemental memory to store a redundant copy of cached instruction data corresponding to a cache boundary position, and thereby enables subsequent single cache access retrieval of an instruction that crosses that boundary position. In one or more embodiments, the cache controller duplicates instruction data for the post-boundary position in the supplemental memory, and multiplexes that copied data into cache data obtained from the pre-boundary position.
PCT/US2007/066980 2006-05-01 2007-04-19 Method and apparatus for caching variable length instructions WO2007130789A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
BRPI0711166-5A BRPI0711166A2 (en) 2006-05-01 2007-04-19 Method and equipment for temporarily storing variable length instructions
JP2009509929A JP4755281B2 (en) 2006-05-01 2007-04-19 Method and apparatus for caching variable length instructions
CA2649476A CA2649476C (en) 2006-05-01 2007-04-19 Method and apparatus for caching variable length instructions
MX2008013776A MX2008013776A (en) 2006-05-01 2007-04-19 Method and apparatus for caching variable length instructions.
CN200780015669.6A CN101432703B (en) 2006-05-01 2007-04-19 Method and apparatus for caching variable length instructions
EP07760923.8A EP2089801B1 (en) 2006-05-01 2007-04-19 Method and apparatus for caching variable length instructions

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/381,038 2006-05-01
US11/381,038 US7337272B2 (en) 2006-05-01 2006-05-01 Method and apparatus for caching variable length instructions

Publications (2)

Publication Number Publication Date
WO2007130789A2 WO2007130789A2 (en) 2007-11-15
WO2007130789A3 true WO2007130789A3 (en) 2008-02-21

Family

ID=38561189

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/066980 WO2007130789A2 (en) 2006-05-01 2007-04-19 Method and apparatus for caching variable length instructions

Country Status (10)

Country Link
US (1) US7337272B2 (en)
EP (1) EP2089801B1 (en)
JP (1) JP4755281B2 (en)
KR (1) KR101005180B1 (en)
CN (1) CN101432703B (en)
BR (1) BRPI0711166A2 (en)
CA (1) CA2649476C (en)
MX (1) MX2008013776A (en)
RU (1) RU2435204C2 (en)
WO (1) WO2007130789A2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7587580B2 (en) * 2005-02-03 2009-09-08 Qualcomm Corporated Power efficient instruction prefetch mechanism
US8261019B2 (en) * 2009-02-13 2012-09-04 Oracle America, Inc. Conveying critical data in a multiprocessor system
US8086801B2 (en) * 2009-04-08 2011-12-27 International Business Machines Corporation Loading data to vector renamed register from across multiple cache lines
CN101699391B (en) * 2009-09-30 2013-01-16 江南大学 Byte code buffer device for improving instruction fetch bandwidth of Java processor and using method thereof
US9460018B2 (en) * 2012-05-09 2016-10-04 Qualcomm Incorporated Method and apparatus for tracking extra data permissions in an instruction cache
US8819342B2 (en) * 2012-09-26 2014-08-26 Qualcomm Incorporated Methods and apparatus for managing page crossing instructions with different cacheability
US9495297B2 (en) 2014-07-22 2016-11-15 International Business Machines Corporation Cache line crossing load techniques for a caching system
US20160179540A1 (en) * 2014-12-23 2016-06-23 Mikhail Smelyanskiy Instruction and logic for hardware support for execution of calculations
US10133627B2 (en) 2015-12-11 2018-11-20 SK Hynix Inc. Memory device controller with mirrored command and operating method thereof
CN106227676B (en) * 2016-09-22 2019-04-19 大唐微电子技术有限公司 A kind of cache and the method and apparatus that data are read from cache
US11334491B1 (en) * 2020-11-18 2022-05-17 Centaur Technology, Inc. Side cache array for greater fetch bandwidth

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999047999A1 (en) * 1998-03-18 1999-09-23 Qualcomm Incorporated A digital signal processor
US6598148B1 (en) * 1989-08-03 2003-07-22 Patriot Scientific Corporation High performance microprocessor having variable speed system clock

Family Cites Families (11)

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Publication number Priority date Publication date Assignee Title
JPS53109443A (en) * 1977-03-07 1978-09-25 Hitachi Ltd Data processor
JPS6020255A (en) * 1983-07-15 1985-02-01 Fujitsu Ltd Buffer memory control system
JPS63245745A (en) * 1987-04-01 1988-10-12 Hitachi Ltd Buffer storage controller
US6006324A (en) * 1995-01-25 1999-12-21 Advanced Micro Devices, Inc. High performance superscalar alignment unit
US5802323A (en) * 1996-06-14 1998-09-01 Advanced Micro Devices, Inc. Transparent burst access to data having a portion residing in cache and a portion residing in memory
US5892962A (en) * 1996-11-12 1999-04-06 Lucent Technologies Inc. FPGA-based processor
US6804799B2 (en) * 2001-06-26 2004-10-12 Advanced Micro Devices, Inc. Using type bits to track storage of ECC and predecode bits in a level two cache
US7340495B2 (en) * 2001-10-29 2008-03-04 Intel Corporation Superior misaligned memory load and copy using merge hardware
JP3755661B2 (en) * 2002-08-20 2006-03-15 日本電気株式会社 Instruction cache control system and instruction cache control method in VLIW processor
US7243172B2 (en) * 2003-10-14 2007-07-10 Broadcom Corporation Fragment storage for data alignment and merger
US7568070B2 (en) * 2005-07-29 2009-07-28 Qualcomm Incorporated Instruction cache having fixed number of variable length instructions

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6598148B1 (en) * 1989-08-03 2003-07-22 Patriot Scientific Corporation High performance microprocessor having variable speed system clock
WO1999047999A1 (en) * 1998-03-18 1999-09-23 Qualcomm Incorporated A digital signal processor

Also Published As

Publication number Publication date
CA2649476C (en) 2012-02-07
KR20090018928A (en) 2009-02-24
CA2649476A1 (en) 2007-11-15
US7337272B2 (en) 2008-02-26
JP2009535743A (en) 2009-10-01
EP2089801A2 (en) 2009-08-19
CN101432703A (en) 2009-05-13
RU2435204C2 (en) 2011-11-27
RU2008147131A (en) 2010-06-10
WO2007130789A2 (en) 2007-11-15
MX2008013776A (en) 2008-11-14
KR101005180B1 (en) 2011-01-04
CN101432703B (en) 2016-09-14
EP2089801B1 (en) 2018-07-18
US20070255905A1 (en) 2007-11-01
JP4755281B2 (en) 2011-08-24
BRPI0711166A2 (en) 2011-08-23

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