IN2012DN02977A - - Google Patents

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Publication number
IN2012DN02977A
IN2012DN02977A IN2977DEN2012A IN2012DN02977A IN 2012DN02977 A IN2012DN02977 A IN 2012DN02977A IN 2977DEN2012 A IN2977DEN2012 A IN 2977DEN2012A IN 2012DN02977 A IN2012DN02977 A IN 2012DN02977A
Authority
IN
India
Prior art keywords
data stream
write permission
prefetch unit
given data
response
Prior art date
Application number
Inventor
Benjamin T Sander
Bharath Narasimha Swamy
Swamy Punyamurtula
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of IN2012DN02977A publication Critical patent/IN2012DN02977A/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6026—Prefetching based on access pattern detection, e.g. stride based prefetch

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

A system and method for efficient data prefetching. A data stream stored in lower-level memory comprises a contiguous block of data used in a computer program. A prefetch unit in a processor detects a data stream by identifying a sequence of storage accesses referencing a contiguous blocks of data in a monotonically increasing or decreasing manner. After a predetermined training period for a given data stream, the prefetch unit prefetches a portion of the given data stream from memory without write permission, in response to an access that does not request write permission. Also, after the training period, the prefetch unit prefetches a portion of the given data stream from lower-level memory with write permission, in response to determining there has been a prior access to the given data stream that requests write permission subsequent to a number of cache misses reaching a predetermined threshold.
IN2977DEN2012 2009-09-11 2010-09-09 IN2012DN02977A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/558,465 US8667225B2 (en) 2009-09-11 2009-09-11 Store aware prefetching for a datastream
PCT/US2010/048241 WO2011031837A1 (en) 2009-09-11 2010-09-09 Store aware prefetching for a datastream

Publications (1)

Publication Number Publication Date
IN2012DN02977A true IN2012DN02977A (en) 2015-07-31

Family

ID=43242176

Family Applications (1)

Application Number Title Priority Date Filing Date
IN2977DEN2012 IN2012DN02977A (en) 2009-09-11 2010-09-09

Country Status (7)

Country Link
US (1) US8667225B2 (en)
EP (1) EP2476060B1 (en)
JP (1) JP5615927B2 (en)
KR (1) KR101614867B1 (en)
CN (1) CN102640124B (en)
IN (1) IN2012DN02977A (en)
WO (1) WO2011031837A1 (en)

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US9098418B2 (en) * 2012-03-20 2015-08-04 Apple Inc. Coordinated prefetching based on training in hierarchically cached processors
US9311226B2 (en) 2012-04-20 2016-04-12 Memory Technologies Llc Managing operational state data of a memory module using host memory in association with state change
US9311251B2 (en) 2012-08-27 2016-04-12 Apple Inc. System cache with sticky allocation
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US9384136B2 (en) * 2013-04-12 2016-07-05 International Business Machines Corporation Modification of prefetch depth based on high latency event
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WO2015089488A1 (en) 2013-12-12 2015-06-18 Memory Technologies Llc Channel optimized storage modules
JP5936152B2 (en) 2014-05-17 2016-06-15 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ Memory access trace method
US9529727B2 (en) 2014-05-27 2016-12-27 Qualcomm Incorporated Reconfigurable fetch pipeline
US9817764B2 (en) * 2014-12-14 2017-11-14 Via Alliance Semiconductor Co., Ltd Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access type
EP3049915B1 (en) 2014-12-14 2020-02-12 VIA Alliance Semiconductor Co., Ltd. Prefetching with level of aggressiveness based on effectiveness by memory access type
US9971694B1 (en) 2015-06-24 2018-05-15 Apple Inc. Prefetch circuit for a processor with pointer optimization
US10324832B2 (en) * 2016-05-25 2019-06-18 Samsung Electronics Co., Ltd. Address based multi-stream storage device access
US10042749B2 (en) 2015-11-10 2018-08-07 International Business Machines Corporation Prefetch insensitive transactional memory
US10474576B2 (en) 2015-11-10 2019-11-12 International Business Machines Corporation Prefetch protocol for transactional memory
US10152419B2 (en) 2015-11-10 2018-12-11 International Business Machines Corporation Deferred response to a prefetch request
JP6734760B2 (en) 2015-11-10 2020-08-05 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ Prefetch insensitive transaction memory
US9904624B1 (en) 2016-04-07 2018-02-27 Apple Inc. Prefetch throttling in a multi-core system
US10180905B1 (en) 2016-04-07 2019-01-15 Apple Inc. Unified prefetch circuit for multi-level caches
US10169240B2 (en) * 2016-04-08 2019-01-01 Qualcomm Incorporated Reducing memory access bandwidth based on prediction of memory request size
US10649904B2 (en) 2016-12-12 2020-05-12 Samsung Electronics Co., Ltd. System and method for store streaming detection and handling
US10331567B1 (en) 2017-02-17 2019-06-25 Apple Inc. Prefetch circuit with global quality factor to reduce aggressiveness in low power modes
KR102429429B1 (en) 2017-03-24 2022-08-04 삼성전자주식회사 Electronic apparatus, and operating method for the same
CN109669880A (en) * 2017-10-13 2019-04-23 展讯通信（上海）有限公司 A kind of data prefetching method and device, microprocessor
CN109408412B (en) * 2018-10-24 2021-04-30 龙芯中科技术股份有限公司 Memory prefetch control method, device and equipment
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GB2593487B (en) * 2020-03-24 2022-05-04 Advanced Risc Mach Ltd Apparatus and method
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Also Published As

Publication number Publication date
EP2476060B1 (en) 2015-06-17
US20110066811A1 (en) 2011-03-17
WO2011031837A1 (en) 2011-03-17
KR101614867B1 (en) 2016-04-22
KR20120070584A (en) 2012-06-29
US8667225B2 (en) 2014-03-04
JP5615927B2 (en) 2014-10-29
EP2476060A1 (en) 2012-07-18
JP2013504815A (en) 2013-02-07
CN102640124B (en) 2015-11-25
CN102640124A (en) 2012-08-15

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