JP2015505091A5 - - Google Patents
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- JP2015505091A5 JP2015505091A5 JP2014546668A JP2014546668A JP2015505091A5 JP 2015505091 A5 JP2015505091 A5 JP 2015505091A5 JP 2014546668 A JP2014546668 A JP 2014546668A JP 2014546668 A JP2014546668 A JP 2014546668A JP 2015505091 A5 JP2015505091 A5 JP 2015505091A5
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- 230000036316 preload Effects 0.000 claims 2
- 230000002123 temporal effect Effects 0.000 claims 2
Claims (17)
コントローラを備え、
前記コントローラは、
コマンドメッセージを受信することであって、前記コマンドメッセージは、前記アクセラレイテッド処理デバイスによる処理の間にアクセスされる命令を含み、前記命令は、メモリの複数の部分のうち一部に関連するデータを含む、ことと、
前記コマンドメッセージが、前記メモリのうちアクセスされる前記一部を前記キャッシュにプレローディングするためのプレローディング命令を含むか否かを判別することによって前記コマンドメッセージを解釈することであって、前記コマンドメッセージが前記プレローディング命令を含むと判別された場合に、少なくとも前記メモリの前記一部を前記キャッシュにプレローディングし、前記コマンドメッセージが前記プレローディング命令を含んでいないと判別された場合に、前記コマンドメッセージの命令をキャッシュアクセス履歴と比較し、前記コマンドメッセージと前記キャッシュアクセス履歴との比較に基づいて、少なくとも前記メモリの前記一部を前記キャッシュにプレローディングすると判別する、ことと、
(i)ローカリティ参照情報および(ii)前記キャッシュのポリシー情報の少なくとも一方に基づいて、前記メモリのうちどの前記複数の部分を前記キャッシュにプレローディングするのか判別することと、
前記一部の内容に関連するデータを含むフェッチメッセージを作成することと、
前記フェッチメッセージを前記キャッシュに出力することと、
を行うように構成されている、システム。 A system including an accelerated processing device electrically connected to a cache comprising:
With a controller,
The controller is
Receiving a command message, wherein the command message includes instructions accessed during processing by the accelerated processing device, the instructions comprising data associated with a portion of the plurality of portions of memory. Including, and
Said command message, the method comprising interpreting the command message by determining whether including preloading instructions for pre-loading the part to be accessed out of the memory to the cache, the command When it is determined that a message includes the preloading instruction, at least the part of the memory is preloaded into the cache, and when it is determined that the command message does not include the preloading instruction, Comparing a command message instruction with a cache access history, and determining, based on a comparison of the command message and the cache access history, to preload at least the portion of the memory into the cache;
And that on the basis of at least one of (i) locality reference information and (ii) the policy information of the cache, to determine which of the plurality of portions of said memory for preloading the cache,
And to create a fetch message that contains the data related to the contents of the previous Symbol part,
And outputting the pre-Symbol fetch message to the cache,
Configured to do the system.
前記メモリのうちプレローディングされる前記一部がどのように前記キャッシュに記憶されるのか、及び、前記キャッシュのブロックが、(1)読み取りのみ、又は、(2)読み取りと書き込みの両方、の何れのときに書き込まれるのか、を決定し、
前記フェッチメッセージは、前記キャッシュに、前記ポリシー情報に基づいて前記データを前記メモリの一部からロードさせる、請求項1に記載のシステム。 The policy information is:
How the preloaded portion of the memory is stored in the cache and whether the block of the cache is (1) read only or (2) both read and write Determine when it will be written,
The fetch message to the cache, to load the data from a portion of the memory on the basis of the policy information system of claim 1.
コマンドメッセージを受信することであって、前記コマンドメッセージは、前記アクセラレイテッド処理デバイスによる処理の間にアクセスされる命令を含み、前記命令は、メモリの複数の部分のうち一部に関連するデータを含む、ことと、
前記コマンドメッセージが、前記メモリのうちアクセスされる前記一部を前記キャッシュにプレローディングするためのプレローディング命令を含むか否かを判別することによって前記コマンドメッセージを解釈することであって、前記コマンドメッセージが前記プレローディング命令を含むと判別された場合に、少なくとも前記メモリの前記一部を前記キャッシュにプレローディングし、前記コマンドメッセージが前記プレローディング命令を含んでいないと判別された場合に、前記コマンドメッセージの命令をキャッシュアクセス履歴と比較し、前記コマンドメッセージと前記キャッシュアクセス履歴との比較に基づいて、少なくとも前記メモリの前記一部を前記キャッシュにプレローディングすると判別する、ことと、
(i)特定されたローカリティ参照情報および(ii)特定された前記キャッシュのポリシー情報の少なくとも一方に基づいて、前記メモリのうちどの前記複数の部分を前記キャッシュにプレローディングするのか判別することと、
前記一部の内容に関連するデータを含むフェッチメッセージを作成することと、
前記フェッチメッセージを前記キャッシュに送信することと、
を含む、方法。 A computer-implemented method for preloading a cache, comprising:
The method comprising: receiving a command message, the command message may include instructions that are accessed during processing by the Accelerated processing device, the instruction is associated with some of the plurality of portions of the memory Including data,
Said command message, the method comprising interpreting the command message by determining whether including preloading instructions for pre-loading the part to be accessed out of the memory to the cache, the command When it is determined that a message includes the preloading instruction, at least the part of the memory is preloaded into the cache, and when it is determined that the command message does not include the preloading instruction, Comparing a command message instruction with a cache access history, and determining, based on a comparison of the command message and the cache access history, to preload at least the portion of the memory into the cache;
Determining which of the plurality of portions of the memory are preloaded into the cache based on at least one of (i) the specified locality reference information and (ii) the specified policy information of the cache;
Creating a fetch message that includes data related to the portion of content;
Sending the fetch message to the cache;
Including a method.
前記メモリのうちプレローディングされる前記一部がどのように前記キャッシュに記憶されるのか、及び、前記キャッシュのブロックが、(1)読み取りのみ、又は、(2)読み取りと書き込みの両方、の何れのときに書き込まれるのか、を決定し、
前記フェッチメッセージは、前記キャッシュに、前記メモリの一部からデータをロードさせる、請求項7に記載の方法。 The policy information is:
How the preloaded portion of the memory is stored in the cache and whether the block of the cache is (1) read only or (2) both read and write Determine when it will be written,
The fetch message to the cache, to load data from a portion of the memory The method of claim 7.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/324,432 | 2011-12-13 | ||
US13/324,432 US9239793B2 (en) | 2011-12-13 | 2011-12-13 | Mechanism for using a GPU controller for preloading caches |
PCT/IB2012/002938 WO2013108070A1 (en) | 2011-12-13 | 2012-12-12 | Mechanism for using a gpu controller for preloading caches |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2015505091A JP2015505091A (en) | 2015-02-16 |
JP2015505091A5 true JP2015505091A5 (en) | 2016-02-12 |
JP5973590B2 JP5973590B2 (en) | 2016-08-23 |
Family
ID=48573113
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014546668A Active JP5973590B2 (en) | 2011-12-13 | 2012-12-12 | Mechanism for using GPU controller for cache preloading |
Country Status (6)
Country | Link |
---|---|
US (1) | US9239793B2 (en) |
EP (1) | EP2791933B1 (en) |
JP (1) | JP5973590B2 (en) |
KR (1) | KR101868997B1 (en) |
CN (1) | CN104025185B (en) |
WO (1) | WO2013108070A1 (en) |
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CN110187835B (en) | 2019-05-24 | 2023-02-03 | 北京百度网讯科技有限公司 | Method, apparatus, device and storage medium for managing access requests |
CN111522771B (en) * | 2020-04-20 | 2023-08-15 | 北京百度网讯科技有限公司 | Fundus image processing method, terminal device and storage medium |
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-
2011
- 2011-12-13 US US13/324,432 patent/US9239793B2/en active Active
-
2012
- 2012-12-12 CN CN201280061641.7A patent/CN104025185B/en active Active
- 2012-12-12 EP EP12866001.6A patent/EP2791933B1/en active Active
- 2012-12-12 KR KR1020147016898A patent/KR101868997B1/en active IP Right Grant
- 2012-12-12 JP JP2014546668A patent/JP5973590B2/en active Active
- 2012-12-12 WO PCT/IB2012/002938 patent/WO2013108070A1/en unknown
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