IN2015DN03878A - - Google Patents
Info
- Publication number
- IN2015DN03878A IN2015DN03878A IN3878DEN2015A IN2015DN03878A IN 2015DN03878 A IN2015DN03878 A IN 2015DN03878A IN 3878DEN2015 A IN3878DEN2015 A IN 3878DEN2015A IN 2015DN03878 A IN2015DN03878 A IN 2015DN03878A
- Authority
- IN
- India
- Prior art keywords
- cache
- memory hierarchy
- prefetch
- processor
- lower level
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
A processor (102) transfers prefetch requests from their targeted cache (104) to another cache (105) in a memory hierarchy based on a fullness of a miss address buffer (MAB) (130) or based on confidence levels of the prefetch requests. Each cache in the memory hierarchy is assigned a number of slots at the MAB. In response to determining the fullness of the slots assigned to a cache is above a threshold when a prefetch request to the cache is received (404) the processor transfers the prefetch request to the next lower level cache in the memory hierarchy (410). In response the data targeted by the access request is prefetched to the next lower level cache in the memory hierarchy and is therefore available for subsequent provision to the cache. In addition the processor can transfer a prefetch request to lower level caches based on a confidence level of a prefetch request.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/669,502 US8909866B2 (en) | 2012-11-06 | 2012-11-06 | Prefetching to a cache based on buffer fullness |
| PCT/US2013/068433 WO2014074489A1 (en) | 2012-11-06 | 2013-11-05 | Prefetching to a cache based on buffer fullness |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IN2015DN03878A true IN2015DN03878A (en) | 2015-10-02 |
Family
ID=49627073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IN3878DEN2015 IN2015DN03878A (en) | 2012-11-06 | 2013-11-05 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US8909866B2 (en) |
| EP (1) | EP2917840B1 (en) |
| JP (1) | JP6105742B2 (en) |
| KR (1) | KR101973731B1 (en) |
| CN (1) | CN104769560B (en) |
| IN (1) | IN2015DN03878A (en) |
| WO (1) | WO2014074489A1 (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9749414B2 (en) * | 2013-08-29 | 2017-08-29 | International Business Machines Corporation | Storing low retention priority data in a dispersed storage network |
| US9811467B2 (en) * | 2014-02-03 | 2017-11-07 | Cavium, Inc. | Method and an apparatus for pre-fetching and processing work for procesor cores in a network processor |
| US9959506B1 (en) * | 2014-06-17 | 2018-05-01 | Amazon Technologies, Inc. | Predictive content retrieval using device movements |
| US9558127B2 (en) * | 2014-09-09 | 2017-01-31 | Intel Corporation | Instruction and logic for a cache prefetcher and dataless fill buffer |
| US9934149B2 (en) | 2016-03-31 | 2018-04-03 | Qualcomm Incorporated | Prefetch mechanism for servicing demand miss |
| US10509732B2 (en) * | 2016-04-27 | 2019-12-17 | Advanced Micro Devices, Inc. | Selecting cache aging policy for prefetches based on cache test regions |
| US10073785B2 (en) * | 2016-06-13 | 2018-09-11 | Advanced Micro Devices, Inc. | Up/down prefetcher |
| US10353819B2 (en) * | 2016-06-24 | 2019-07-16 | Qualcomm Incorporated | Next line prefetchers employing initial high prefetch prediction confidence states for throttling next line prefetches in a processor-based system |
| CN106487711B (en) * | 2016-10-13 | 2020-02-21 | 福建星海通信科技有限公司 | Method and system for dynamic cache allocation |
| CN108446240A (en) * | 2016-12-12 | 2018-08-24 | 中国航空工业集团公司西安航空计算技术研究所 | Storage management circuit based on buffer unit ID |
| US10776043B2 (en) * | 2018-08-31 | 2020-09-15 | Arm Limited | Storage circuitry request tracking |
| CN112997162A (en) * | 2018-11-20 | 2021-06-18 | 华为技术有限公司 | Method and device for deleting index entry in memory |
| WO2021066687A1 (en) * | 2019-10-02 | 2021-04-08 | Telefonaktiebolaget Lm Ericsson (Publ) | Entities, system and methods performed therein for handling memory operations of an application in a computer environment |
| US20210182214A1 (en) * | 2019-12-17 | 2021-06-17 | Advanced Micro Devices, Inc. | Prefetch level demotion |
| JP2022107377A (en) * | 2021-01-08 | 2022-07-21 | 富士通株式会社 | Information processing device, compilation method, and compilation program |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6065110A (en) * | 1998-02-09 | 2000-05-16 | International Business Machines Corporation | Method and apparatus for loading an instruction buffer of a processor capable of out-of-order instruction issue |
| US6212603B1 (en) | 1998-04-09 | 2001-04-03 | Institute For The Development Of Emerging Architectures, L.L.C. | Processor with apparatus for tracking prefetch and demand fetch instructions serviced by cache memory |
| US6029294A (en) * | 1998-07-23 | 2000-02-29 | Saringer Research Inc. | Mechanism for generating wave motion |
| JP3512678B2 (en) * | 1999-05-27 | 2004-03-31 | 富士通株式会社 | Cache memory control device and computer system |
| US6571318B1 (en) | 2001-03-02 | 2003-05-27 | Advanced Micro Devices, Inc. | Stride based prefetcher with confidence counter and dynamic prefetch-ahead mechanism |
| US20040103251A1 (en) * | 2002-11-26 | 2004-05-27 | Mitchell Alsup | Microprocessor including a first level cache and a second level cache having different cache line sizes |
| US20060143401A1 (en) * | 2004-12-27 | 2006-06-29 | Jacob Doweck | Method and apparatus for prefetching based on cache fill buffer hits |
| US7840761B2 (en) * | 2005-04-01 | 2010-11-23 | Stmicroelectronics, Inc. | Apparatus and method for supporting execution of prefetch threads |
| EP1990731B1 (en) * | 2006-02-28 | 2015-05-27 | Fujitsu Limited | Processor having prefetch function |
| US7908236B2 (en) * | 2006-07-20 | 2011-03-15 | International Business Machines Corporation | Using multiple data structures to manage data in cache |
| US7484042B2 (en) * | 2006-08-18 | 2009-01-27 | International Business Machines Corporation | Data processing system and method for predictively selecting a scope of a prefetch operation |
| US8230177B2 (en) * | 2009-05-28 | 2012-07-24 | Oracle America, Inc. | Store prefetching via store queue lookahead |
| JP5444889B2 (en) * | 2009-06-30 | 2014-03-19 | 富士通株式会社 | Arithmetic processing device and control method of arithmetic processing device |
| CN101634970B (en) * | 2009-08-26 | 2011-09-07 | 成都市华为赛门铁克科技有限公司 | Method and device for adjusting pre-fetch length and storage system |
| US8856451B2 (en) | 2010-08-26 | 2014-10-07 | Advanced Micro Devices, Inc. | Method and apparatus for adapting aggressiveness of a pre-fetcher |
| US8880847B2 (en) * | 2010-09-28 | 2014-11-04 | Texas Instruments Incorporated | Multistream prefetch buffer |
-
2012
- 2012-11-06 US US13/669,502 patent/US8909866B2/en active Active
-
2013
- 2013-11-05 WO PCT/US2013/068433 patent/WO2014074489A1/en active Application Filing
- 2013-11-05 CN CN201380058101.8A patent/CN104769560B/en active Active
- 2013-11-05 EP EP13795065.5A patent/EP2917840B1/en active Active
- 2013-11-05 IN IN3878DEN2015 patent/IN2015DN03878A/en unknown
- 2013-11-05 KR KR1020157014676A patent/KR101973731B1/en active IP Right Grant
- 2013-11-05 JP JP2015541846A patent/JP6105742B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP6105742B2 (en) | 2017-03-29 |
| WO2014074489A1 (en) | 2014-05-15 |
| CN104769560B (en) | 2017-04-12 |
| EP2917840B1 (en) | 2018-12-26 |
| US20140129772A1 (en) | 2014-05-08 |
| EP2917840A1 (en) | 2015-09-16 |
| JP2016509272A (en) | 2016-03-24 |
| US8909866B2 (en) | 2014-12-09 |
| KR101973731B1 (en) | 2019-04-29 |
| KR20150082457A (en) | 2015-07-15 |
| CN104769560A (en) | 2015-07-08 |
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