JP4030314B2 - Arithmetic processing unit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an arithmetic processing unit that includes a cache memory and performs prefetch processing to conceal memory access latency, and more particularly, by performing prefetch processing based on runtime information. It is related with the arithmetic processing apparatus which aimed at improvement.
[0002]
[Prior art]
In the current computer system, an increase in memory access latency is a major cause of hindering an improvement in the performance of the entire system. A general computer system focuses on the temporal and spatial locality of memory access, and is equipped with a cache memory that can be accessed at high speed between the processor (register) and the main memory. The access performance is improved.
[0003]
However, when there is no data in the cache memory when a memory access occurs, that is, when a cache miss occurs, it is necessary to transfer the data from the main memory. At this time, a long time is required for data transfer (cache miss penalty). In the current arithmetic processing unit, access to the cache memory is about 1 to several tens of cycles, but the cache miss penalty reaches several tens of cycles. Accordingly, the program execution time is largely limited by the cache miss penalty. The gap between processor operating speed and memory access speed is increasing year by year, and the above problem will cause more serious damage to computer systems in the future.
[0004]
In order to solve this problem, in the prior art, a method called data prefetch (data prefetching, hereinafter simply referred to as prefetch) has been widely proposed and used. Data prefetching is a process in which data that is expected to be accessed in the future is transferred in advance to an upper layer (cache memory) of the memory. By appropriately performing data prefetching, the access delay time to the main memory is hidden, and the program is executed as if the data is always present in the cache.
[0005]
Many prefetch methods have been proposed so far, but can be broadly divided into the following two methods.
[0006]
(1) Software prefetch. In general, a compiler or the like statically analyzes a program behavior and inserts a prefetch instruction into the program. A compiler or the like may insert a prefetch instruction based on profile information obtained by executing a program.
[0007]
(2) Hardware prefetch. A hardware mechanism dedicated to prefetch is provided inside or outside the processor. Generally, dynamically (during program execution), this dedicated hardware recognizes the occurrence of a cache miss and performs prefetch processing based on a predetermined algorithm. The existing hardware prefetch method recognizes that a cache miss has occurred several times, and starts prefetching using this as a trigger.
[0008]
As an example of the above (1), in Japanese Patent Laid-Open No. 11-212802, the original program is converted into intermediate text, the converted intermediate text is optimized, the address for data prefetching is calculated, and the prefetch instruction is issued. A compilation technique of inserting has been proposed.
[0009]
As for (2) above, for example, when a certain cache block is accessed, it is predicted that the next cache block will be accessed in the near future, and prefetching is performed for that address. In addition, many other methods have been proposed, such as prefetching by stride prediction in which an address to be accessed next time is determined by adding a certain value. In addition, as actually used commercially, Pentium (registered trademark) 4 has a mechanism that always reads data 256 bytes ahead from the address that is actually accessed.
[0010]
[Problems to be solved by the invention]
Generally, when performing prefetch processing, it is necessary to pay attention to the following problems.
[0011]
(1) Cache pollution occurs. By performing the prefetch, the data stored in the cache memory is evicted. If prefetch processing is not performed, if there is data that would not have been evicted and hit the cache originally, prefetching may cause performance degradation.
[0012]
(2) Prefetched data is evicted before use by subsequent accesses. If the prefetch process is performed for a long time before the prefetched data is actually accessed, the prefetched data may be expelled by the preceding memory access before the actual access.
[0013]
(3) The bus bandwidth is wasted due to excessive prefetch processing. By performing prefetch processing more than necessary, the memory bus bandwidth is wasted, and conversely, performance degradation is caused.
[0014]
Regarding the above (1) and (2), it is necessary to appropriately determine the distance (prefetch distance) between the prefetch insertion position and the instruction that actually uses the prefetched data. As for the above (3), a prefetch instruction must be inserted only when it can be determined that prefetching is effective rather than prefetching all memory accesses in which a cache miss occurs.
[0015]
On the other hand, in the conventional prefetch method, the program behavior may change depending on the situation at the time of execution, or the system configuration may be changed (the configuration of the processor or the memory system may be changed). It is difficult to set the distance appropriately.
[0016]
First, in software prefetching, when an environment change as described above occurs, an operation such as recompiling a source program is required. Thus, it is not realistic to prepare an executable file for each system. In addition, it is not possible to cope with a program whose behavior changes depending on the input to the program.
[0017]
On the other hand, even in hardware prefetching, an effective prefetching distance cannot be maintained by simply performing prefetching when a load miss occurs. In addition, it is difficult to implement complicated processing related to a method for determining whether to perform hardware prefetching. In fact, the conventional hardware prefetch is generally simple, such as executing prefetch when a cache miss occurs several times, or continuing to prefetch the next block after the accessed block.
[0018]
The present invention has been made in view of the above-described problems, and an object of the present invention is to provide an arithmetic processing device having a cache memory by inserting a prefetch instruction into an instruction stream based on runtime information. Another object of the present invention is to provide an apparatus capable of efficiently performing prefetching while minimizing problems such as cache contamination associated with a conventional prefetch method.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, an operation is executed by dynamically inserting a prefetch instruction instructing to transfer data from the main memory to the cache memory in advance into the instruction sequence. A processing device, a prefetch target selecting means for selecting an instruction to be subjected to a prefetch process among instructions causing a cache miss, and a memory access at the time of executing an instruction which is a target of the prefetch process by the prefetch target selecting means Address predicting means for predicting an address; prefetch instruction insertion position determining means for determining an insertion position of a prefetch instruction corresponding to an instruction that has been subjected to prefetch processing by the prefetch target selecting means; and the address prediction Operate the memory access address predicted by the means A prefetch instruction with the de, the insertion position determined by the prefetch instruction insertion position determining means, the arithmetic processing apparatus is provided comprising a prefetch instruction insertion means for inserting.
[0020]
Also, according to the second aspect of the present invention, preferably, the prefetch target selecting means includes a counter for measuring the number of times a cache miss occurs for each instruction address, and the value of the counter exceeds a certain value. In this case, a handler that processes cache miss information is activated, and an instruction to be subjected to prefetch processing is selected by the handler.
[0021]
Also, according to the third aspect of the present invention, preferably, the prefetch instruction insertion position determining means includes a table that holds an instruction address and an execution completion time for an instruction sequence that has been executed in the past. The insertion position of the prefetch instruction in the instruction string is determined based on the information.
[0022]
According to the fourth aspect of the present invention, the prefetch target selection means, the prefetch instruction insertion position determination means, the address prediction means, and the prefetch instruction insertion means may be provided in a cache memory.
[0023]
According to the fifth aspect of the present invention, in the case of an arithmetic processing unit capable of controlling a plurality of execution instruction streams, the handler for processing the cache miss information is executed as an independent instruction stream independent of the main instruction stream. Is done.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
[0025]
FIG. 1 is a diagram for explaining the outline of the operation of an arithmetic processing unit that performs prefetch instruction insertion processing according to the present invention. FIG. 1 shows only the portion related to the present invention. The instruction fetch unit and the instruction decoder unit are combined into a part that controls the execution of the instruction, and this part is called a control unit. In the arithmetic processing device that is the subject of the present invention, an instruction address that designates the next instruction to be executed is specified from the control unit, and the instruction is read from the memory (or cache memory) in which the instruction sequence is stored, Input to the control unit. Thereafter, the instruction is executed in a single or a plurality of arithmetic units. The sequence of instructions read from the memory is referred to as an “instruction stream (instruction stream)” in the present invention.
[0026]
The control unit in FIG. 1 inserts a prefetch instruction at the designated instruction address. At runtime, the program itself is stored in the main memory and is not directly modified. In an example of a method for inserting and executing a prefetch instruction at a specified instruction address, an instruction fetch unit (included in the control unit in FIG. 1) compares the instruction address to be fetched with the instruction address to be inserted. If they match, the prefetch instruction is interrupted into the instruction stream acquired from the main memory, and then the arithmetic unit executes the prefetch instruction.
[0027]
In the arithmetic processing unit according to the present invention, an instruction address (load / store instruction, arithmetic instruction with memory access, etc.) where a cache miss occurs is detected. Various algorithms may be applied to determine whether to actually perform data prefetch for the detected instruction address. When prefetching is performed, a prefetch instruction insertion position (instruction address) corresponding to the cache miss penalty in the system is specified. Furthermore, various data address prediction methods that have already been proposed to date can be applied to data addresses to be prefetched. Thus, it is possible to perform dynamic and effective prefetching without recompiling the program and without depending on the runtime environment.
[0028]
FIG. 2 is a diagram showing a configuration example of an arithmetic processing apparatus according to the present invention. In the embodiment shown in FIG. 2, an instruction cache 12 and a data cache 14 are provided for the main memory 10. The instruction fetch unit 20 fetches an instruction from the instruction cache 12 based on the value of the program counter (PC) 24 (address where the instruction to be fetched is stored) and sends the instruction to the decoder 30. The instruction decoded by the decoder 30 is processed in the branch instruction processing unit 32, the arithmetic instruction processing unit 34 or the load / store instruction processing unit 36.
[0029]
Inside the instruction fetch unit 20 in this embodiment, a plurality of registers (prefetch instruction insertion address registers) 22a to 22d for specifying the insertion address of the prefetch instruction are provided. The instruction fetch unit 20 compares the value of the program counter (PC) 24 and the values of the prefetch instruction insertion address registers 22a to 22d in parallel in comparators (comparators) 26a to 26d at the time of instruction fetch. If they match, a prefetch instruction is inserted at a predetermined position in the instruction queue 28 for inputting an instruction to the decoder 30.
[0030]
When selecting an instruction to be subject to prefetch processing among instructions that cause a data cache miss, a sufficient effect can be obtained by prefetch processing by recording the instruction address where the cache miss has occurred and statistically processing it. It is desirable to be able to select an instruction address.
[0031]
In this embodiment, a counter that measures the occurrence of a cache miss is provided in order to efficiently obtain statistical data of an instruction address at which a cache miss occurs. That is, the event counter 42 in the register file 40 in FIG. 2 is the counter. When the event counter 42 counts the designated number of times, a handler designated beforehand is executed inside the arithmetic processing unit. By providing such a mechanism, it is possible to perform flexible processing of cache miss information by software while avoiding the overhead that the detection function is activated each time a cache miss occurs.
[0032]
The activated handler determines whether or not to perform prefetch processing based on a table that stores the number of times a cache miss has occurred for each instruction address as shown in FIG. This table is provided on the main memory.
[0033]
To determine the optimal prefetch distance, for example, assume the number of execution cycles per instruction (Cycle Per Instruction, CPI), and calculate an appropriate prefetch distance in consideration of the cache miss penalty in the target system configuration. can do.
[0034]
However, in this case, it is generally difficult to know the CPI of the target system (target program) at the time of execution, and it cannot necessarily be said that it reflects the execution status near the instruction to be prefetched.
[0035]
Therefore, it is preferable to provide the arithmetic processing unit with a table that holds an execution history of instructions that have been executed in the past for a fixed number of instructions. In this case, when inserting a prefetch instruction, it is possible to know an insertion address with higher accuracy than by assuming CPI by referring to this table. As a result, adverse effects due to prefetching can be minimized.
[0036]
The execution history table 50 shown in FIG. 2 is a table that holds an instruction execution history, and the above-described handler determines the insertion position of the prefetch instruction corresponding to the instruction to be prefetched in the instruction string. This is what you will refer to. A configuration example of the execution history table 50 is shown in FIG. As shown in this figure, each entry in the table includes an instruction address and a time (clock unit) when the execution instruction is completed. This table includes a plurality of entries, and can hold completion information about several tens of instructions before the instruction that has been recently executed.
[0037]
When inserting a prefetch instruction, the handler activated when a cache miss event occurs refers to the execution history table 50 to determine the insertion position and sets it to any of the prefetch instruction insertion address registers 22a to 22d. Note that this handler can access the registers 22a to 22d in the same manner as the general registers. In this manner, such a handler can accurately determine the position to insert the prefetch instruction by accessing the execution history table 50 when inserting the prefetch instruction. In this case, it is necessary to add an instruction for accessing the execution history table, or to memory map this table.
[0038]
The address prediction unit 60 in FIG. 2 is used to determine the memory address to be data prefetched, that is, the operand of the prefetch instruction. The above-described handler transmits an instruction address of an instruction (load instruction) to be prefetched to this unit in advance. Note that the address prediction unit 60 is implemented with a generally known address prediction technique. For example, techniques disclosed in Japanese Patent Laid-Open No. 4-206917, MH Lipasti, et al. “Value Locality and Load Value Prediction” in ASPLOS-VII, 1996, etc. can be used.
[0039]
An address prediction table is prepared inside the address prediction unit 60. Each entry of this table holds a load instruction address (index) and a memory address to be loaded last time and the last time. When a load instruction address is transmitted to this address prediction unit 60, this unit (1) compares the address in the address prediction table with the index, and (2) And the address accessed next time is predicted from the difference (stride) of the memory address of the previous time.
[0040]
Hereinafter, a sequence for inserting a prefetch instruction using an actually simple sample program will be exemplified. The sample program is shown in FIG. This program is obtained by cutting out only a portion for performing loop calculation processing within a specified range of an array from an entire program. Here, description is made using pseudo-instructions, not instructions of a specific architecture.
[0041]
In the program, a load instruction (ld) indicated by reference numeral 70 is a load instruction that causes many cache misses. This load instruction is to load the contents of the memory addressed with the value obtained by adding the value stored in the register r6 and the value stored in the register r7 into the register r1. The sequence is shown below.
[0042]
(1) During execution of a program, a cache miss occurs when a load instruction indicated by reference numeral 70 is executed. At this time, the event counter 42 (FIG. 2) is counted up. If the counter overflows, the handler is activated.
[0043]
(2) Based on the table shown in FIG. 3 described above, the activated handler determines whether a number of cache misses have occurred at this instruction address and the prefetch process should be performed.
[0044]
(3) When performing prefetch processing, the handler refers to the execution history table 50 (FIG. 4). In the case of this sample program, the contents of the execution history table 50 are as shown in FIG. FIG. 6 shows a corresponding instruction stream together with the execution history table 50. In this system, when the cache miss penalty is 0x60 (hexadecimal display) processor cycle, it can be seen from this table that prefetch instructions should be inserted before and after the load instruction two loops before.
[0045]
(4) The handler sets the instruction address (0x00010030) of the load instruction in one of the registers 22a to 22d for designating the prefetch instruction insertion address in the instruction fetch unit 20, and at the same time, the address prediction unit 60 Instructs generation of operand (memory address). In addition, it indicates how many loop destination predicted addresses it is desired to obtain (in this example, 2).
[0046]
(5) If the instruction address is present in the address prediction table in the unit, the address prediction unit 60 obtains the difference between the previous and previous memory addresses of the entry. In this example, as can be seen from the fact that 32 is added to the register r7 by the add instruction every time one loop is executed, the memory address difference is 32 bytes.
[0047]
(6) The address prediction unit 60 transmits the data ahead of 32 (bytes) × 2 (loop) to the instruction fetch unit 20 as a prefetch target memory address.
[0048]
Note that the cache miss penalty (0x60 cycles) in (3) is changed when the system configuration is changed. Thereafter, the instruction fetch unit 20 repeatedly inserts a prefetch instruction for the address when it reaches the execution before and after the load instruction again. At this time, the address prediction unit 60 generates a memory address to be prefetched each time.
[0049]
In the above-described embodiment, the prefetch instruction is inserted in the instruction fetch unit 20 (that is, the control unit in FIG. 1) in the arithmetic processing unit. However, the prefetch instruction can be inserted in the cache memory. Many arithmetic processing units are equipped with a dedicated cache memory (instruction cache) for storing instruction words or a shared cache memory for storing instruction words together with data. The cache memory device can be provided with the above-described prefetch instruction insertion device so that when the instruction acquisition request is issued from the control unit, the prefetch instruction inserted is returned.
[0050]
By providing the cache memory with the prefetch insertion function in this way, it becomes possible to add functions without any modification to the inside of the arithmetic processing unit (control unit, arithmetic unit).
[0051]
By the way, when the control unit can only control a single instruction stream (such as a superscalar processor), when executing a software handler, the execution of the currently executing program is temporarily suspended and the execution context is saved. After that, the execution of the handler starts. After the handler is executed, the saved execution context is restored and the program execution is resumed. The above overhead occurs when the handler is started.
[0052]
On the other hand, in an architecture such as SMT (Simultaneous Multi-Threading) or CMP (on Chip Multi Processor) where multiple independent instruction streams can be controlled simultaneously, the handler is parallel to the main instruction stream. As a result, the overhead associated with the execution of the above-described handler can be reduced.
[0053]
When an architecture such as the above SMT is adopted, a plurality of instruction control units are provided. However, not all instruction control units are operating during processor operation. Therefore, when the instruction control unit is idling, by executing the above handler, it is possible to improve the operating rate of the arithmetic processing unit (processor) while reducing the execution overhead.
[0054]
FIG. 7 is a diagram showing a basic configuration of an example in which the present invention is applied to a system employing an SMT (Simultaneous Multi-Threading) architecture. In the figure, DC is a decoder, ALU is an arithmetic logic unit, and REG is a register. SU is a scheduling unit. FPA is a floating point adder, FPM is a floating point multiplier, FPD is a floating point divider, and LD / ST is a load store unit.
[0055]
The instruction fetch unit 120 includes a register for storing a prefetch instruction insertion address and a comparator, as described with reference to FIG. The sequencers 121a, 121b, and 121c for controlling each thread have independent registers. Reference numerals 128a, 128b and 128c indicate instruction queues.
[0056]
In such a configuration, when a cache miss event counter (not shown) overflows, when the event is notified as an interrupt, the interrupt is notified only to a specific sequencer (for example, 121c). Thus, a handler for processing cache miss information is executed by a specific sequencer.
[0057]
Since the main instruction stream is executed using another sequencer, the execution of the main instruction stream is not hindered when the handler is executed. Further, in the case of this figure, since an execution context (register) such as a register is held for each sequencer, there is no overhead of save / restore processing when the handler is started / finished.
[0058]
The present invention has been described in detail with particular reference to preferred embodiments thereof. For easy understanding of the present invention, specific embodiments of the present invention will be described below.
[0059]
(Supplementary Note 1) An arithmetic processing unit that dynamically inserts and executes a prefetch instruction instructing to transfer data from a main memory to a cache memory in advance in an instruction sequence,
Prefetch target selection means for selecting an instruction to be subject to prefetch processing among instructions causing a cache miss;
An address predicting means for predicting a memory access address at the time of execution of an instruction to be prefetched by the prefetch target selecting means;
Prefetch instruction insertion position determination means for determining an insertion position in an instruction string of a prefetch instruction corresponding to an instruction subjected to prefetch processing by the prefetch target selection means;
Prefetch instruction insertion means for inserting a prefetch instruction having a memory access address predicted by the address prediction means as an operand at an insertion position determined by the prefetch instruction insertion position determination means;
An arithmetic processing apparatus comprising:
[0060]
(Supplementary Note 2) The prefetch target selection means includes a counter that counts the number of times a cache miss occurs for each instruction address, and activates a handler that processes cache miss information when the counter value exceeds a certain value. The arithmetic processing apparatus according to attachment 1, wherein the handler selects an instruction to be subjected to prefetch processing.
[0061]
(Additional remark 3) The said prefetch instruction insertion position determination means is provided with the table which hold | maintains an instruction address and execution completion time about the instruction sequence which execution completed in the past, Based on the information of this table, the instruction sequence of the prefetch instruction The arithmetic processing apparatus according to Supplementary Note 1 or Supplementary Note 2, which determines an insertion position.
[0062]
(Supplementary Note 4) The arithmetic processing apparatus according to Supplementary Note 1, wherein the prefetch target selection unit, the prefetch instruction insertion position determination unit, the address prediction unit, and the prefetch instruction insertion unit are provided in a cache memory.
[0063]
(Supplementary note 5) The arithmetic processing unit according to supplementary note 3, wherein a plurality of execution instruction streams are controllable, and a handler for processing the cache miss information is executed independently of a main instruction stream as an independent instruction stream.
[0064]
(Supplementary Note 6) An arithmetic processing method of executing a prefetch instruction for instructing to transfer data from a main memory to a cache memory in advance and dynamically inserting it into an instruction sequence,
(a) selecting an instruction to be subjected to prefetch processing among instructions causing a cache miss; and
(b) a step of predicting a memory access address at the time of execution of the instruction targeted for prefetch processing in step (a);
(c) determining an insertion position in the instruction string of the prefetch instruction corresponding to the instruction subjected to the prefetch processing in step (a);
(d) inserting a prefetch instruction having the memory access address predicted in step (b) as an operand at the insertion position determined in step (c);
An arithmetic processing method comprising:
[0065]
(Supplementary note 7) Step (a) measures the number of times a cache miss occurs for each instruction address, and when the number exceeds a certain value, starts a handler that processes cache miss information. The arithmetic processing method according to attachment 6, wherein an instruction to be subjected to prefetch processing is selected.
[0066]
(Supplementary Note 8) Step (c) includes a table that holds an instruction address and an execution completion time for an instruction sequence that has been executed in the past. Based on information in the table, the insertion position of the prefetch instruction in the instruction sequence is determined. The arithmetic processing method according to appendix 6 or appendix 7, which is determined.
[0067]
(Supplementary note 9) The arithmetic operation according to supplementary note 8, further comprising a step of controlling a plurality of execution instruction streams and causing the handler for processing the cache miss information to be executed independently of the main instruction stream as an independent instruction stream. Processing method.
[0068]
【The invention's effect】
As described above, according to the present invention, in an arithmetic processing unit equipped with a cache memory, by inserting a prefetch instruction into an instruction stream based on execution time information, it is possible to prevent cache contamination associated with the conventional prefetch method. It is possible to efficiently perform prefetching while minimizing problems.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining the outline of the operation of an arithmetic processing unit that performs prefetch instruction insertion processing according to the present invention;
FIG. 2 is a diagram illustrating a configuration example of an arithmetic processing apparatus according to the present invention.
FIG. 3 is a diagram illustrating a configuration of a table that stores the number of times a cache miss has occurred for each instruction address;
FIG. 4 is a diagram showing a configuration of an execution history table.
FIG. 5 is a diagram showing a sample program.
FIG. 6 is a diagram showing contents of an execution history table together with an instruction stream when a sample program is executed.
FIG. 7 is a diagram showing a basic configuration of an example in which the present invention is applied to a system adopting an SMT architecture.
[Explanation of symbols]
10 ... Main memory
12 ... Instruction cache
14 ... Data cache
20 ... Instruction fetch unit
22a to 22d: Prefetch instruction insertion address register
24 ... Program counter (PC)
26a to 26d: Comparator
28 ... Instruction queue
30 ... Decoder
32 ... Branch instruction processing unit
34. Arithmetic instruction processing unit
36 ... Load / store instruction processing unit
40: Register file
42 ... Event counter
50 ... Execution history table
60: Address prediction unit
120 ... Instruction fetch unit
121a, 121b, 121c ... sequencer
128a, 128b, 128c ... instruction queue

Claims (3)

An arithmetic processing unit that employs an architecture capable of simultaneously controlling a plurality of execution instruction streams, and that dynamically inserts a prefetch instruction instructing to transfer data from the main memory to the cache memory in advance into the instruction sequence. There,
Prefetch target selection means for selecting an instruction to be subject to prefetch processing among instructions causing a cache miss;
An address predicting means for predicting a memory access address at the time of execution of an instruction to be prefetched by the prefetch target selecting means;
Prefetch instruction insertion position determination means for determining an insertion position in an instruction string of a prefetch instruction corresponding to an instruction subjected to prefetch processing by the prefetch target selection means;
Prefetch instruction insertion means for inserting a prefetch instruction having a memory access address predicted by the address prediction means as an operand at an insertion position determined by the prefetch instruction insertion position determination means;
Equipped with,
The prefetch target selection means includes a counter for measuring the number of times a cache miss occurs for each instruction address, and activates a handler that processes cache miss information when the value of the counter exceeds a certain value, The instruction to be prefetched by the handler is selected, and
The prefetch target selecting means causes a handler for processing the cache miss information to be executed as an instruction stream independent of a main instruction stream;
Arithmetic processing unit. The prefetch instruction insertion position determining means includes a table that holds an instruction address and an execution completion time for an instruction sequence that has been executed in the past, and determines an insertion position of the prefetch instruction in the instruction sequence based on information in the table The arithmetic processing device according to claim 1 .   The arithmetic processing apparatus according to claim 1, wherein the prefetch target selection unit, the prefetch instruction insertion position determination unit, the address prediction unit, and the prefetch instruction insertion unit are provided in a cache memory.

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