JPS53109443A - Data processor - Google Patents

Data processor

Info

Publication number
JPS53109443A
JPS53109443A JP2384977A JP2384977A JPS53109443A JP S53109443 A JPS53109443 A JP S53109443A JP 2384977 A JP2384977 A JP 2384977A JP 2384977 A JP2384977 A JP 2384977A JP S53109443 A JPS53109443 A JP S53109443A
Authority
JP
Japan
Prior art keywords
data processor
instruction
bytes
length
bridging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2384977A
Other languages
Japanese (ja)
Inventor
Kanji Kubo
Mamoru Hinai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2384977A priority Critical patent/JPS53109443A/en
Publication of JPS53109443A publication Critical patent/JPS53109443A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To realize the data processor reading out the instructions efficiently, by adding the data signal line by the length corresponding to the latter half of the instruction bridging the boundary of instruction readout (when the length of instruction is 4 bytes, then 2 bytes).
COPYRIGHT: (C)1978,JPO&Japio
JP2384977A 1977-03-07 1977-03-07 Data processor Pending JPS53109443A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2384977A JPS53109443A (en) 1977-03-07 1977-03-07 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2384977A JPS53109443A (en) 1977-03-07 1977-03-07 Data processor

Publications (1)

Publication Number Publication Date
JPS53109443A true JPS53109443A (en) 1978-09-25

Family

ID=12121846

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2384977A Pending JPS53109443A (en) 1977-03-07 1977-03-07 Data processor

Country Status (1)

Country Link
JP (1) JPS53109443A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6043742A (en) * 1983-08-19 1985-03-08 Toshiba Corp Reading circuit of variable length data
JPS61165166A (en) * 1984-12-24 1986-07-25 Fujitsu Ltd Data buffer controlling system
JP2009535743A (en) * 2006-05-01 2009-10-01 クゥアルコム・インコーポレイテッド Method and apparatus for caching variable length instructions

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49122933A (en) * 1973-03-26 1974-11-25
JPS5096144A (en) * 1973-12-24 1975-07-31

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49122933A (en) * 1973-03-26 1974-11-25
JPS5096144A (en) * 1973-12-24 1975-07-31

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6043742A (en) * 1983-08-19 1985-03-08 Toshiba Corp Reading circuit of variable length data
JPS61165166A (en) * 1984-12-24 1986-07-25 Fujitsu Ltd Data buffer controlling system
JP2009535743A (en) * 2006-05-01 2009-10-01 クゥアルコム・インコーポレイテッド Method and apparatus for caching variable length instructions

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