WO2007126274A1

WO2007126274A1 - Memory device and method for processing instruction

Info

Publication number: WO2007126274A1
Application number: PCT/KR2007/002101
Authority: WO
Inventors: Se-Jin Kang
Original assignee: Mtekvision Co., Ltd.
Priority date: 2006-04-27
Filing date: 2007-04-27
Publication date: 2007-11-08
Also published as: KR20070105779A

Abstract

A memory device having a processing function and a method thereof are provided. The memory device has a memory unit, which is written with at least one piece of data and command information by a processor, and a processing part, which processes the data written in the memory unit according to the command information. With the present invention, the memory device can independently carry out a command received from a processor and increase the efficiency of a processor that processes data written in the memory device.

Description

[DESCRIPTION]

[Invention Title]

MEMORY DEVICE AND METHOD FOR PROCESSING INSTRUCTION

[Technical Field]

The present invention relates to a memory device, more particularly to a

memory device having a processing function and a method for processing a memory

device.

[Background Art]

A conventional memory control method was an interrupt method, in which a

series of operations are completed as a processor (the central processing unit) sends a

command (for example, a data send command to a data receive terminal) to an

internally equipped or connected input/output controller and the input/output controller

executes the received command.

In the conventional memory control method, in a case of an independently

equipped input/output controller, it was possible that a processor carries out another

operation before the input/output controller finished the received command. However,

the processor had to be directly involved in a communication between a memory device

and an input/output controller. To improve this problem, a DMA (Direct Memory access) method has been

suggested. In this method, data is transmitted directly between memories or between a

memory and a peripheral device without using a processor. Therefore, a DMA

controller has to be disposed such that there is given guidance in discovering about an

address of an input/output controller, operation designated data (for example, data for

analyzing conducting command for a reading and/or writing action), a starting address

in a storage unit in a memory, transmitted data, etc. because the DMA method does not

use a processor.

The DMA method had a merit, in which a load of a processor is decreased and

a processor is not used in a memory controlling. However, the memory had to have a

direct memory control function, and each corresponding interface had to be disposed for

a direct memory controller to communicate with a processor or memory. Moreover,

memory replacement was limited because the corresponding interface had to be

disposed for linking with the direct memory controller.

[Disclosure]

[Technical Problem]

The present invention provides a memory device and a method for processing

instruction that has a process function in which a memory device can carry out a

command independently. The present invention provides a memory device and a method for processing

instruction that has a processing unit that can increase an efficiency rate of a processor

that processes data written in a memory device.

The present invention provides a memory device and a method for processing

instruction that can increase an efficiency rate and a process speed of a system in a case

data written in a memory device is displayed through an external output device.

Other technical problems of the present invention can be easily understood

through the below description about certain embodiment(s) of the present invention.

[Technical Solution]

An aspect of the present invention features a memory device that has a

processing function.

The memory device in accordance with an embodiment of the present

invention has a memory unit, which stores data and command information written by a

processor, and a processing part, which processes the data in accordance with the

command information stored in the memory unit.

The process can be one of the data copy process, data operation process and

data output process through an external output device.

The command information can include command start information for

instructing to start the process and command processing information for designating the type and content of the process.

If the process is a data copy process, the command processing information can

include type information for designating the type of the process, address information in

which source data is written, and address information in which data to which the source

data is copied is to be written. The address information is in the memory unit.

If the process is a data operation process, the command processing information

can include type information for designating the type of the process, address

information in which source data is written, and address information in which data

processed from the source data is to be written. The address information is in the

memory unit.

If the process is a data output process, the command processing information

can include type information for designating the type of the process, address

information in which source data to be outputted through the external output device is

written, and address information in which information on the external output device and

data to be outputted are to be written. The address information is in the memory unit.

According to an embodiment of the present invention, the memory unit can

include a storage area, in which data is written, a mailbox controlling register, in which

the command start information is written, and a mailbox, in which the command

processing information is written.

The memory unit can also have a mail out box, in which command complete information corresponding to a result of the process by the processing part is written.

Furthermore, the processing part can include a command signal generating unit,

which determines whether the command start information is written and outputting a

command starting signal if the command start information is written, and a command

process unit, which reads the command processing information and carries out a process

corresponding to the command processing information in accordance with the command

starting signal.

The processing part can output an interrupt signal to the processor if a process

corresponding to the command information is completed.

The memory device can be located between the processor and the external

output device.

The memory device, in accordance with an embodiment of the present

invention, shared by a plurality of processors can include a memory unit, in which data

and command information written by a processor are stored, and a plurality of

processing parts, which processes the data in accordance with the command information

stored in the memory unit. Each of the processing parts can be disposed for each of the

connected processors, respectively.

There can be one or more memory units included in the memory device shared

by the plurality of processors. However, each of the processing parts can be individually

disposed for each of the plurality of processors. If there is a plurality of the memory units, particularly, each of the memory

units can be assigned to each of the respective processors to be paired with the

processing part.

Moreover, if one or more memory units are disposed, one of the memory units

can have a plurality of partitions corresponding to the number of the connected

processors, and each partition can be assigned to each respective processor to be paired

with the processing part.

Furthermore, if one of the memory units is assigned to the processing parts,

each of which is connected to each of the plurality of processors, regardless of the

number of the processors, and stores data, the processing part can carry out a process

individually according to command information only by a connected processor.

In other words, the memory unit can be equipped in pairs with the plurality of

processing parts physically or logically using logical partition. The plurality of

processing parts can share a partition in which command information transferred from

the processor is recorded, hi this case, however, each processor can write information,

instructing the processing part connected to the processor to process a command such

that each of the processing parts can process a command in accordance with the

command of the processor, in the same partition.

The process is one of a data copy process, a data operation process and a data

output process through an external output device. The command information can also include command start information for

instructing to start the process, and command processing information for designating the

type and content of the process.

If the command start information and command processing information are

distinguished and written in the memory unit from the processor, the memory unit can

include a storage area, in which at least one piece of data is written, a mailbox

controlling register, in which the command start information is written, and a mailbox,

in which the command processing information is written.

The memory unit can also have a mail out box, in which command complete

information corresponding to a result of the process by the processing part is written.

The processing part can include a command signal generating unit, which

determines whether the command start information is written and outputs a command

starting signal if the command start information is written; and a command process unit,

which reads the command processing information and carries out a process

starting signal.

Moreover, the processing part can output an interrupt signal to the processor if

a process corresponding to the command information is completed.

An aspect of the present invention features a method for a memory device to

perform a predetermined process. Include in the method are the steps of: determining whether command start information is written by a processor; if the command start

information is written, reading written command processing information in accordance

with the command start information; and performing the predetermined process

according to the read command processing information.

Command complete information can be written if the process is completed.

The command complete information is a result value according to the performance of

the process.

Command complete information can be outputted if the process is completed.

the process.

An interrupt signal can be outputted to the processor if the process is

completed.

An aspect of the present invention features a recorded medium, which tangibly

embodies a program of instructions that are executable by a memory device to execute a

method of performing a process. The program is readable by the memory device and

executes: determining whether command start information is written by a processor; if

the command start information is written, reading written command processing

information in accordance with the command start information; and performing the

predetermined process according to the read command processing information. [Description of Drawings]

FIG. 1 is a block diagram of a memory device and a peripheral device

according to an embodiment of the present invention.

FIG. 2 illustrates a flowchart for processing a command if it is not necessary

for a processor to receive command completion information according to an

embodiment of the present invention.

FIG. 3 illustrates a flowchart for processing a command if it is necessary for a

processor to receive command completion information according to an embodiment of

the present invention.

FIG. 4 illustrates a flowchart for processing a command if a processing part

120 delivers command completion information to an external output device directly

according to an embodiment of the present invention.

FIG. 5 illustrates an example of a command to be processed in the processing

part 120 according to an embodiment of the present invention.

FIG. 6 illustrates a dual port memory device that indicates a command

processing relationship among several processors according to an embodiment of the

present invention.

[Mode for Invention]

As the claimed invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in drawings and described in

detail in the written description. However, this is not intended to limit the claimed

invention to particular modes of practice, and it is to be appreciated that all changes,

equivalents, and substitutes that do not depart from the spirit and technical scope of the

claimed invention are encompassed in the claimed invention. In describing each figure,

like reference numerals are used for like elements throughout.

While such terms as "first" and "second," etc., may be used to describe various

components, such components must not be limited to the above terms. The above terms

are used only to distinguish one component from another. For example, a first

component may be referred to as a second component without departing from the scope

of rights of the claimed invention, and likewise a second component may be referred to

as a first component. The term "and/or" encompasses both combinations of the plurality

of related items disclosed and any item from among the plurality of related items

disclosed.

When a component is mentioned to be "connected" to or "accessing" another

component, this may mean that it is directly connected to or accessing the other

component, but it is to be understood that another component may exist in-between. On

the other hand, when a component is mentioned to be "directly connected" to or

"directly accessing" another component, it is to be understood that there are no other

components in-between. The terms used in the present application are merely used to describe particular

embodiments, and are not intended to limit the claimed invention. An expression used

in the singular encompasses the expression of the plural, unless it has a clearly different

meaning in the context. In the present application, it is to be understood that the terms

such as "including" or "having," etc., are intended to indicate the existence of the

features, numbers, operations, actions, components, parts, or combinations thereof

disclosed in the specification, and are not intended to preclude the possibility that one or

more other features, numbers, operations, actions, components, parts, or combinations

thereof may exist or may be added.

Unless otherwise defined, all terms used herein, including technical or

scientific terms, have the same meanings as those generally understood by those with

ordinary knowledge in the field of art to which the claimed invention belongs. Such

terms as those defined in a generally used dictionary are to be interpreted to have the

meanings equal to the contextual meanings in the relevant field of art, and are not to be

interpreted to have ideal or excessively formal meanings unless clearly defined in the

present application.

Embodiments of the claimed invention will be described below in detail with

reference to the accompanying drawings. For better understanding overall in describing

aspects of the claimed invention, the same reference numerals are used for the same

means, regardless of the figure number. FIG. 1 is a block diagram of a memory device and a peripheral device

according to an embodiment of the present invention.

Referring to FIG. 1, a memory device according to an embodiment of the

present invention 100 has a memory unit 110 and the processing part 120.

The memory unit 110 can have a mailbox controlling register 112, a mailbox

114, a mail out box 116 sind a storage area 118. The memory unit 110 can be, for

example, an SDRAM.

The mailbox controlling register 112 is the region in which command start

information is written by a processor 130. The command initiation information is for

starting command processing information that is written in the mailbox 114 by the

processor 130.

The processor 130 can access a mailbox controlling register 112 and write the

command start information (for example, ' 1 ' or O', but presumed to be ' 1 ' hereinafter).

The mailbox controlling register 112 can be a storage unit with, for example, tens of

bytes, and the processor 130 can read a value written therein or write a value therein.

The processing part 120 may not carry out any operation in a case '0' is written

in a mailbox controlling register 112 even though command processing information is

written in the mailbox 114. Then, if ' 1 ' is written in the mailbox controlling register 112,

a process (for example, data copy, graphic data process, data output to the external

output device 140, etc.) corresponding to the command processing information written in the mailbox 114 is caπied out. Of course, the command start information can be

written as a value of n (n being a natural number) bits and it shall be evident that, when

a value is written, the criteria for determining whether or not the value is the command

start information can be configured in various ways.

The mail box 114 is a region in which the command processing information is

written by the processor 130. The command processing information indicates the

contents of a command which the processing part 120 is to carry out.

The type of command processing information can be predetermined to be

recognized by the processing part 120. For example, the command processing

information can be an operational command for mutually operating each value written

in an address of the storage area 118 and writing its result in a new address. And the

operational command can include an operational command for operating a value (for

example, operating a log value, an exponential value, etc.) written in the address.

The mail out box 116 is an area in which the command complete information,

which is the result value processed corresponding to the command processing

information, is written by the processing part 120. In this case, according to the type of

the command processing unit, it can be determined whether the processing part 120

writes the command complete information in the mail out box 116, which will be

further described in detail with reference to FIGS. 2 to 4 below. Of course, since an

address to be written with the processed result value is designated by the pertinent professor 130, the mail out box 116 can be omitted if an address of the storage area 118

is predesignated as an address in which the processed result value is to be written.

However, the description assumes the case of allotting the mail out box 116 separately

in order that the processor 130 can receive the processed result value.

The storage area 118 is a storing area in which the data, to be processed by the

processing part 120 or to be used by each processor 130, is written. The mailbox

controlling register 112, the mailbox 114 and the mail out box 116 can be areas of the

storage area 118 that are allotted for designated work.

The processing part 120 can include the command signal generating unit 122

and the command processing unit 124. For the convenience of description and

understanding, Fig. 1 illustrates the command signal generating unit 122 and the

processing part 124, respectively, as an independent element. However, it shall be

obvious that both of them can be unificably realized in case that the command

processing unit 124 additionally performs the function of the command signal

generating unit 122. It is also obvious that the processing part 120 can be realized as a

software program (or the combination of program codes).

If the command signal generating unit 122 recognizes that the command start

information is written in the mail box controlling register 112, the command signal

generating unit 122 provides a command starting signal to the command processing unit

124 such that the command processing unit 124 can perform a processing operation corresponding to the command processing information written in the mail box 114. The

command signal generating unit 122 will be able to sense whether the command start

information is written by monitoring the mail box controlling register 112 continuously

or periodically.

Briefly described below is the processing operation of the command signal

generating unit 122.

If the command start information, for example, ' 1 ', is written in the mail box

controlling register 112, the command signal generating unit 122 can generate the

command starting signal in a predetermined form by using a toggle signal and a delay

signal for periodically outputting each toggle signal.

If the command starting signal is inputted from the command signal generating

unit 122, the command processing unit 124 reads the command processing information

written in the mail box 114 and performs a predetermined processing operation (i.e.

processes a pertinent command) corresponding to the pertinent command processing

information. In this case, the command processing unit 124 can write the command

complete information as the result value according to the type of pertinent command

processing information in the mail out box 116 or transfer the data, to be outputted to

the external output device 140.

Also, in case that the processing operation, corresponding to the command

processing information written by the processor 130, is completed, the processing part 120 outputs an interrupt signal, indicating that the performance of the command

processing information is completed, to the corresponding processor 130.

As described above, the command processing information, written by the

processor 130, can be a command (e.g. a copy command) reading the data written in an

address of the storage area 118, writing the read data in another address and another

command (e.g. an operation command) calculating (e.g. one of 4 fundamental rules of

arithmetic, log and exponent) the read value and writes the result value in another

address and another command (e.g. an output command) converting the read data into

data in a form capable of being outputted through the external output device 140 and

transferred to the external output device 140.

Of course, in case that the processor 130 is directly coupled to the external

output device 140 and performs an additional operation (e.g. the processor 130

processes graphic data, and then, directly outputs the processed graphic data through the

external output device), the processor 130 can control the external output device 140

independently of the memory device 100, and it shall be obvious that data-processing

and data input/output relationship between the processor 130, the memory device 100

and the external output device 140 can be variously determined.

Also, the aforementioned interrupt signal is a signal that the processing part

120 transmits to the processor 130 in order to inform that the processing corresponding

to the directed command processing information is completed. The interrupt signal can be designated in a form of signal transition (e.g. low to high or high to low) or an edge

signal (e.g. rising edge or falling edge), for example.

FIG. 2 illustrates a flowchart for processing the command in a case the

processor does not need to receive the command complete information, which is the

result value for the command processing information, from the processing part 120

according to an embodiment of the present invention.

For a case of the processor 130 not needing to receive the command complete

information corresponding to the command processing information, the command

processing information can be a copy command, for example.

In a step represented by S200, the processor 130 writes the command

processing information processed by the processing part 120 and the command start

information for indicating the start of the command processing in the memory unit 110.

As described above, the areas written with the command processing information and the

command start information, respectively, can be different from each other. In this case,

the processor 130 can write the command processing information after completing the

writing of the command start information or can write the command start information

after writing the command processing information.

In a step represented by S210, the processing part 120 senses that the command

start information is written in the memory unit 110. As described above, the command

signal generating unit 122 or the command processing unit 124 can sense whether the command start information is written.

The command signal generating unit 122, which sensed that the command start

information has been written, generates the command starting signal for indicating to

start processing corresponding to the command processing information, and outputs the

command starting signal to the command processing unit 124 in a step represented by

S220. As described above, in case that the command signal generating unit 122 and the

command processing unit 124 are unificably realized, the step represented by S220 may

be omitted.

The processing part 120 reads the command processing information written in

the memory unit 110 in a step represented by S230. Then, the step represented by S240

is performed to carry out a corresponding processing operation. The type and processing

method of the command to be processed by the processing part 120 through the

command processing information can be predetermined. It shall be obvious that the

processing part 120 is realized in order to make it possible to perform a corresponding

operation.

As described above, in the case of the copy command copying data written in a

first address of the storage area 118 in a second address of the storage area 118, the

processing part 120 reads the data written in the first address and copies the read data in

the second address.

In a step represented by S250, the processing part 120 outputs an interrupt signal, informing that the processing of the command processing information is

completed, to the processor 130 having written the command processing information.

FIG. 3 illustrates a flowchart for processing the command in a case the

processor needs to receive the command complete information according to another

embodiment of the present invention.

However, the description related to the same part as that of FIG. 2 will be

omitted. Besides, steps represented by S300 through S340, which are the same as the

command processing method described in FIG. 2, will be omitted.

In a step represented by S350, the processing part 120 processes the command

according to command processing information. Then, the processing part 120 writes

command complete information, which is the result value of the command processing

corresponding to the command processing information, in a particular area of the

memory unit 110. The particular area is designated by the processor 130, and can be the

mail out box, for example. In this case, it is necessary to re-transfer the command

complete information to the processor 130. As an example of the command processing

information, there can be provided an operational command, which

operational-processes (e.g. generates a new result value by using 4 fundamental rules of

arithmetic, or generates a new result value by using a log operation or an exponent

operation) information, written in a particular portion C of the storage area 118, and information, written in another portion D of the storage area 118, and writes the

information in another particular portion E.

The step represented by S360 will be omitted because the description is related

to the same part as that of the step represented by S260 in FIG. 2.

In a step represented by S370, in case the command is processed by the

processing part 120, the processing part 120 generates and outputs the interrupt signal to

the processor 130, which then reads the command complete information from the

particular portion E written with the command complete information. Of course, it is

possible that the processor 130 does not read the command complete information. For

example, in case that the processor 130 performs a process corresponding to an

improper operational command, the processor 130 may not read the command complete

information and delete the read command complete information.

FIG. 4 illustrates a flowchart for processing the command in case the

processing part 120 directly transmits the command complete information to the

external output device according to another embodiment of the present invention. Of

course, as described above, the processor 130 can output a data to the external output

device 140 directly. However, the description related to the same part described above

will be omitted. Steps represented by S400 through S440, which are the same as the

command processing method described in FIG. 2, will be omitted.

In a step represented by S450, after processing the command corresponding to the command processing information, the processing part 120 transfers the command

complete information, the result value of the processing, to the external output device

140. As an example of the command processing information, there can be provided an

operational command, which operational-processes information, written in a particular

portion F of the storage area 118 in the memory unit 110, and information, written in

another portion G, and outputs the command complete information, the result value of

the processing, to the external output device 140.

The step represented by S460 will be omitted because the description is related

to the same part as that of the step represented by S260 in FIG. 2.

FIG. 5 illustrates the structure of a copy command, which is one of command

processing information in accordance with an embodiment of the present invention.

Referring to FIG. 5, the command processing apparatus corresponding to the

copy command can include a first row, designating the type of the pertinent command, a

second row, indicating a writing address of source data, a third row, indicating a

destination address, which is the address to be written with copied data, and a fourth

row indicating the size of data to be written.

In detail, the command processing information of FIG. 5shows that 'OxffffδO'

(510-1) of the address of the mail box 114 is written with "0x0001" (530-1, i.e. the copy

command) indicating the type of the pertinent command, and "0xffff84" (510-2) of the address of the mail box 114 is written with the address (530-2) in the storage area 118

written with the source data. Although FIG. 5 illustrates that the pertinent address

(530-2) is marked as "not fixed", it shall be obvious that the pertinent field can be

substantially written with a related address.

Similarly, "Oxffff88" (510-3) of the address of the mail box 114 is written with

an address (530-3) to be written with the copied data, and "OxffffSc" (510-4) of the

address of the mail box 114 is written with the size (530-4) of data to be copied.

Of course, it shall be obvious that the exampled structure of the command

processing information can vary depending on the type of the pertinent command. For

example, in the case of the operational command, a plurality of source data addresses,

which are the object of the operation, can be included, and an address to be written with

the operated result value can be included. And in the case of the output command, the

address to be written with the operated result value can be omitted, and in the case of a

plurality of external output devices 140, information determining through which one of

the plurality of external output devices 140 is to output can be also included.

FIG. 6 illustrates a dual port memory device indicating command processing

relations from a plurality of processors in accordance with another embodiment of the

present invention.

It is obvious that the technical ideas of the present invention can be applied to a multi-port memory device without any restriction. However, for the convenience of

description and understanding, the below description assumes that the memory device is

a dual port memory device shared by 2 processors.

In case that one memory device 600 is shared by a plurality of processors 640

and 650, the memory device 600 can be equipped with memory units 612 and 614 and

processing parts 620 and 630, corresponding to each processor.

In other words, a first processor 640 writes command processing information

and command start information in predetermined areas, respectively, of a first memory

unit 612, and a second processor 650 writes command processing information and

command start information in predetermined areas, respectively, of a second memory

unit 614.

A first processing part 620 performs corresponding processing by using the

command processing information and the command start information, written in the

first memory unit 612, and then outputs an interrupt signal to the first processor 640. A

second processing part 630 performs corresponding processing by using the command

processing information and the command start information, written in the second

memory unit 614, and then outputs an interrupt signal to the second processor 650.

The first and second memory units 612 and 614 can have the identical or

similar structure to the memory unit 110, described with reference to FIG. 1. In other

words, in case that the storage area accessible for each processor is logically divided and determined, the first and second memory units 612 and 614 can have the same

structure as the memory unit 110 of FIG. 1. However, in case that the storage area is set

to be commonly accessible but each element, such as the mail box 114, is independently

allotted, the first and second memory units 612 and 614 will have a little different

structure from the memory unit 110 of FIG. 1.

However, in the case of the latter, if addresses to be written with the result

values by the processing directed by each processor are identical to each other, it may

be impossible to complete the proper processing. To prevent this problem, the address

for being written with the processed result values can be differently set per each

processor. Alternatively, the step of mutually checking the command processing

information between each processing parts 620 and 630 (or between the processors) can

be allowed to be performed before the writing of the processed value.

In other words, the memory unit can be equipped in pairs with a plurality of the

processing parts physically or logically using logical partition. And the plurality of

processing parts can share an area in which the command information delivered from

the processor is recorded. However, in this case, each processor can write information

for which the processing part connected to the processor carries out the command in the

same area for carrying out the command corresponding to the command by the

processor.

The dual port memory device connected to the plurality of processors in accordance with an embodiment of the present invention can be located between the

plurality of processors and the external output device. And, the external output device

can be disposed in pairs corresponding to the plurality of processors. The external

output device can be equipped in association with the plurality of the processor.

In other words, the plurality of processing parts can be equipped in pairs

corresponding to the plurality of processors and can be connected in pairs with the

external output device. It shall be obvious that the plurality of processing parts can be

disposed in pairs corresponding with the plurality of processors or connected in

association with the external output device to carry out a process (e.g. an external output

command) corresponding to the command processing information written by the

processor.

The drawings and detailed description are only examples of the present

invention, serve only for describing the present invention and by no means limit or

restrict the spirit and scope of the present invention. Thus, any person of ordinary skill

in the art shall understand that a large number of permutations and other equivalent

embodiments are possible. The true scope of the present invention must be defined only

by the spirit of the appended claims.

[Industrial Applicability]

The memory device and method for processing an instruction method according to the present invention can carry out the command independently.

The memory device and method for processing an instruction method

according to the present invention can increase the efficiency of a processor that

processes data written in a memory device.

The memory device and method for processing an instruction method of the

present invention can increase the efficiency and process speed of a system in case data

written in a memory device is displayed through an external output device.

The memory device and method for processing an instruction method of the

present invention can easily exchange a memory device because it is not necessary to

have a separate interface for applying a direct memory control method.

Claims

[CLAIMS]

[Claim 1]

A memory device comprising:

a memory unit, storing data and command information being written by a

processor; and

a processing pant, processing the data in accordance with the command

information stored in the memory unit.

[Claim 2]

The memory device of Claim 1, wherein the process is one of the data copy

process, data operation process and data output process through an external output

device.

[Claim 3]

The memory device of Claim 2, wherein the command information comprises:

command start information for instructing to start the process;

and command processing information for designating the type and content of

the process.

[Claim 4] The memory device of Claim 3, wherein, if the process is a data copy process,

the command processing information comprises type information for designating the

type of the process, address information in which source data is written, and address

information in which data to which the source data is copied is to be written, the address

information being in the memory unit.

[Claim 5]

The memory device of Claim 3, wherein, if the process is a data operation

process, the command processing information comprises type information for

designating the type of the process, address information in which source data is written,

and address information in which data processed from the source data is to be written,

the address information being in the memory unit.

[Claim 6]

The memory device of Claim 3, wherein, if the process is a data output process,

type of the process, address information in which source data to be outputted through

the external output device is written, and address information in which information on

the external output device and data to be outputted are to be written, the address

information being in the memory unit.

[Claim 7]

The memory device of Claim 3, wherein the memory unit comprises:

a storage area, in which data is written;

a mailbox controlling register, in which the command start information is

written; and

a mailbox, in which the command processing information is written.

[Claim 8]

The memory device of Claim 3, wherein the memory unit further comprises a

mail out box, in which command complete information corresponding to a result of the

process by the processing part is written.

[Claim 9]

The memory device according to any one of the Claims 3 to 8, wherein the

processing part comprises:

a command signal generating unit, determining whether the command start

information is written and outputting a command starting signal if the command start

information is written; and

a command process unit, reading the command processing information and carrying out a process corresponding to the command processing information in

accordance with the command starting signal.

[Claim 10]

The memory device of Claim 1, wherein the processing part outputs an

interrupt signal to the processor if a process corresponding to the command information

is completed.

[Claim 11]

The memory device of Claim 2, wherein the memory device is located between

the processor and the external output device.

[Claim 12]

A memory device shared by a plurality of processors, the memory device

comprising:

a memory unit, in which data and command information written by a processor

are stored; and

a plurality of processing parts, processing the data in accordance with the

command information stored in the memory unit,

whereas each of the processing parts is disposed for each of the connected processors, respectively.

[Claim 13]

The memory device of Claim 12, wherein there are a plurality of the memory

units, and each of the memory units is assigned to each of the respective processors to

be paired with the processing part.

[Claim 14]

The memory device of Claim 12, wherein the memory unit comprises a

plurality of partitions corresponding to the number of the connected processors, and

each partition is assigned to each respective processor to be paired with the processing

part.

[Claim 15]

The memory device of Claim 12, wherein the memory unit is commonly

assigned to the processing part connected to each of the processors, whereas the

processing part carries out a process individually according to command information by

a connected processor.

[Claim 16] The memory device according to any one of the Claims 13 to 15, wherein the

process is one of a data copy process, a data operation process and a data output process

through an external output device.

[Claim 17]

The memory device of Claim 16, wherein the command information

comprises:

command start information for instructing to start the process; and

command processing information for designating the type and content of the

process.

[Claim 18]

The memory device of Claim 17, wherein, if the process is a data copy process,

information being in the storage area.

[Claim 19]

The memory device of Claim 17, wherein, if the process is a data operation process, the command processing information comprises type information for

designating the type of the process, a plurality of address information in which source

data is written, and address information in which data processed from the source data is

to be written, the address information being in the memory unit.

[Claim 20]

The memory device of Claim 17, wherein, if the process is a data output

process, the command processing information comprises type information for

designating the type of the process, address information in which one or more source

data to be outputted through the external output device is written, and address

information in which information on the external output device and data to be outputted

are to be written, the address information being in the memory unit.

[Claim 21]

The memory device of Claim 17, wherein the memory unit comprises:

a storage area, in which at least one piece of data is written;

a mailbox controlling register, in which the command start information is

written; and

a mailbox, in which the command processing information is written.

[Claim 22]

The memory device of Claim 21, wherein the memory unit further comprises a

process by the processing part is written.

[Claim 23]

The memory device of Claim 17, wherein the processing part comprises:

a command signal generating unit, determining whether the command start

information is written; and

a command process unit, reading the command processing information and

carrying out a process corresponding to the command processing information in

accordance with the command starting signal.

[Claim 24]

The memory device of Claim 12, wherein the processing part outputs an

is completed.

[Claim 25] The memory device according to any one of the Claims 12 to 15, wherein the

memory device is located between the processor and the external output device.

[Claim 26]

A method for a memory device to perform a predetermined process, the

method comprising:

(a) determining whether command start information is written by a processor;

(b) if the command start information is written, reading written command

processing information in accordance with the command start information; and

(c) performing the predetermined process according to the read command

processing information.

[Claim 27]

The method of Claim 26, wherein the step (c) further comprises writing

command complete information if the process is completed, the command complete

information being a result value according to the performance of the process.

[Claim 28]

The method of Claim 26, wherein the step (c) further comprises outputting

command complete information if the process is completed, the command complete information being a result value according to the performance of the process.

[Claim 29]

The method according to any one of the Claims 26 to 28 further comprising

outputting an interrupt signal to the processor if the process is completed.

[Claim 30]

A recorded medium tangibly embodying a program of instructions executable

by a memory device to execute a method of performing a process, the program being

readable by the memory device, the program executing:

determining whether command start information is written by a processor;

if the command start information is written, reading written command

processing information in accordance with the command start information; and

performing the predetermined process according to the read command

processing information.