WO2007114790A1 - procédé de fabrication d'une interconnexion permettant de raccorder électriquement un composant électrique à un substrat - Google Patents

procédé de fabrication d'une interconnexion permettant de raccorder électriquement un composant électrique à un substrat Download PDF

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Publication number
WO2007114790A1
WO2007114790A1 PCT/SG2006/000080 SG2006000080W WO2007114790A1 WO 2007114790 A1 WO2007114790 A1 WO 2007114790A1 SG 2006000080 W SG2006000080 W SG 2006000080W WO 2007114790 A1 WO2007114790 A1 WO 2007114790A1
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WO
WIPO (PCT)
Prior art keywords
solder bump
substrate
distance
solder
bump
Prior art date
Application number
PCT/SG2006/000080
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English (en)
Inventor
Ee Hua Wong
Ranjan S/O Rajoo
Kah Woon Simon Seah
Ah Ong Andrew Tay
Original Assignee
Agency For Science, Technology And Research
National University Of Singapore
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Publication date
Application filed by Agency For Science, Technology And Research, National University Of Singapore filed Critical Agency For Science, Technology And Research
Priority to PCT/SG2006/000080 priority Critical patent/WO2007114790A1/fr
Publication of WO2007114790A1 publication Critical patent/WO2007114790A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
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    • H05K2201/09427—Special relation between the location or dimension of a pad or land and the location or dimension of a terminal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the field of electrical interconnectors that are used to mount and electrically connect electrical components to their respective substrates. More specifically, the present invention relates to a method of fabricating a stretched spring interconnector with enhanced z-axis compliance (z-compliance) for mounting and electrically connecting an electrical component to a substrate.
  • z-compliance enhanced z-axis compliance
  • Electrical interconnectors have typically been employed in the mounting of integrated circuits (IC) onto printed circuit boards (PCB) or substrates and form part of the microelectronics packaging along with the substrate and an electrical component, such as an IC. Apart from providing an electrical connection between the IC and the PCB, electrical interconnectors also provide mechanical support and in some instances, assistance in the dissipation of the thermal energy generated by the IC.
  • 'drop-impact reliability is used to describe the reliability of an electrical interconnector that connects an IC package (or component) to a printed circuit board (PCB) when the device having said interconnectors undergoes a drop-impact. In other words, it implies a qualitative assessment of the tendency or likelihood of an interconnector to fail after undergoing a drop-impact.
  • thermal cycling of a microelectronics package may happen when the temperature of the microelectronics package itself changes cyclically such that the package (and its constituting elements) undergoes cyclic thermal expansion or contraction.
  • the constituting elements of the microelectronics package are made of different materials, said constituting elements may each have a differing thermal expansion coefficient. Accordingly, the differing thermal expansion coefficient gives rise to a thermal mismatch between the different constituting elements of the microelectronics package.
  • the effects of the thermal mismatch may be illustrated when the substrate expands at a higher rate than the mounted electrical component. In such an exemplary illustration, the interconnector between the substrate and the electrical component experiences a shear force which may result in the shearing of the interconnector.
  • Takahisa Doha, 2000 IEMP, Loctite, reworkability is an important industrial requirement as it allows for the possibility of design changes to be implemented with ease, and for manufacturing defects to be corrected at minimal cost.
  • the epoxy underfill when an electrical component mounted on a substrate requires adjustments or needs to be replaced, carrying out the required adjustments or replacements is very difficult once the epoxy sets.
  • the use of an epoxy underfill requires additional processing steps to be carried out.
  • the mounting of the exemplary CSP onto a PCB involves just two main steps. This is done simply by first placing the IC package having solder balls attached thereto, onto the PCB, followed by passing them through an oven to melt the solder balls to form the interconnection between the CSP and the PCB.
  • the epoxy underfill three additional processing steps are required.
  • the first additional step involves the baking of the PCBs for 24hrs to remove moisture prior to mounting the CSP. This is necessary as the presence of moisture may lead to delimination along the PCB — epoxy underfill interface.
  • the second additional processing step is the dispensing of the epoxy underfill between the CSP and the PCB after the interconnections have been formed therebetween.
  • the third additional processing step is the curing of the epoxy underfill through the application of heat. Accordingly, the additional processing requirements, as well as the materials required, give rise to higher manufacturing costs, as mentioned earlier.
  • U.S. Patent 6,787,456 Another method of forming interconnectors is also disclosed in U.S. Patent 6,787,456.
  • This patent also describes the fabrication of a spring-like structure, similar in functionality to that as described in the above U.S. patent.
  • the fabrication process described herein includes the method steps of forming a structure channel, filling the structure channel with the structure material and releasing the interconnector structure from the channel.
  • a first sacrificial layer is deposited on a substrate and patterned followed by a second sacrificial layer, which is also patterned by lithography, for example.
  • the channel formed from the patterned sacrificial layers is filled with the material that the interconnector is to be made of and finally, said interconnector structure is released from the channel.
  • such a method of fabricating an interconnection for electrically connecting an electrical component to a substrate comprises:
  • such a method for fabricating an interconnection for electrically connecting an electrical component to a substrate comprises: providing a first substrate and forming thereon at least one solder bump; providing a second substrate and forming thereon at least one solder-wettable pad; positioning said at least one solder bump and at least one solder-wettable pad to be in positional and angular alignment relative to one another, whereby the at least one solder bump and at least one solder- wettable pad are separated from one another by a first distance and the substrates are separated from one another by a second distance; heating the at least one solder bump till molten; reducing the first distance till the at least one molten solder contacts and adheres to the at least one solder-wettable pad to form an at least one single solder bump; maintaining the at least one single solder bump in its molten state while increasing the second distance between the two substrates thereby lengthening said at least one single solder bump forming an at least one elongated solder bump; terminating the step of increasing the
  • the first substrate having the at least one first solder bump formed thereon is typically a functional substrate.
  • the functional substrate include, but are not limited to, standard Very Large Scale Integration (VLSI) wafers, Ultra Large Scale Integration wafers (ULSI) wafers, Integrated Circuit (IC) devices, Chip Scale Packages (CSP), a matrix of CSP, and Wafer Level Packages (WLP).
  • VLSI Very Large Scale Integration
  • ULSI Ultra Large Scale Integration wafers
  • IC Integrated Circuit
  • CSP Chip Scale Packages
  • WLP Wafer Level Packages
  • the functional substrate includes, for example, electrical connections within the interiors of their wafers.
  • the second substrate having the at least one second solder bump formed thereon is either a dummy substrate or a functional substrate. When the second substrate is a functional substrate, said second substrate may be a printed circuit board (PCB) having electrical contact points.
  • PCB printed circuit board
  • the electrical contact points of the PCB correspond to the electrical contact points of the first substrate. That is, the location and layout of the at least one solder bump formed on the contact points of the second substrate correspond to the at least one solder bump formed on the contact points of the first substrate.
  • the second substrate is a dummy substrate
  • the layout and location of the solder bumps on the second substrate is identical to the layout and location of the solder bumps on the first substrate.
  • a more definitive location of the solder bumps formed thereon may be considered to be on the underside, or on the side to be mounted onto a PCB, for example.
  • Each solder bump on either the first or second substrate is typically formed from an alloy of tin (Sn).
  • solder alloy compositions include, but are not limited to, 95Pb5Sn, 95PbIOSn, 90PbIOSn, Pb37Sn, Sn3.5AgO.7Cu, Sn3Cu, SnO.7Cu, Sn3.5Ag, Sn20Au and 80Pb20Sn.
  • the adherence of the solder bump to the dummy substrate differs from that of a functional substrate.
  • the difference lies in the strength of adhesion between the solder bump and the dummy substrate.
  • the adhesive strength between a solder bump and a dummy substrate is significantly less than the adhesive strength between a solder bump and a functional substrate.
  • the variance in adhesive strength comes about from the introduction of a weak adhesion layer between the solder bump and the surface of the dummy substrate.
  • the weak adhesion layer when used in connection with a dummy substrate, may be a thin layer of metallic or organic materials that have low adhesion strength, such as silicon dioxide, for example, with the solder bump or with the surface of the dummy substrate.
  • the low adhesion strength may be attributed to the inherent properties of the mating surfaces concerned.
  • the weak adhesion layer could result from the active modification of the surface properties of the adhesion layer via chemical etching or plasma etching, for example.
  • the weak adhesion layer may be a result of a modification to the microstructure of the solder bump, especially at the interface with the dummy substrate, through heat treatment such as thermal aging, for example.
  • the first and second substrates having at least one first and second solder bump formed thereon respectively, are positioned such that they are in positional and angular alignment with respect to each other.
  • the two substrates may be considered to be positioned parallel to each other such that the at least one first and second solder bumps are facing each other in vertical alignment, separated by the first distance.
  • the first distance between the at least one first and second solder bumps refers to the vertical distance between the at least one first solder bump and the at least one second solder bump formed on the respective substrates that are in parallel alignment with each other.
  • the first distance separating the first solder bump and the second solder bump is typically at least 0.5mm.
  • the substrates are also in angular alignment with one another. The distance separating the first and second substrates is known as the second distance.
  • first substrate and the second substrate may be inclined at an angle with respect to each other.
  • the vertical alignment of the at least one first solder bump and the at least one second solder bump must still be in positional alignment with respect to each other.
  • the at least one first solder bump and the at least one second solder bump are still separated by a first distance and the respective substrates are also separated by a second distance.
  • the solder bump on the first substrate and those on the second substrate are heated till they are molten.
  • the melting point of said solder alloys typically lies within a range of about 26O 0 C - about 28O 0 C, for example.
  • the first distance i.e. the distance between the at least one first solder bump and the at least one second solder bump is reduced. Since the two respective solder bumps are in the molten state, when they contact each other, said solder bumps merge to form at least one single solder bump.
  • the single solder bump When the single solder bump is formed, it is maintained in its molten state by maintaining the temperature as mentioned above.
  • the second distance i.e. the distance separating the first and second substrates, is then increased gradually thereby elongating the single solder bump to form at least one elongated solder bump.
  • the elongation step of the at least one solder bump is terminated once the elongated solder bump achieves its desired aspect ratio.
  • the aspect ratio is the ratio between the stretched length (or height) of the interconnector to the bonding pad diameter on a chip, for example.
  • the aspect ratio of the interconnector is thus manipulated by changing the stretched length of the interconnector.
  • an un- stretched solder joint typically gives an aspect ratio of about 0.8. Since the diameter of the bonding pad is a constant, any amount of stretching of the solder interconnect leads to an increase in the aspect ratio.
  • any increase in the aspect ratio of the solder interconnect increases its compliance, which in turn typically leads to reduced stress within the interconnect when it is subjected to temperature cycling. Accordingly, a high aspect ratio compensates well against the effects of temperature cycling and possibly, against the effects of drop impacts as well, hi the context of the present invention, the desired aspect ratio is, but is not limited to, at least 0.5 or 0.8, for example. Further exemplary values of the aspect ratio maybe 1, 2, 3, 4, any value therebetween or even higher.
  • the temperature of the at least one elongated solder bump is reduced and maintained at one that is suitable for hot working said solder bump while also being low enough so as to minimize damage to the interconnector during the subsequent solid-state deformation.
  • the hot working temperature of a metal such as a solder, for example, is defined as the temperature above which re- crystallization takes place such that the metal can be deformed continuously without fracture, i.e. is malleable.
  • the malleability of a metal is the property describing the ability of the metals to be deformed and shaped and increases at higher temperatures. Accordingly, most metals have limited malleability at room temperature.
  • the upper limit for the hot- working temperature of a metal is determined by the temperature at which the metals still retains its solid-state strength and before it becomes too liquid-like for shaping (i.e. just below its melting point).
  • the hot working temperature of a tin-based solder alloy typically ranges between about 100 0 C - about 150 0 C but is should be noted that the given range may vary according to the actual solder utilized and the determination thereof is within the knowledge of the average skilled person in the art.
  • a first offset of the first or second substrate is carried out.
  • the direction of the offset of one of the two substrates is substantially parallel to the plane of the corresponding substrate on which the at least one solder bump is formed.
  • the direction of the offset is parallel to the plane in which the solder bumps on the second substrate are formed and vice versa.
  • the offset described above may be considered to be lateral in nature, i.e. it may comprise of a movement in either a single direction or in two directions while maintaining the movement in a substantially parallel manner to the plane in which the solder bumps on the second substrate are formed.
  • the plane in which the solder bumps formed on the second substrate is defined by the x-axis and the y- axis.
  • the offset of the first substrate would be parallel to the plane as defined by the x-axis and the y-axis.
  • the offset may be in the x-axis, the y-axis or a combination of both (i.e. a diagonal movement).
  • the first offset results in the elongated solder bump being slanted from its initially substantially vertical orientation.
  • the first offset is followed thereafter by a second offset of the first or second substrate.
  • the direction is that which is substantially perpendicular to the plane of the corresponding substrate on which the at least one bump is formed.
  • the second offset comprises of a vertical movement (unidirectional) that reduces the distance between the first and the second substrates.
  • the second offset of either the first or second substrate may be considered to be a vertical movement in the z-axis, if the plane in which the solder bumps are formed is defined by the x-axis and the y-axis.
  • the slanted elongated solder bump now adopts a free form shape that may be, generically speaking, but is not limited to, an s-shaped curve.
  • the form of the solder bumps after the elongation step i.e. when the at least one single solder bump is elongated with the increasing of the second distance
  • the form of the solder bumps after the elongation step essentially depends upon the subsequent offset movements carried out on the respective substrates.
  • the resulting shape is a two - dimensional (2-D) interconnector having a predominantly s-shaped form imbued with elastic-like properties.
  • the movement during the first offset may be bidirectional, as mentioned earlier.
  • the bidirectional movement may be carried out in a first direction (x-axis direction) followed by the second direction (y-axis direction) or it may be a concurrent movement that results in a diagonal movement.
  • the 2-D interconnector has a planar geometry. When the 2-D interconnector is viewed from the vertical direction (i.e. top view), the interconnector appears as a straight line. This is achieved by a single x-offset, or by a single y-offset, or by a single x-y offset in which the x- y path makes a straight line (i.e. diagonal). Any of the planar offsets described above is sufficient to form a 2-D interconnector.
  • a three-dimensional (3-D) interconnector may be formed.
  • the three dimensional interconnector typically comprises of, but is not limited to, a helix-like shape that also includes elastic-like properties as the 2-D interconnector.
  • a 3-D interconnector as the name implies, has a three-dimensional geometry instead of the planar or two- dimensional geometry of the 2-D interconnector.
  • the three- dimensional geometry may be formed simply by carrying out an offset in the x-axis direction, followed by an offset in the y-axis direction.
  • the x-offset and y-offset may be either sequential or simultaneous.
  • the sequential or simultaneous offset may cause the resultant shape to be different.
  • the x-y offset is then followed by an offset in the z-axis direction. Again, the z- offset may be sequential or simultaneous with the x-y offset.
  • a further embodiment of the invention is as follows: If the x-y displacement is simultaneous and makes a circular path, i.e. a circle within a particular plane, such as the x-y plane, while a z-offset is also applied downwards (in the z-axis direction), then a 3-D spiral spring is formed.
  • the shaping of the interconnectors is advantageous in that the compliance of the interconnector, for example, a helical spring, is greater than the compliance of a sphere. This increase in compliance increases in turn the reliability of the interconnectors during thermal cycling and drop impact.
  • a variety of shapes may be formed such that said shapes display "spring-like" properties.
  • the hot-worked elongated solder bump is cooled.
  • the hot- worked elongated solder bump is essentially cooled down from its hot working temperature to room temperature, for example.
  • the cooling of the solder may be carried out by air cooling, for example.
  • the final step in the fabrication process is the separation of the hot worked elongated solder bump (either a 2-D or 3-D interconnector) from the first or second substrate.
  • the separation process is typically carried out by mechanical means by increasing the distance between the substrates till one end of the interconnectors detaches from the dummy substrate to which it is attached to, thereby leaving the interconnector with one end attached to the functional substrate and the other being a free end.
  • the two substrates may be moved with respect to each other such that a shear force is introduced at the junction of the interconnector and the dummy substrate.
  • the separation can also carried out using chemical separation techniques.
  • the degree of adhesion may be affected. This may for example be achieved, as mentioned previously, by modifying the surface morphology of the dummy substrate, or by modifying the microstructure of the interconnector-dummy substrate interface.
  • the second substrate includes at least one solder-wettable pad.
  • all the above-mentioned steps of forming the interconnector on the first substrate are performed in the same manner and sequence except that a solder-wettable pad is used instead of the at least one second solder bump.
  • Another method that aids in the separation of the solder bump from the dummy substrate includes reducing the contact area between the solder bump and the dummy wafer. This may be achieved by having the contact area to be an annular area instead of a circular area as in a conventional joint, for example.
  • the type of second substrate used in the method according to the present invention depends upon the context to which the method, as described above, is applied to. There are at least two possible applications.
  • the first substrate is a wafer or a matrix of IC packages (typically CSP) and the second substrate is a dummy wafer, as described above, for the sole purpose of shaping (stretching and forming) the interconnector.
  • the shaped interconnectors are then separated from the second substrate (dummy substrate) leaving the shaped interconnectors in a free-standing form on the first substrate.
  • This first substrate may be subsequently singularized into individual components that are capable of being mounted onto a functional substrate such as PCB, for example.
  • the dummy substrate is typically formed of high temperature- resistance materials that allow the interconnector materials, which have a higher melting temperature than conventional solder alloys, to adhere and detach from the dummy substrate.
  • the dummy substrate may be made of high temperature materials such as a silicon wafer (without an IC) or a stainless steel wafer.
  • a wide selection of materials may be used as solder bumps to form the interconnectors. Examples of such solder bumps, as mentioned above, include, but are not limited to 95PbIOSn (melting temperature of 320 0 C) and Sn3.0Cu (melting temperature of 300 0 C).
  • any temperature can be used to attach the solder bump to the first (and second substrate) and to elongate the interconnector as long as it does not cause damage to either of the substrates and the type of solder used is chosen according to the melting points of the respective substrates and metallization present thereon.
  • the melting temperature of the solder bump is typically not be more than about 500 0 C.
  • the melting temperature of the solder bump maybe as high as 800 0 C.
  • solder bumps As such, it is possible to use a tin-based solder alloy having a melting point as low as 220 0 C for the silicon wafer with aluminum metallization and a having a tin-based solder alloy having a melting point as high as 800 0 C for the silicon substrate with copper metallization, for example. Accordingly, there are numerous metal alloys that are available for use as solder bumps.
  • the first substrate is typically an IC component and the second substrate is typically a functional substrate, such as a PCB, for example, hi this case, the shaped interconnector is typically not separated from the second (or functional) substrate unlike the first application described above.
  • Figure IA illustrates the bending effect on an interconnector due to drop impact
  • Figure IB illustrates the effect of thermal cycling on a solder interconnector
  • Figure 2 shows a fabrication process for mounting an electrical component onto a functional substrate using an epoxy underfill according to the prior art
  • Figure 3 illustrates the fabrication process for an electrical component onto a functional substrate and shaping the interconnectors according to the present invention
  • Figure 4 shows a scanning electron microscope (SEM) image of a 2-D interconnector fabricated according to the present invention.
  • Figure 5 shows an alternative embodiment of the method of fabrication.
  • Figure IA illustrates the bending effect on an interconnector 10 due to drop impact.
  • Drop-impacts result when a device, traveling with a velocity, impacts a rigid surface resulting in the velocity of the device being reduced to zero over a short period of time.
  • the PCB assembly within the device continues with its motion for a longer time, resulting in a flexing of the PCB assembly. Due to different boundary conditions, the PCB, and the IC components mounted thereon, undergoes differential flexing and this results in stresses being exerted on the electrical interconnectors, which may ultimately lead to failure thereof.
  • Figure IB illustrates the effect of thermal cycling on a solder interconnector 12.
  • Thermal cycling of a microelectronics package may happen when the temperature of the microelectronics package itself changes cyclically such that the package (and its constituting elements) undergoes cyclic thermal expansion (or contraction).
  • the constituting elements of the microelectronics package are made of different materials; said constituting elements may each have a differing thermal coefficient of expansion. Accordingly, the differing thermal coefficient of expansion gives rise to a thermal mismatch between the different constituting elements of the microelectronics package.
  • the effects of the thermal mismatch may be illustrated when the substrate expands at a higher rate than the mounted electrical component. In such an exemplary illustration, the interconnector 12 between the substrate and the electrical component experiences a shear force which may result in the shearing of the interconnector.
  • FIG. 2 shows the fabrication process using an epoxy underfill as described in the prior art.
  • step (1) the functional substrate 21 is dry baked via heating means 22 before the placement of the electrical component 23, which already has the attached solder bump 25, in step (2) onto the substrate 21 using a holder 24 .
  • the solder interconnectors 25 are heated and form joints with the substrate 21.
  • step (3) the thermosetting epoxy underfill 29 is placed around the interconnectors 25 so as to support said interconnectors 25.
  • the final step involves the curing of the underfill 29 by the application of heat via the heating means 22, as shown in step (4).
  • FIG 3 illustrates the fabrication process for an interconnector according to the method of the present invention
  • the electrical component 33 which already has the attached solder bumps 35
  • the electrical component is placed onto a functional substrate 31 using a holder 34.
  • the solder bumps 35 are heated and form joints with the substrate 31.
  • the electrical component is given a vertical upward displacement (I) that results in the elongation of the interconnectors 36, which are in the molten state.
  • the temperature is then reduced to below the melting temperature of the interconnectors 36 but above the cold working temperature of the interconnectors 36.
  • II horizontal displacement
  • Step (2b) and step (2c) are alternatives to step (2a).
  • Step (2b) is identical to step (2a) up to the horizontal displacement (II), which is followed by a vertical downward displacement (III) applied to the electrical component 33 leading to a 2-D S-shaped spring interconnector 37.
  • Step (2c) is identical to step (2a) up to the vertical upward displacement (I); this is followed by a spiral displacement (or helix displacement) (IV) to the electrical component 33 leading to the formation of a 3-D spiral spring interconnector 38.
  • Figure 4 shows a scanning electron microscope (SEM) image of a 2-D interconnector fabricated according to the present invention.
  • the interconnector generally has an S-shaped curvature which imparts a degree of elasticity to said interconnector to compensate for the effects of thermal cycling and drop impacts.
  • Step (1) shows a dummy substrate 51 whose surface is pre-treated with either a weak adhesive layer 59 or a sacrificial layer 59 (alternatively, the dummy substrate may have solder bumps).
  • step (2) a functional substrate 53, which contains many electrical devices and already has solder bumps 55 attached thereto, is placed onto the dummy substrate 51 using a holder 54.
  • the solder bumps 55 are heated, via heating means 52, and form joints with the dummy substrate 51.
  • Step (3) illustrates a specific technique for forming 2-D S-shaped interconnectors 56.
  • step (3) the functional substrate is given a vertical upward displacement (I) that results in the elongation of the interconnectors 56 in the molten state, after which, the temperature is then reduced to below the melting temperature of the interconnectors 56 but above the cold working temperature of the interconnectors 56.
  • a horizontal displacement (II) and then a vertical downward displacement (III) of the electrical component.
  • the movements (I) — (III) leads to the formation of 2-D S-shaped interconnectors 56.
  • Step (4) the functional substrate is released from the dummy substrate by either mechanical separation, in the case of a weak adhesion layer 59 or by disintegration, in the case of a sacrificial layer 59.
  • step (5) the functional substrate is singularized into an individual electrical component 57.
  • Step (6) shows the attachment of this electrical component 57 onto a functional substrate 58 using a conductive material 59 that is having lower melting temperature than the material that forms the interconnector 56.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un procédé de fabrication d'une interconnexion permettant de raccorder électriquement un composant électrique à un substrat, ledit procédé comprenant les étapes consistant à utiliser un premier substrat et former sur celui-ci au moins une première perle de brasage ; à utiliser un second substrat et former sur celui-ci au moins une seconde perle de brasage ; à positionner ladite ou lesdites premières et secondes perles de brasage de façon à les aligner de manière positionnelle et angulaire l'une par rapport à l'autre, ladite ou lesdites premières perles de brasage et ladite ou lesdites secondes perles de brasage étant séparées l'une de l'autre par une première distance et les substrats étant séparés l'un de l'autre par une seconde distance ; à chauffer la première perle de brasage et la seconde perle de brasage jusqu'à ce qu'elles fondent ; à réduire la première distance jusqu'à ce que les perles de brasage fondues fusionnent pour constituer au moins une perle de brasage simple ; à maintenir ladite au moins une perle de brasage simple à l'état fondu tout en augmentant la seconde distance entre les deux substrats, rallongeant ainsi ladite au moins une perle de brasage simple et constituant au moins une perle de brasage allongée ; à terminer l'étape d'augmentation de la seconde distance entre les substrats lorsque ladite ou lesdites perles de brasage allongées atteignent un rapport d'allongement désiré ; à réduire la température de ladite au ou desdites perles de brasage allongées jusqu'à leur température d'usinage à chaud et à la maintenir à ladite température d'usinage à chaud ; à réaliser un premier décalage du premier ou du second substrat dans une direction sensiblement parallèle au plan du substrat correspondant sur lequel ladite ou lesdites perles sont formées; à réaliser un second décalage du premier ou du second substrat dans une direction sensiblement perpendiculaire à la direction sensiblement parallèles au plan du substrat correspondant sur lequel ladite ou lesdites perles sont formées pour ainsi réduire la seconde distance séparant le premier et le second substrats ; à abaisser la température de ladite ou desdites perles de brasage allongées usinées à chaud ; à séparer ladite ou lesdites perles de brasage allongées usinées à chaud du premier ou du second substrat.
PCT/SG2006/000080 2006-03-31 2006-03-31 procédé de fabrication d'une interconnexion permettant de raccorder électriquement un composant électrique à un substrat WO2007114790A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/SG2006/000080 WO2007114790A1 (fr) 2006-03-31 2006-03-31 procédé de fabrication d'une interconnexion permettant de raccorder électriquement un composant électrique à un substrat

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SG2006/000080 WO2007114790A1 (fr) 2006-03-31 2006-03-31 procédé de fabrication d'une interconnexion permettant de raccorder électriquement un composant électrique à un substrat

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109803484A (zh) * 2019-01-10 2019-05-24 东华大学 一种织物电路板与电子元器件的可拆卸连接方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996017378A1 (fr) * 1994-11-15 1996-06-06 Formfactor, Inc. Structures de contact electrique obtenues par configuration d'un fil souple
US20030176083A1 (en) * 2002-03-18 2003-09-18 Che-Yu Li Test and burn-in connector
US6953707B2 (en) * 2003-05-28 2005-10-11 Texas Instruments Incorporated Method and system for chip-to-package interconnection

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996017378A1 (fr) * 1994-11-15 1996-06-06 Formfactor, Inc. Structures de contact electrique obtenues par configuration d'un fil souple
US20030176083A1 (en) * 2002-03-18 2003-09-18 Che-Yu Li Test and burn-in connector
US6953707B2 (en) * 2003-05-28 2005-10-11 Texas Instruments Incorporated Method and system for chip-to-package interconnection

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109803484A (zh) * 2019-01-10 2019-05-24 东华大学 一种织物电路板与电子元器件的可拆卸连接方法
CN109803484B (zh) * 2019-01-10 2021-07-02 东华大学 一种织物电路板与电子元器件的可拆卸连接方法

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